From: Vidya Sagar Date: Tue, 24 Mar 2026 19:09:53 +0000 (+0530) Subject: PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode X-Git-Tag: v7.1-rc1~151^2~4^2~5 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=f50e0c7d57b08dfbd6a2aab1eed8f99dd8e81377;p=thirdparty%2Flinux.git PCI: tegra194: Calibrate pipe to UPHY for Endpoint mode Calibrate 'Pipe to Universal PHY(UPHY)' (P2U) for the Endpoint controller to request UPHY PLL rate change to 2.5GT/s (Gen 1) during initialization. This helps to reset stale PLL state from the previous bad link state. Signed-off-by: Vidya Sagar Signed-off-by: Manikanta Maddireddy Signed-off-by: Manivannan Sadhasivam Signed-off-by: Bjorn Helgaas Tested-by: Jon Hunter Reviewed-by: Jon Hunter Reviewed-by: Vidya Sagar Link: https://patch.msgid.link/20260324191000.1095768-3-mmaddireddy@nvidia.com --- diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c index 002945de5e117..7f74d72a21dd3 100644 --- a/drivers/pci/controller/dwc/pcie-tegra194.c +++ b/drivers/pci/controller/dwc/pcie-tegra194.c @@ -1072,6 +1072,9 @@ static int tegra_pcie_enable_phy(struct tegra_pcie_dw *pcie) ret = phy_power_on(pcie->phys[i]); if (ret < 0) goto phy_exit; + + if (pcie->of_data->mode == DW_PCIE_EP_TYPE) + phy_calibrate(pcie->phys[i]); } return 0;