From: Michal Simek Date: Tue, 25 Sep 2012 08:43:12 +0000 (+0200) Subject: zynq: Clear reboot status register 0x0F000000 bits X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=f6071d0902467e9d2db7e3867f933e2d88548ce8;p=thirdparty%2Fu-boot.git zynq: Clear reboot status register 0x0F000000 bits FSBL check the reboot status register 0x0F000000 bits to decide which the partition it should work on. If the bitstream is presented in the partition, it programs the bistream. This commit is a temporary workaround to reload the bitstream after uboot reset. Signed-off-by: Jason Wu Signed-off-by: Michal Simek --- diff --git a/board/xilinx/zynq_common/board.c b/board/xilinx/zynq_common/board.c index 54a109a8e75..ad8f0592299 100644 --- a/board/xilinx/zynq_common/board.c +++ b/board/xilinx/zynq_common/board.c @@ -157,6 +157,11 @@ void reset_cpu(ulong addr) /* unlock SLCR */ *(slcr_p + 2) = 0xDF0D; + /* Clear 0x0F000000 bits of reboot status register to workaround + * the FSBL not loading the bitstream after soft reset + * This is a temporary solution until we know more. + */ + XIo_Out32(XPSS_SYS_CTRL_BASEADDR + 0x258, (XIo_In32(XPSS_SYS_CTRL_BASEADDR + 0x258) & 0xF0FFFFFF)); /* Tickle soft reset bit */ *(slcr_p + 128) = 1;