From: Sasha Levin Date: Thu, 27 Jun 2024 14:07:04 +0000 (-0400) Subject: Fixes for 5.10 X-Git-Tag: v4.19.317~147 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=f94d4927aa225e2ed4ef0d609eed780f6242ab52;p=thirdparty%2Fkernel%2Fstable-queue.git Fixes for 5.10 Signed-off-by: Sasha Levin --- diff --git a/queue-5.10/input-ili210x-fix-ili251x_read_touch_data-return-val.patch b/queue-5.10/input-ili210x-fix-ili251x_read_touch_data-return-val.patch new file mode 100644 index 00000000000..107b4a1a639 --- /dev/null +++ b/queue-5.10/input-ili210x-fix-ili251x_read_touch_data-return-val.patch @@ -0,0 +1,41 @@ +From fb3f3c239496adb23b4a8a5ecd8584fdf34a2269 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 23 May 2024 09:56:24 +0100 +Subject: Input: ili210x - fix ili251x_read_touch_data() return value + +From: John Keeping + +[ Upstream commit 9f0fad0382124e7e23b3c730fa78818c22c89c0a ] + +The caller of this function treats all non-zero values as an error, so +the return value of i2c_master_recv() cannot be returned directly. + +This fixes touch reporting when there are more than 6 active touches. + +Fixes: ef536abd3afd1 ("Input: ili210x - define and use chip operations structure") +Signed-off-by: John Keeping +Link: https://lore.kernel.org/r/20240523085624.2295988-1-jkeeping@inmusicbrands.com +Signed-off-by: Dmitry Torokhov +Signed-off-by: Sasha Levin +--- + drivers/input/touchscreen/ili210x.c | 4 ++-- + 1 file changed, 2 insertions(+), 2 deletions(-) + +diff --git a/drivers/input/touchscreen/ili210x.c b/drivers/input/touchscreen/ili210x.c +index f437eefec94ad..9452a12ddb096 100644 +--- a/drivers/input/touchscreen/ili210x.c ++++ b/drivers/input/touchscreen/ili210x.c +@@ -231,8 +231,8 @@ static int ili251x_read_touch_data(struct i2c_client *client, u8 *data) + if (!error && data[0] == 2) { + error = i2c_master_recv(client, data + ILI251X_DATA_SIZE1, + ILI251X_DATA_SIZE2); +- if (error >= 0 && error != ILI251X_DATA_SIZE2) +- error = -EIO; ++ if (error >= 0) ++ error = error == ILI251X_DATA_SIZE2 ? 0 : -EIO; + } + + return error; +-- +2.43.0 + diff --git a/queue-5.10/pinctrl-fix-deadlock-in-create_pinctrl-when-handling.patch b/queue-5.10/pinctrl-fix-deadlock-in-create_pinctrl-when-handling.patch new file mode 100644 index 00000000000..8e86bba1d64 --- /dev/null +++ b/queue-5.10/pinctrl-fix-deadlock-in-create_pinctrl-when-handling.patch @@ -0,0 +1,48 @@ +From 440443f1af896188ebd3c1eb27988bccfda0acbe Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Tue, 4 Jun 2024 08:58:38 +0000 +Subject: pinctrl: fix deadlock in create_pinctrl() when handling -EPROBE_DEFER + +From: Hagar Hemdan + +[ Upstream commit adec57ff8e66aee632f3dd1f93787c13d112b7a1 ] + +In create_pinctrl(), pinctrl_maps_mutex is acquired before calling +add_setting(). If add_setting() returns -EPROBE_DEFER, create_pinctrl() +calls pinctrl_free(). However, pinctrl_free() attempts to acquire +pinctrl_maps_mutex, which is already held by create_pinctrl(), leading to +a potential deadlock. + +This patch resolves the issue by releasing pinctrl_maps_mutex before +calling pinctrl_free(), preventing the deadlock. + +This bug was discovered and resolved using Coverity Static Analysis +Security Testing (SAST) by Synopsys, Inc. + +Fixes: 42fed7ba44e4 ("pinctrl: move subsystem mutex to pinctrl_dev struct") +Suggested-by: Maximilian Heyne +Signed-off-by: Hagar Hemdan +Link: https://lore.kernel.org/r/20240604085838.3344-1-hagarhem@amazon.com +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/core.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/core.c b/drivers/pinctrl/core.c +index ee99dc56c5448..3d44d6f48cc4c 100644 +--- a/drivers/pinctrl/core.c ++++ b/drivers/pinctrl/core.c +@@ -1092,8 +1092,8 @@ static struct pinctrl *create_pinctrl(struct device *dev, + * an -EPROBE_DEFER later, as that is the worst case. + */ + if (ret == -EPROBE_DEFER) { +- pinctrl_free(p, false); + mutex_unlock(&pinctrl_maps_mutex); ++ pinctrl_free(p, false); + return ERR_PTR(ret); + } + } +-- +2.43.0 + diff --git a/queue-5.10/pinctrl-rockchip-fix-pinmux-bits-for-rk3328-gpio2-b-.patch b/queue-5.10/pinctrl-rockchip-fix-pinmux-bits-for-rk3328-gpio2-b-.patch new file mode 100644 index 00000000000..5f9748dae0d --- /dev/null +++ b/queue-5.10/pinctrl-rockchip-fix-pinmux-bits-for-rk3328-gpio2-b-.patch @@ -0,0 +1,69 @@ +From a880632203ead4e826b0f85e5b251a89afbfb7e9 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jun 2024 20:57:52 +0800 +Subject: pinctrl: rockchip: fix pinmux bits for RK3328 GPIO2-B pins + +From: Huang-Huang Bao + +[ Upstream commit e8448a6c817c2aa6c6af785b1d45678bd5977e8d ] + +The pinmux bits for GPIO2-B0 to GPIO2-B6 actually have 2 bits width, +correct the bank flag for GPIO2-B. The pinmux bits for GPIO2-B7 is +recalculated so it remain unchanged. + +The pinmux bits for those pins are not explicitly specified in RK3328 +TRM, however we can get hint from pad name and its correspinding IOMUX +setting for pins in interface descriptions. The correspinding IOMIX +settings for GPIO2-B0 to GPIO2-B6 can be found in the same row next to +occurrences of following pad names in RK3328 TRM. + +GPIO2-B0: IO_SPIclkm0_GPIO2B0vccio5 +GPIO2-B1: IO_SPItxdm0_GPIO2B1vccio5 +GPIO2-B2: IO_SPIrxdm0_GPIO2B2vccio5 +GPIO2-B3: IO_SPIcsn0m0_GPIO2B3vccio5 +GPIO2-B4: IO_SPIcsn1m0_FLASHvol_sel_GPIO2B4vccio5 +GPIO2-B5: IO_ I2C2sda_TSADCshut_GPIO2B5vccio5 +GPIO2-B6: IO_ I2C2scl_GPIO2B6vccio5 + +This fix has been tested on NanoPi R2S for fixing confliting pinmux bits +between GPIO2-B7 with GPIO2-B5. + +Signed-off-by: Huang-Huang Bao +Reviewed-by: Heiko Stuebner +Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support") +Link: https://lore.kernel.org/r/20240606125755.53778-2-i@eh5.me +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/pinctrl-rockchip.c | 8 +------- + 1 file changed, 1 insertion(+), 7 deletions(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 2a454098eaaa5..afa7055114370 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -800,12 +800,6 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { + + static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { + { +- .num = 2, +- .pin = 12, +- .reg = 0x24, +- .bit = 8, +- .mask = 0x3 +- }, { + .num = 2, + .pin = 15, + .reg = 0x28, +@@ -3882,7 +3876,7 @@ static struct rockchip_pin_bank rk3328_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(1, 32, "gpio1", 0, 0, 0, 0), + PIN_BANK_IOMUX_FLAGS(2, 32, "gpio2", 0, +- IOMUX_WIDTH_3BIT, ++ 0, + IOMUX_WIDTH_3BIT, + 0), + PIN_BANK_IOMUX_FLAGS(3, 32, "gpio3", +-- +2.43.0 + diff --git a/queue-5.10/pinctrl-rockchip-fix-pinmux-bits-for-rk3328-gpio3-b-.patch b/queue-5.10/pinctrl-rockchip-fix-pinmux-bits-for-rk3328-gpio3-b-.patch new file mode 100644 index 00000000000..9b91ec0dc2b --- /dev/null +++ b/queue-5.10/pinctrl-rockchip-fix-pinmux-bits-for-rk3328-gpio3-b-.patch @@ -0,0 +1,111 @@ +From 9a954342511a93ce47344a2f2adb70c0a32dd930 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jun 2024 20:57:53 +0800 +Subject: pinctrl: rockchip: fix pinmux bits for RK3328 GPIO3-B pins + +From: Huang-Huang Bao + +[ Upstream commit 5ef6914e0bf578357b4c906ffe6b26e7eedb8ccf ] + +The pinmux bits for GPIO3-B1 to GPIO3-B6 pins are not explicitly +specified in RK3328 TRM, however we can get hint from pad name and its +correspinding IOMUX setting for pins in interface descriptions. The +correspinding IOMIX settings for these pins can be found in the same +row next to occurrences of following pad names in RK3328 TRM. + +GPIO3-B1: IO_TSPd5m0_CIFdata5m0_GPIO3B1vccio6 +GPIO3-B2: IO_TSPd6m0_CIFdata6m0_GPIO3B2vccio6 +GPIO3-B3: IO_TSPd7m0_CIFdata7m0_GPIO3B3vccio6 +GPIO3-B4: IO_CARDclkm0_GPIO3B4vccio6 +GPIO3-B5: IO_CARDrstm0_GPIO3B5vccio6 +GPIO3-B6: IO_CARDdetm0_GPIO3B6vccio6 + +Add pinmux data to rk3328_mux_recalced_data as mux register offset for +these pins does not follow rockchip convention. + +Signed-off-by: Huang-Huang Bao +Reviewed-by: Heiko Stuebner +Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support") +Link: https://lore.kernel.org/r/20240606125755.53778-3-i@eh5.me +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/pinctrl-rockchip.c | 51 ++++++++++++++++++++++++++++++ + 1 file changed, 51 insertions(+) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index afa7055114370..ad51f84d5e81f 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -800,17 +800,68 @@ static struct rockchip_mux_recalced_data rk3308_mux_recalced_data[] = { + + static struct rockchip_mux_recalced_data rk3328_mux_recalced_data[] = { + { ++ /* gpio2_b7_sel */ + .num = 2, + .pin = 15, + .reg = 0x28, + .bit = 0, + .mask = 0x7 + }, { ++ /* gpio2_c7_sel */ + .num = 2, + .pin = 23, + .reg = 0x30, + .bit = 14, + .mask = 0x3 ++ }, { ++ /* gpio3_b1_sel */ ++ .num = 3, ++ .pin = 9, ++ .reg = 0x44, ++ .bit = 2, ++ .mask = 0x3 ++ }, { ++ /* gpio3_b2_sel */ ++ .num = 3, ++ .pin = 10, ++ .reg = 0x44, ++ .bit = 4, ++ .mask = 0x3 ++ }, { ++ /* gpio3_b3_sel */ ++ .num = 3, ++ .pin = 11, ++ .reg = 0x44, ++ .bit = 6, ++ .mask = 0x3 ++ }, { ++ /* gpio3_b4_sel */ ++ .num = 3, ++ .pin = 12, ++ .reg = 0x44, ++ .bit = 8, ++ .mask = 0x3 ++ }, { ++ /* gpio3_b5_sel */ ++ .num = 3, ++ .pin = 13, ++ .reg = 0x44, ++ .bit = 10, ++ .mask = 0x3 ++ }, { ++ /* gpio3_b6_sel */ ++ .num = 3, ++ .pin = 14, ++ .reg = 0x44, ++ .bit = 12, ++ .mask = 0x3 ++ }, { ++ /* gpio3_b7_sel */ ++ .num = 3, ++ .pin = 15, ++ .reg = 0x44, ++ .bit = 14, ++ .mask = 0x3 + }, + }; + +-- +2.43.0 + diff --git a/queue-5.10/pinctrl-rockchip-fix-pinmux-reset-in-rockchip_pmx_se.patch b/queue-5.10/pinctrl-rockchip-fix-pinmux-reset-in-rockchip_pmx_se.patch new file mode 100644 index 00000000000..113eae593c0 --- /dev/null +++ b/queue-5.10/pinctrl-rockchip-fix-pinmux-reset-in-rockchip_pmx_se.patch @@ -0,0 +1,42 @@ +From e75f9f47cacd27d978aaa63abed0873513dfbeb5 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jun 2024 20:57:55 +0800 +Subject: pinctrl: rockchip: fix pinmux reset in rockchip_pmx_set + +From: Huang-Huang Bao + +[ Upstream commit 4ea4d4808e342ddf89ba24b93ffa2057005aaced ] + +rockchip_pmx_set reset all pinmuxs in group to 0 in the case of error, +add missing bank data retrieval in that code to avoid setting mux on +unexpected pins. + +Fixes: 14797189b35e ("pinctrl: rockchip: add return value to rockchip_set_mux") +Reviewed-by: Heiko Stuebner +Signed-off-by: Huang-Huang Bao +Link: https://lore.kernel.org/r/20240606125755.53778-5-i@eh5.me +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/pinctrl-rockchip.c | 4 +++- + 1 file changed, 3 insertions(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 7637b25c6edf7..02b41f1bafe71 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -2131,8 +2131,10 @@ static int rockchip_pmx_set(struct pinctrl_dev *pctldev, unsigned selector, + + if (ret) { + /* revert the already done pin settings */ +- for (cnt--; cnt >= 0; cnt--) ++ for (cnt--; cnt >= 0; cnt--) { ++ bank = pin_to_bank(info, pins[cnt]); + rockchip_set_mux(bank, pins[cnt] - bank->pin_base, 0); ++ } + + return ret; + } +-- +2.43.0 + diff --git a/queue-5.10/pinctrl-rockchip-separate-struct-rockchip_pin_bank-t.patch b/queue-5.10/pinctrl-rockchip-separate-struct-rockchip_pin_bank-t.patch new file mode 100644 index 00000000000..6fc9f91d720 --- /dev/null +++ b/queue-5.10/pinctrl-rockchip-separate-struct-rockchip_pin_bank-t.patch @@ -0,0 +1,535 @@ +From 5ab6dfd5ae57175b0b8a7893a0019642185322d0 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Mon, 16 Aug 2021 09:19:41 +0800 +Subject: pinctrl/rockchip: separate struct rockchip_pin_bank to a head file + +From: Jianqun Xu + +[ Upstream commit e1450694e94657458395af886d2467d6ac3355af ] + +Separate struct rockchip_pin_bank to pinctrl-rockchip.h file, which will +be used by gpio-rockchip driver in the future. + +Signed-off-by: Jianqun Xu +Link: https://lore.kernel.org/r/20210816011948.1118959-3-jay.xu@rock-chips.com +Signed-off-by: Linus Walleij +Stable-dep-of: 01b4b1d1cec4 ("pinctrl: rockchip: use dedicated pinctrl type for RK3328") +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/pinctrl-rockchip.c | 226 +------------------------- + drivers/pinctrl/pinctrl-rockchip.h | 245 +++++++++++++++++++++++++++++ + 2 files changed, 246 insertions(+), 225 deletions(-) + create mode 100644 drivers/pinctrl/pinctrl-rockchip.h + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index ad51f84d5e81f..25716bdf5bbe5 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -35,6 +35,7 @@ + + #include "core.h" + #include "pinconf.h" ++#include "pinctrl-rockchip.h" + + /* GPIO control registers */ + #define GPIO_SWPORT_DR 0x00 +@@ -50,21 +51,6 @@ + #define GPIO_EXT_PORT 0x50 + #define GPIO_LS_SYNC 0x60 + +-enum rockchip_pinctrl_type { +- PX30, +- RV1108, +- RK2928, +- RK3066B, +- RK3128, +- RK3188, +- RK3288, +- RK3308, +- RK3368, +- RK3399, +- RK3568, +-}; +- +- + /** + * Generate a bitmask for setting a value (v) with a write mask bit in hiword + * register 31:16 area. +@@ -82,103 +68,6 @@ enum rockchip_pinctrl_type { + #define IOMUX_WIDTH_3BIT BIT(4) + #define IOMUX_WIDTH_2BIT BIT(5) + +-/** +- * struct rockchip_iomux +- * @type: iomux variant using IOMUX_* constants +- * @offset: if initialized to -1 it will be autocalculated, by specifying +- * an initial offset value the relevant source offset can be reset +- * to a new value for autocalculating the following iomux registers. +- */ +-struct rockchip_iomux { +- int type; +- int offset; +-}; +- +-/* +- * enum type index corresponding to rockchip_perpin_drv_list arrays index. +- */ +-enum rockchip_pin_drv_type { +- DRV_TYPE_IO_DEFAULT = 0, +- DRV_TYPE_IO_1V8_OR_3V0, +- DRV_TYPE_IO_1V8_ONLY, +- DRV_TYPE_IO_1V8_3V0_AUTO, +- DRV_TYPE_IO_3V3_ONLY, +- DRV_TYPE_MAX +-}; +- +-/* +- * enum type index corresponding to rockchip_pull_list arrays index. +- */ +-enum rockchip_pin_pull_type { +- PULL_TYPE_IO_DEFAULT = 0, +- PULL_TYPE_IO_1V8_ONLY, +- PULL_TYPE_MAX +-}; +- +-/** +- * struct rockchip_drv +- * @drv_type: drive strength variant using rockchip_perpin_drv_type +- * @offset: if initialized to -1 it will be autocalculated, by specifying +- * an initial offset value the relevant source offset can be reset +- * to a new value for autocalculating the following drive strength +- * registers. if used chips own cal_drv func instead to calculate +- * registers offset, the variant could be ignored. +- */ +-struct rockchip_drv { +- enum rockchip_pin_drv_type drv_type; +- int offset; +-}; +- +-/** +- * struct rockchip_pin_bank +- * @reg_base: register base of the gpio bank +- * @regmap_pull: optional separate register for additional pull settings +- * @clk: clock of the gpio bank +- * @irq: interrupt of the gpio bank +- * @saved_masks: Saved content of GPIO_INTEN at suspend time. +- * @pin_base: first pin number +- * @nr_pins: number of pins in this bank +- * @name: name of the bank +- * @bank_num: number of the bank, to account for holes +- * @iomux: array describing the 4 iomux sources of the bank +- * @drv: array describing the 4 drive strength sources of the bank +- * @pull_type: array describing the 4 pull type sources of the bank +- * @valid: is all necessary information present +- * @of_node: dt node of this bank +- * @drvdata: common pinctrl basedata +- * @domain: irqdomain of the gpio bank +- * @gpio_chip: gpiolib chip +- * @grange: gpio range +- * @slock: spinlock for the gpio bank +- * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode +- * @recalced_mask: bit mask to indicate a need to recalulate the mask +- * @route_mask: bits describing the routing pins of per bank +- */ +-struct rockchip_pin_bank { +- void __iomem *reg_base; +- struct regmap *regmap_pull; +- struct clk *clk; +- int irq; +- u32 saved_masks; +- u32 pin_base; +- u8 nr_pins; +- char *name; +- u8 bank_num; +- struct rockchip_iomux iomux[4]; +- struct rockchip_drv drv[4]; +- enum rockchip_pin_pull_type pull_type[4]; +- bool valid; +- struct device_node *of_node; +- struct rockchip_pinctrl *drvdata; +- struct irq_domain *domain; +- struct gpio_chip gpio_chip; +- struct pinctrl_gpio_range grange; +- raw_spinlock_t slock; +- u32 toggle_edge_mode; +- u32 recalced_mask; +- u32 route_mask; +-}; +- + #define PIN_BANK(id, pins, label) \ + { \ + .bank_num = id, \ +@@ -318,119 +207,6 @@ struct rockchip_pin_bank { + #define RK_MUXROUTE_PMU(ID, PIN, FUNC, REG, VAL) \ + PIN_BANK_MUX_ROUTE_FLAGS(ID, PIN, FUNC, REG, VAL, ROCKCHIP_ROUTE_PMU) + +-/** +- * struct rockchip_mux_recalced_data: represent a pin iomux data. +- * @num: bank number. +- * @pin: pin number. +- * @bit: index at register. +- * @reg: register offset. +- * @mask: mask bit +- */ +-struct rockchip_mux_recalced_data { +- u8 num; +- u8 pin; +- u32 reg; +- u8 bit; +- u8 mask; +-}; +- +-enum rockchip_mux_route_location { +- ROCKCHIP_ROUTE_SAME = 0, +- ROCKCHIP_ROUTE_PMU, +- ROCKCHIP_ROUTE_GRF, +-}; +- +-/** +- * struct rockchip_mux_recalced_data: represent a pin iomux data. +- * @bank_num: bank number. +- * @pin: index at register or used to calc index. +- * @func: the min pin. +- * @route_location: the mux route location (same, pmu, grf). +- * @route_offset: the max pin. +- * @route_val: the register offset. +- */ +-struct rockchip_mux_route_data { +- u8 bank_num; +- u8 pin; +- u8 func; +- enum rockchip_mux_route_location route_location; +- u32 route_offset; +- u32 route_val; +-}; +- +-struct rockchip_pin_ctrl { +- struct rockchip_pin_bank *pin_banks; +- u32 nr_banks; +- u32 nr_pins; +- char *label; +- enum rockchip_pinctrl_type type; +- int grf_mux_offset; +- int pmu_mux_offset; +- int grf_drv_offset; +- int pmu_drv_offset; +- struct rockchip_mux_recalced_data *iomux_recalced; +- u32 niomux_recalced; +- struct rockchip_mux_route_data *iomux_routes; +- u32 niomux_routes; +- +- void (*pull_calc_reg)(struct rockchip_pin_bank *bank, +- int pin_num, struct regmap **regmap, +- int *reg, u8 *bit); +- void (*drv_calc_reg)(struct rockchip_pin_bank *bank, +- int pin_num, struct regmap **regmap, +- int *reg, u8 *bit); +- int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, +- int pin_num, struct regmap **regmap, +- int *reg, u8 *bit); +-}; +- +-struct rockchip_pin_config { +- unsigned int func; +- unsigned long *configs; +- unsigned int nconfigs; +-}; +- +-/** +- * struct rockchip_pin_group: represent group of pins of a pinmux function. +- * @name: name of the pin group, used to lookup the group. +- * @pins: the pins included in this group. +- * @npins: number of pins included in this group. +- * @data: local pin configuration +- */ +-struct rockchip_pin_group { +- const char *name; +- unsigned int npins; +- unsigned int *pins; +- struct rockchip_pin_config *data; +-}; +- +-/** +- * struct rockchip_pmx_func: represent a pin function. +- * @name: name of the pin function, used to lookup the function. +- * @groups: one or more names of pin groups that provide this function. +- * @ngroups: number of groups included in @groups. +- */ +-struct rockchip_pmx_func { +- const char *name; +- const char **groups; +- u8 ngroups; +-}; +- +-struct rockchip_pinctrl { +- struct regmap *regmap_base; +- int reg_size; +- struct regmap *regmap_pull; +- struct regmap *regmap_pmu; +- struct device *dev; +- struct rockchip_pin_ctrl *ctrl; +- struct pinctrl_desc pctl; +- struct pinctrl_dev *pctl_dev; +- struct rockchip_pin_group *groups; +- unsigned int ngroups; +- struct rockchip_pmx_func *functions; +- unsigned int nfunctions; +-}; +- + static struct regmap_config rockchip_regmap_config = { + .reg_bits = 32, + .val_bits = 32, +diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h +new file mode 100644 +index 0000000000000..dba9e95406337 +--- /dev/null ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -0,0 +1,245 @@ ++/* SPDX-License-Identifier: GPL-2.0-only */ ++/* ++ * Copyright (c) 2020-2021 Rockchip Electronics Co. Ltd. ++ * ++ * Copyright (c) 2013 MundoReader S.L. ++ * Author: Heiko Stuebner ++ * ++ * With some ideas taken from pinctrl-samsung: ++ * Copyright (c) 2012 Samsung Electronics Co., Ltd. ++ * http://www.samsung.com ++ * Copyright (c) 2012 Linaro Ltd ++ * https://www.linaro.org ++ * ++ * and pinctrl-at91: ++ * Copyright (C) 2011-2012 Jean-Christophe PLAGNIOL-VILLARD ++ */ ++ ++#ifndef _PINCTRL_ROCKCHIP_H ++#define _PINCTRL_ROCKCHIP_H ++ ++enum rockchip_pinctrl_type { ++ PX30, ++ RV1108, ++ RK2928, ++ RK3066B, ++ RK3128, ++ RK3188, ++ RK3288, ++ RK3308, ++ RK3368, ++ RK3399, ++ RK3568, ++}; ++ ++/** ++ * struct rockchip_iomux ++ * @type: iomux variant using IOMUX_* constants ++ * @offset: if initialized to -1 it will be autocalculated, by specifying ++ * an initial offset value the relevant source offset can be reset ++ * to a new value for autocalculating the following iomux registers. ++ */ ++struct rockchip_iomux { ++ int type; ++ int offset; ++}; ++ ++/* ++ * enum type index corresponding to rockchip_perpin_drv_list arrays index. ++ */ ++enum rockchip_pin_drv_type { ++ DRV_TYPE_IO_DEFAULT = 0, ++ DRV_TYPE_IO_1V8_OR_3V0, ++ DRV_TYPE_IO_1V8_ONLY, ++ DRV_TYPE_IO_1V8_3V0_AUTO, ++ DRV_TYPE_IO_3V3_ONLY, ++ DRV_TYPE_MAX ++}; ++ ++/* ++ * enum type index corresponding to rockchip_pull_list arrays index. ++ */ ++enum rockchip_pin_pull_type { ++ PULL_TYPE_IO_DEFAULT = 0, ++ PULL_TYPE_IO_1V8_ONLY, ++ PULL_TYPE_MAX ++}; ++ ++/** ++ * struct rockchip_drv ++ * @drv_type: drive strength variant using rockchip_perpin_drv_type ++ * @offset: if initialized to -1 it will be autocalculated, by specifying ++ * an initial offset value the relevant source offset can be reset ++ * to a new value for autocalculating the following drive strength ++ * registers. if used chips own cal_drv func instead to calculate ++ * registers offset, the variant could be ignored. ++ */ ++struct rockchip_drv { ++ enum rockchip_pin_drv_type drv_type; ++ int offset; ++}; ++ ++/** ++ * struct rockchip_pin_bank ++ * @reg_base: register base of the gpio bank ++ * @regmap_pull: optional separate register for additional pull settings ++ * @clk: clock of the gpio bank ++ * @irq: interrupt of the gpio bank ++ * @saved_masks: Saved content of GPIO_INTEN at suspend time. ++ * @pin_base: first pin number ++ * @nr_pins: number of pins in this bank ++ * @name: name of the bank ++ * @bank_num: number of the bank, to account for holes ++ * @iomux: array describing the 4 iomux sources of the bank ++ * @drv: array describing the 4 drive strength sources of the bank ++ * @pull_type: array describing the 4 pull type sources of the bank ++ * @valid: is all necessary information present ++ * @of_node: dt node of this bank ++ * @drvdata: common pinctrl basedata ++ * @domain: irqdomain of the gpio bank ++ * @gpio_chip: gpiolib chip ++ * @grange: gpio range ++ * @slock: spinlock for the gpio bank ++ * @toggle_edge_mode: bit mask to toggle (falling/rising) edge mode ++ * @recalced_mask: bit mask to indicate a need to recalulate the mask ++ * @route_mask: bits describing the routing pins of per bank ++ */ ++struct rockchip_pin_bank { ++ void __iomem *reg_base; ++ struct regmap *regmap_pull; ++ struct clk *clk; ++ int irq; ++ u32 saved_masks; ++ u32 pin_base; ++ u8 nr_pins; ++ char *name; ++ u8 bank_num; ++ struct rockchip_iomux iomux[4]; ++ struct rockchip_drv drv[4]; ++ enum rockchip_pin_pull_type pull_type[4]; ++ bool valid; ++ struct device_node *of_node; ++ struct rockchip_pinctrl *drvdata; ++ struct irq_domain *domain; ++ struct gpio_chip gpio_chip; ++ struct pinctrl_gpio_range grange; ++ raw_spinlock_t slock; ++ u32 toggle_edge_mode; ++ u32 recalced_mask; ++ u32 route_mask; ++}; ++ ++/** ++ * struct rockchip_mux_recalced_data: represent a pin iomux data. ++ * @num: bank number. ++ * @pin: pin number. ++ * @bit: index at register. ++ * @reg: register offset. ++ * @mask: mask bit ++ */ ++struct rockchip_mux_recalced_data { ++ u8 num; ++ u8 pin; ++ u32 reg; ++ u8 bit; ++ u8 mask; ++}; ++ ++enum rockchip_mux_route_location { ++ ROCKCHIP_ROUTE_SAME = 0, ++ ROCKCHIP_ROUTE_PMU, ++ ROCKCHIP_ROUTE_GRF, ++}; ++ ++/** ++ * struct rockchip_mux_recalced_data: represent a pin iomux data. ++ * @bank_num: bank number. ++ * @pin: index at register or used to calc index. ++ * @func: the min pin. ++ * @route_location: the mux route location (same, pmu, grf). ++ * @route_offset: the max pin. ++ * @route_val: the register offset. ++ */ ++struct rockchip_mux_route_data { ++ u8 bank_num; ++ u8 pin; ++ u8 func; ++ enum rockchip_mux_route_location route_location; ++ u32 route_offset; ++ u32 route_val; ++}; ++ ++struct rockchip_pin_ctrl { ++ struct rockchip_pin_bank *pin_banks; ++ u32 nr_banks; ++ u32 nr_pins; ++ char *label; ++ enum rockchip_pinctrl_type type; ++ int grf_mux_offset; ++ int pmu_mux_offset; ++ int grf_drv_offset; ++ int pmu_drv_offset; ++ struct rockchip_mux_recalced_data *iomux_recalced; ++ u32 niomux_recalced; ++ struct rockchip_mux_route_data *iomux_routes; ++ u32 niomux_routes; ++ ++ void (*pull_calc_reg)(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit); ++ void (*drv_calc_reg)(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit); ++ int (*schmitt_calc_reg)(struct rockchip_pin_bank *bank, ++ int pin_num, struct regmap **regmap, ++ int *reg, u8 *bit); ++}; ++ ++struct rockchip_pin_config { ++ unsigned int func; ++ unsigned long *configs; ++ unsigned int nconfigs; ++}; ++ ++/** ++ * struct rockchip_pin_group: represent group of pins of a pinmux function. ++ * @name: name of the pin group, used to lookup the group. ++ * @pins: the pins included in this group. ++ * @npins: number of pins included in this group. ++ * @data: local pin configuration ++ */ ++struct rockchip_pin_group { ++ const char *name; ++ unsigned int npins; ++ unsigned int *pins; ++ struct rockchip_pin_config *data; ++}; ++ ++/** ++ * struct rockchip_pmx_func: represent a pin function. ++ * @name: name of the pin function, used to lookup the function. ++ * @groups: one or more names of pin groups that provide this function. ++ * @ngroups: number of groups included in @groups. ++ */ ++struct rockchip_pmx_func { ++ const char *name; ++ const char **groups; ++ u8 ngroups; ++}; ++ ++struct rockchip_pinctrl { ++ struct regmap *regmap_base; ++ int reg_size; ++ struct regmap *regmap_pull; ++ struct regmap *regmap_pmu; ++ struct device *dev; ++ struct rockchip_pin_ctrl *ctrl; ++ struct pinctrl_desc pctl; ++ struct pinctrl_dev *pctl_dev; ++ struct rockchip_pin_group *groups; ++ unsigned int ngroups; ++ struct rockchip_pmx_func *functions; ++ unsigned int nfunctions; ++}; ++ ++#endif +-- +2.43.0 + diff --git a/queue-5.10/pinctrl-rockchip-use-dedicated-pinctrl-type-for-rk33.patch b/queue-5.10/pinctrl-rockchip-use-dedicated-pinctrl-type-for-rk33.patch new file mode 100644 index 00000000000..df2a1bb64f4 --- /dev/null +++ b/queue-5.10/pinctrl-rockchip-use-dedicated-pinctrl-type-for-rk33.patch @@ -0,0 +1,77 @@ +From b95aee507c6aec6953ca9119e8e16399d6cab937 Mon Sep 17 00:00:00 2001 +From: Sasha Levin +Date: Thu, 6 Jun 2024 20:57:54 +0800 +Subject: pinctrl: rockchip: use dedicated pinctrl type for RK3328 + +From: Huang-Huang Bao + +[ Upstream commit 01b4b1d1cec48ef4c26616c2fc4600b2c9fec05a ] + +rk3328_pin_ctrl uses type of RK3288 which has a hack in +rockchip_pinctrl_suspend and rockchip_pinctrl_resume to restore GPIO6-C6 +at assume, the hack is not applicable to RK3328 as GPIO6 is not even +exist in it. So use a dedicated pinctrl type to skip this hack. + +Fixes: 3818e4a7678e ("pinctrl: rockchip: Add rk3328 pinctrl support") +Reviewed-by: Heiko Stuebner +Signed-off-by: Huang-Huang Bao +Link: https://lore.kernel.org/r/20240606125755.53778-4-i@eh5.me +Signed-off-by: Linus Walleij +Signed-off-by: Sasha Levin +--- + drivers/pinctrl/pinctrl-rockchip.c | 5 ++++- + drivers/pinctrl/pinctrl-rockchip.h | 1 + + 2 files changed, 5 insertions(+), 1 deletion(-) + +diff --git a/drivers/pinctrl/pinctrl-rockchip.c b/drivers/pinctrl/pinctrl-rockchip.c +index 25716bdf5bbe5..7637b25c6edf7 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.c ++++ b/drivers/pinctrl/pinctrl-rockchip.c +@@ -1864,6 +1864,7 @@ static int rockchip_get_pull(struct rockchip_pin_bank *bank, int pin_num) + case RK3188: + case RK3288: + case RK3308: ++ case RK3328: + case RK3368: + case RK3399: + case RK3568: +@@ -1918,6 +1919,7 @@ static int rockchip_set_pull(struct rockchip_pin_bank *bank, + case RK3188: + case RK3288: + case RK3308: ++ case RK3328: + case RK3368: + case RK3399: + case RK3568: +@@ -2239,6 +2241,7 @@ static bool rockchip_pinconf_pull_valid(struct rockchip_pin_ctrl *ctrl, + case RK3188: + case RK3288: + case RK3308: ++ case RK3328: + case RK3368: + case RK3399: + case RK3568: +@@ -3717,7 +3720,7 @@ static struct rockchip_pin_ctrl rk3328_pin_ctrl = { + .pin_banks = rk3328_pin_banks, + .nr_banks = ARRAY_SIZE(rk3328_pin_banks), + .label = "RK3328-GPIO", +- .type = RK3288, ++ .type = RK3328, + .grf_mux_offset = 0x0, + .iomux_recalced = rk3328_mux_recalced_data, + .niomux_recalced = ARRAY_SIZE(rk3328_mux_recalced_data), +diff --git a/drivers/pinctrl/pinctrl-rockchip.h b/drivers/pinctrl/pinctrl-rockchip.h +index dba9e95406337..7263db68d0efe 100644 +--- a/drivers/pinctrl/pinctrl-rockchip.h ++++ b/drivers/pinctrl/pinctrl-rockchip.h +@@ -27,6 +27,7 @@ enum rockchip_pinctrl_type { + RK3188, + RK3288, + RK3308, ++ RK3328, + RK3368, + RK3399, + RK3568, +-- +2.43.0 + diff --git a/queue-5.10/series b/queue-5.10/series index 676139abe80..d6d738b9d44 100644 --- a/queue-5.10/series +++ b/queue-5.10/series @@ -254,3 +254,10 @@ acpi-x86-add-another-system-to-quirk-list-for-forcin.patch acpi-x86-utils-add-cezanne-to-the-list-for-forcing-s.patch acpi-x86-utils-add-picasso-to-the-list-for-forcing-s.patch acpi-x86-force-storaged3enable-on-more-products.patch +input-ili210x-fix-ili251x_read_touch_data-return-val.patch +pinctrl-fix-deadlock-in-create_pinctrl-when-handling.patch +pinctrl-rockchip-fix-pinmux-bits-for-rk3328-gpio2-b-.patch +pinctrl-rockchip-fix-pinmux-bits-for-rk3328-gpio3-b-.patch +pinctrl-rockchip-separate-struct-rockchip_pin_bank-t.patch +pinctrl-rockchip-use-dedicated-pinctrl-type-for-rk33.patch +pinctrl-rockchip-fix-pinmux-reset-in-rockchip_pmx_se.patch