From: Srinivas Kandagatla Date: Fri, 13 Mar 2026 10:38:18 +0000 (+0000) Subject: arm64: dts: qcom: monaco: add dt entry for lpass lpi pinctrl X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=faf08fd43411d8ebcc30bd96a05ac4aa31aac66b;p=thirdparty%2Fkernel%2Fstable.git arm64: dts: qcom: monaco: add dt entry for lpass lpi pinctrl Add LPASS LPI pinctrl node used for setting MI2S and soundwire pin configs. Co-developed-by: Loic Poulain Signed-off-by: Loic Poulain Signed-off-by: Srinivas Kandagatla Reviewed-by: Dmitry Baryshkov Reviewed-by: Konrad Dybcio Link: https://lore.kernel.org/r/20260313103824.2634519-4-srinivas.kandagatla@oss.qualcomm.com Signed-off-by: Bjorn Andersson --- diff --git a/arch/arm64/boot/dts/qcom/monaco.dtsi b/arch/arm64/boot/dts/qcom/monaco.dtsi index 4abdfb567d15..2a0d237b37dd 100644 --- a/arch/arm64/boot/dts/qcom/monaco.dtsi +++ b/arch/arm64/boot/dts/qcom/monaco.dtsi @@ -21,6 +21,7 @@ #include #include #include +#include #include / { @@ -2872,6 +2873,20 @@ }; }; + lpass_tlmm: pinctrl@3440000 { + compatible = "qcom,qcs8300-lpass-lpi-pinctrl", "qcom,sm8450-lpass-lpi-pinctrl"; + reg = <0x0 0x03440000 0x0 0x20000>, + <0x0 0x034d0000 0x0 0x10000>; + + clocks = <&q6prmcc LPASS_HW_MACRO_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>, + <&q6prmcc LPASS_HW_DCODEC_VOTE LPASS_CLK_ATTRIBUTE_COUPLE_NO>; + clock-names = "core", "audio"; + + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&lpass_tlmm 0 0 23>; + }; + lpass_ag_noc: interconnect@3c40000 { compatible = "qcom,qcs8300-lpass-ag-noc"; reg = <0x0 0x03c40000 0x0 0x17200>;