From: Shawn Guo <shawn.guo@linaro.org>
Date: Wed, 3 Mar 2021 03:31:06 +0000 (+0800)
Subject: arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'
X-Git-Tag: v5.12.4~478
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=fc474a743e6b7f064cfdadca79e605ce876dcbe1;p=thirdparty%2Fkernel%2Fstable.git

arm64: dts: qcom: sm8350: fix number of pins in 'gpio-ranges'

[ Upstream commit 790158579c8e663081e7d708d57e8ac6d69dca4e ]

The last cell of 'gpio-ranges' should be number of GPIO pins, and in
case of qcom platform it should match msm_pinctrl_soc_data.ngpio rather
than msm_pinctrl_soc_data.ngpio - 1.

This fixes the problem that when the last GPIO pin in the range is
configured with the following call sequence, it always fails with
-EPROBE_DEFER.

    pinctrl_gpio_set_config()
        pinctrl_get_device_gpio_range()
            pinctrl_match_gpio_range()

Fixes: b7e8f433a673 ("arm64: dts: qcom: Add basic devicetree support for SM8350 SoC")
Cc: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Link: https://lore.kernel.org/r/20210303033106.549-5-shawn.guo@linaro.org
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
---

diff --git a/arch/arm64/boot/dts/qcom/sm8350.dtsi b/arch/arm64/boot/dts/qcom/sm8350.dtsi
index e8bf3f95c674c..e2fca420e5183 100644
--- a/arch/arm64/boot/dts/qcom/sm8350.dtsi
+++ b/arch/arm64/boot/dts/qcom/sm8350.dtsi
@@ -382,7 +382,7 @@
 			#gpio-cells = <2>;
 			interrupt-controller;
 			#interrupt-cells = <2>;
-			gpio-ranges = <&tlmm 0 0 203>;
+			gpio-ranges = <&tlmm 0 0 204>;
 
 			qup_uart3_default_state: qup-uart3-default-state {
 				rx {