From: Alex Bee Date: Sun, 19 Nov 2023 12:13:40 +0000 (+0100) Subject: ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK3128 X-Git-Tag: v6.8-rc1~130^2~27^2~18 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=fd610e604837936440ef7c64ab6998b004631647;p=thirdparty%2Fkernel%2Fstable.git ARM: dts: rockchip: Make usbphy the parent of SCLK_USB480M for RK3128 Without setting the parent for SCLK_USB480M the clock will use xin24m as it's default parent. While this is generally not an issue for the usb blocks to work, it becomes an issue for RK3128 since SCLK_USB480M can be a parent for other HW blocks (GPU, VPU, VIO), but they will never chose it, since it is currently always running at OSC frequency which is to slow for their needs. This sets the usb2 phy's output as SCLK_USB480M's parent and it's users can chose it if desired. Signed-off-by: Alex Bee Link: https://lore.kernel.org/r/20231119121340.109025-6-knaerzche@gmail.com Signed-off-by: Heiko Stuebner --- diff --git a/arch/arm/boot/dts/rockchip/rk3128.dtsi b/arch/arm/boot/dts/rockchip/rk3128.dtsi index b5dac13226312..4e8b38604ecd4 100644 --- a/arch/arm/boot/dts/rockchip/rk3128.dtsi +++ b/arch/arm/boot/dts/rockchip/rk3128.dtsi @@ -266,6 +266,8 @@ clocks = <&cru SCLK_OTGPHY0>; clock-names = "phyclk"; clock-output-names = "usb480m_phy"; + assigned-clocks = <&cru SCLK_USB480M>; + assigned-clock-parents = <&usb2phy>; #clock-cells = <0>; status = "disabled";