From: Anand Moon Date: Mon, 25 Aug 2025 06:51:42 +0000 (+0530) Subject: arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC X-Git-Tag: v6.18-rc1~147^2~10^2~12 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=fd7b48b1f91e1830e22e73744e7525af24d8ae25;p=thirdparty%2Flinux.git arm64: dts: amlogic: Add cache information to the Amlogic SM1 SoC As per S905X3 datasheet add missing cache information to the Amlogic SM1 SoC. ARM Cortex-A55 CPU uses unified L3 cache instead of L2 cache. - Each Cortex-A55 core has 32KB of L1 instruction cache available and 32KB of L1 data cache available. - Along with 256KB Unified L2 cache. Cache memory significantly reduces the time it takes for the CPU to access data and instructions, leading to faster program execution and overall system responsiveness. Signed-off-by: Anand Moon Link: https://lore.kernel.org/r/20250825065240.22577-3-linux.amoon@gmail.com Signed-off-by: Neil Armstrong --- diff --git a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi index 966ebb19cc55f..e5db8ce940620 100644 --- a/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi +++ b/arch/arm64/boot/dts/amlogic/meson-sm1.dtsi @@ -55,6 +55,12 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x0>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -64,6 +70,12 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x1>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -73,6 +85,12 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x2>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -82,6 +100,12 @@ compatible = "arm,cortex-a55"; reg = <0x0 0x3>; enable-method = "psci"; + d-cache-line-size = <32>; + d-cache-size = <0x8000>; + d-cache-sets = <32>; + i-cache-line-size = <32>; + i-cache-size = <0x8000>; + i-cache-sets = <32>; next-level-cache = <&l2>; #cooling-cells = <2>; }; @@ -90,6 +114,9 @@ compatible = "cache"; cache-level = <2>; cache-unified; + cache-size = <0x40000>; /* L2. 256 KB */ + cache-line-size = <64>; + cache-sets = <256>; }; };