From: Greg Kroah-Hartman Date: Tue, 13 Aug 2024 06:19:13 +0000 (+0200) Subject: drop queue-6.1/parisc-fix-a-possible-dma-corruption.patch X-Git-Tag: v6.1.105~24 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=fe24afaead10d8f3941f8c4029c8943e980ab25c;p=thirdparty%2Fkernel%2Fstable-queue.git drop queue-6.1/parisc-fix-a-possible-dma-corruption.patch --- diff --git a/queue-6.1/parisc-fix-a-possible-dma-corruption.patch b/queue-6.1/parisc-fix-a-possible-dma-corruption.patch deleted file mode 100644 index 81998074f28..00000000000 --- a/queue-6.1/parisc-fix-a-possible-dma-corruption.patch +++ /dev/null @@ -1,62 +0,0 @@ -From 7ae04ba36b381bffe2471eff3a93edced843240f Mon Sep 17 00:00:00 2001 -From: Mikulas Patocka -Date: Sat, 27 Jul 2024 20:22:52 +0200 -Subject: parisc: fix a possible DMA corruption - -From: Mikulas Patocka - -commit 7ae04ba36b381bffe2471eff3a93edced843240f upstream. - -ARCH_DMA_MINALIGN was defined as 16 - this is too small - it may be -possible that two unrelated 16-byte allocations share a cache line. If -one of these allocations is written using DMA and the other is written -using cached write, the value that was written with DMA may be -corrupted. - -This commit changes ARCH_DMA_MINALIGN to be 128 on PA20 and 32 on PA1.1 - -that's the largest possible cache line size. - -As different parisc microarchitectures have different cache line size, we -define arch_slab_minalign(), cache_line_size() and -dma_get_cache_alignment() so that the kernel may tune slab cache -parameters dynamically, based on the detected cache line size. - -Signed-off-by: Mikulas Patocka -Cc: stable@vger.kernel.org -Signed-off-by: Helge Deller -Signed-off-by: Greg Kroah-Hartman ---- - arch/parisc/Kconfig | 1 + - arch/parisc/include/asm/cache.h | 11 ++++++++++- - 2 files changed, 11 insertions(+), 1 deletion(-) - ---- a/arch/parisc/Kconfig -+++ b/arch/parisc/Kconfig -@@ -18,6 +18,7 @@ config PARISC - select ARCH_SUPPORTS_HUGETLBFS if PA20 - select ARCH_SUPPORTS_MEMORY_FAILURE - select ARCH_STACKWALK -+ select ARCH_HAS_CACHE_LINE_SIZE - select ARCH_HAS_DEBUG_VM_PGTABLE - select HAVE_RELIABLE_STACKTRACE - select DMA_OPS ---- a/arch/parisc/include/asm/cache.h -+++ b/arch/parisc/include/asm/cache.h -@@ -20,7 +20,16 @@ - - #define SMP_CACHE_BYTES L1_CACHE_BYTES - --#define ARCH_DMA_MINALIGN L1_CACHE_BYTES -+#ifdef CONFIG_PA20 -+#define ARCH_DMA_MINALIGN 128 -+#else -+#define ARCH_DMA_MINALIGN 32 -+#endif -+#define ARCH_KMALLOC_MINALIGN 16 /* ldcw requires 16-byte alignment */ -+ -+#define arch_slab_minalign() ((unsigned)dcache_stride) -+#define cache_line_size() dcache_stride -+#define dma_get_cache_alignment cache_line_size - - #define __read_mostly __section(".data..read_mostly") - diff --git a/queue-6.1/series b/queue-6.1/series index 5478f9f7ab4..55e2dacd9d1 100644 --- a/queue-6.1/series +++ b/queue-6.1/series @@ -107,7 +107,6 @@ driver-core-fix-uevent_show-vs-driver-detach-race.patch ntp-safeguard-against-time_constant-overflow.patch timekeeping-fix-bogus-clock_was_set-invocation-in-do_adjtimex.patch serial-core-check-uartclk-for-zero-to-avoid-divide-by-zero.patch -parisc-fix-a-possible-dma-corruption.patch asoc-amd-yc-add-quirk-entry-for-omen-by-hp-gaming-laptop-16-n0xxx.patch kcov-properly-check-for-softirq-context.patch irqchip-xilinx-fix-shift-out-of-bounds.patch