From: Mukesh Ojha Date: Fri, 27 Mar 2026 17:12:39 +0000 (+0530) Subject: pinctrl: qcom: eliza: Fix interrupt target bit X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=fe8933c5b3e2e5294f82da546792268e5687391e;p=thirdparty%2Fkernel%2Fstable.git pinctrl: qcom: eliza: Fix interrupt target bit The intr_target_bit for Eliza was incorrectly set to 5, which is the value used by older Qualcomm SoCs (e.g. SM8250, MSM8996, X1E80100). Newer SoCs such as SM8650, SM8750, Milos, and Kaanapali all use bit 8 for the interrupt target field in the TLMM interrupt configuration register. Eliza belongs to the newer generation and should use bit 8 to correctly route interrupts to the KPSS (Applications Processor). Using the wrong bit position means the interrupt target routing is silently misconfigured, which can result in GPIO interrupts not being delivered to the expected processor. Fix this by aligning Eliza with the correct value used by its peer SoCs. Fixes: 6f26989e15fb ("pinctrl: qcom: Add Eliza pinctrl driver") Signed-off-by: Mukesh Ojha Reviewed-by: Abel Vesa Signed-off-by: Linus Walleij --- diff --git a/drivers/pinctrl/qcom/pinctrl-eliza.c b/drivers/pinctrl/qcom/pinctrl-eliza.c index 1a2e6461a69b..19c706137f81 100644 --- a/drivers/pinctrl/qcom/pinctrl-eliza.c +++ b/drivers/pinctrl/qcom/pinctrl-eliza.c @@ -47,7 +47,7 @@ .intr_status_bit = 0, \ .intr_wakeup_present_bit = 6, \ .intr_wakeup_enable_bit = 7, \ - .intr_target_bit = 5, \ + .intr_target_bit = 8, \ .intr_target_kpss_val = 3, \ .intr_raw_status_bit = 4, \ .intr_polarity_bit = 1, \