From: Julian Seward <jseward@acm.org>
Date: Thu, 6 Nov 2008 09:22:05 +0000 (+0000)
Subject: Tighten up decoding of isel instruction.
X-Git-Tag: svn/VALGRIND_3_4_1^2~9
X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=fea1aa9762fe9014e64f3c00e8b79536e561dbc4;p=thirdparty%2Fvalgrind.git

Tighten up decoding of isel instruction.


git-svn-id: svn://svn.valgrind.org/vex/trunk@1871
---

diff --git a/VEX/priv/guest-ppc/toIR.c b/VEX/priv/guest-ppc/toIR.c
index 3b4e5415a6..dcd04afb23 100644
--- a/VEX/priv/guest-ppc/toIR.c
+++ b/VEX/priv/guest-ppc/toIR.c
@@ -9479,7 +9479,9 @@ DisResult disInstr_PPC_WRK (
          /* Deal with some other cases that we would otherwise have
             punted on. */
          /* --- ISEL (PowerISA_V2.05.pdf, p74) --- */
-         if (IFIELD(theInstr, 1, 5) == 15) {
+         /* only decode this insn when reserved bit 0 (31 in IBM's
+            notation) is zero */
+         if (IFIELD(theInstr, 0, 6) == (15<<1)) {
             UInt rT = ifieldRegDS( theInstr );
             UInt rA = ifieldRegA( theInstr );
             UInt rB = ifieldRegB( theInstr );