From: Michael J. Ruhl Date: Wed, 9 Feb 2022 16:28:01 +0000 (-0500) Subject: PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist X-Git-Tag: v5.18-rc1~114^2~13^2 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=feaea1fe8b36b2e5b12b2f9e6e050db28dfee789;p=thirdparty%2Flinux.git PCI/P2PDMA: Add Intel 3rd Gen Intel Xeon Scalable Processors to whitelist In order to do P2P communication the bridge ID of the platform must be in the P2P device table. Update the P2P device table with a device ID for the 3rd Gen Intel Xeon Scalable Processors. Link: https://lore.kernel.org/r/20220209162801.7647-1-michael.j.ruhl@intel.com Signed-off-by: Michael J. Ruhl Signed-off-by: Bjorn Helgaas Reviewed-by: Dan Williams --- diff --git a/drivers/pci/p2pdma.c b/drivers/pci/p2pdma.c index 1015274bd2fed..30b1df3c9d2f4 100644 --- a/drivers/pci/p2pdma.c +++ b/drivers/pci/p2pdma.c @@ -321,6 +321,7 @@ static const struct pci_p2pdma_whitelist_entry { {PCI_VENDOR_ID_INTEL, 0x2032, 0}, {PCI_VENDOR_ID_INTEL, 0x2033, 0}, {PCI_VENDOR_ID_INTEL, 0x2020, 0}, + {PCI_VENDOR_ID_INTEL, 0x09a2, 0}, {} };