From: Greg Kroah-Hartman Date: Sun, 1 Jul 2018 10:01:10 +0000 (+0200) Subject: 3.18-stable patches X-Git-Tag: v3.18.114~32 X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=ff56c1899f5d38d8c51a8a0cb81a03ecabd91593;p=thirdparty%2Fkernel%2Fstable-queue.git 3.18-stable patches added patches: mips-bcm47xx-enable-74k-core-externalsync-for-pcie-erratum.patch mtd-cfi_cmdset_0002-avoid-walking-all-chips-when-unlocking.patch mtd-cfi_cmdset_0002-change-erase-functions-to-retry-for-error.patch mtd-cfi_cmdset_0002-change-write-buffer-to-check-correct-value.patch mtd-cfi_cmdset_0002-fix-segv-unlocking-multiple-chips.patch mtd-cfi_cmdset_0002-fix-unlocking-requests-crossing-a-chip-boudary.patch mtd-cfi_cmdset_0002-use-right-chip-in-do_ppb_xxlock.patch pci-pciehp-clear-presence-detect-and-data-link-layer-status-changed-on-resume.patch --- diff --git a/queue-3.18/mips-bcm47xx-enable-74k-core-externalsync-for-pcie-erratum.patch b/queue-3.18/mips-bcm47xx-enable-74k-core-externalsync-for-pcie-erratum.patch new file mode 100644 index 00000000000..d535119929c --- /dev/null +++ b/queue-3.18/mips-bcm47xx-enable-74k-core-externalsync-for-pcie-erratum.patch @@ -0,0 +1,84 @@ +From 2a027b47dba6b77ab8c8e47b589ae9bbc5ac6175 Mon Sep 17 00:00:00 2001 +From: Tokunori Ikegami +Date: Sun, 3 Jun 2018 23:02:01 +0900 +Subject: MIPS: BCM47XX: Enable 74K Core ExternalSync for PCIe erratum +MIME-Version: 1.0 +Content-Type: text/plain; charset=UTF-8 +Content-Transfer-Encoding: 8bit + +From: Tokunori Ikegami + +commit 2a027b47dba6b77ab8c8e47b589ae9bbc5ac6175 upstream. + +The erratum and workaround are described by BCM5300X-ES300-RDS.pdf as +below. + + R10: PCIe Transactions Periodically Fail + + Description: The BCM5300X PCIe does not maintain transaction ordering. + This may cause PCIe transaction failure. + Fix Comment: Add a dummy PCIe configuration read after a PCIe + configuration write to ensure PCIe configuration access + ordering. Set ES bit of CP0 configu7 register to enable + sync function so that the sync instruction is functional. + Resolution: hndpci.c: extpci_write_config() + hndmips.c: si_mips_init() + mipsinc.h CONF7_ES + +This is fixed by the CFE MIPS bcmsi chipset driver also for BCM47XX. +Also the dummy PCIe configuration read is already implemented in the +Linux BCMA driver. + +Enable ExternalSync in Config7 when CONFIG_BCMA_DRIVER_PCI_HOSTMODE=y +too so that the sync instruction is externalised. + +Signed-off-by: Tokunori Ikegami +Reviewed-by: Paul Burton +Acked-by: Hauke Mehrtens +Cc: Chris Packham +Cc: Rafał Miłecki +Cc: linux-mips@linux-mips.org +Cc: stable@vger.kernel.org +Patchwork: https://patchwork.linux-mips.org/patch/19461/ +Signed-off-by: James Hogan +Signed-off-by: Greg Kroah-Hartman + +--- + arch/mips/bcm47xx/setup.c | 6 ++++++ + arch/mips/include/asm/mipsregs.h | 3 +++ + 2 files changed, 9 insertions(+) + +--- a/arch/mips/bcm47xx/setup.c ++++ b/arch/mips/bcm47xx/setup.c +@@ -269,6 +269,12 @@ static int __init bcm47xx_cpu_fixes(void + */ + if (bcm47xx_bus.bcma.bus.chipinfo.id == BCMA_CHIP_ID_BCM4706) + cpu_wait = NULL; ++ ++ /* ++ * BCM47XX Erratum "R10: PCIe Transactions Periodically Fail" ++ * Enable ExternalSync for sync instruction to take effect ++ */ ++ set_c0_config7(MIPS_CONF7_ES); + break; + #endif + } +--- a/arch/mips/include/asm/mipsregs.h ++++ b/arch/mips/include/asm/mipsregs.h +@@ -667,6 +667,8 @@ + #define MIPS_CONF7_WII (_ULCAST_(1) << 31) + + #define MIPS_CONF7_RPS (_ULCAST_(1) << 2) ++/* ExternalSync */ ++#define MIPS_CONF7_ES (_ULCAST_(1) << 8) + + #define MIPS_CONF7_IAR (_ULCAST_(1) << 10) + #define MIPS_CONF7_AR (_ULCAST_(1) << 16) +@@ -1863,6 +1865,7 @@ __BUILD_SET_C0(status) + __BUILD_SET_C0(cause) + __BUILD_SET_C0(config) + __BUILD_SET_C0(config5) ++__BUILD_SET_C0(config7) + __BUILD_SET_C0(intcontrol) + __BUILD_SET_C0(intctl) + __BUILD_SET_C0(srsmap) diff --git a/queue-3.18/mtd-cfi_cmdset_0002-avoid-walking-all-chips-when-unlocking.patch b/queue-3.18/mtd-cfi_cmdset_0002-avoid-walking-all-chips-when-unlocking.patch new file mode 100644 index 00000000000..9bb816917a1 --- /dev/null +++ b/queue-3.18/mtd-cfi_cmdset_0002-avoid-walking-all-chips-when-unlocking.patch @@ -0,0 +1,33 @@ +From f1ce87f6080b1dda7e7b1eda3da332add19d87b9 Mon Sep 17 00:00:00 2001 +From: Joakim Tjernlund +Date: Wed, 6 Jun 2018 12:13:30 +0200 +Subject: mtd: cfi_cmdset_0002: Avoid walking all chips when unlocking. + +From: Joakim Tjernlund + +commit f1ce87f6080b1dda7e7b1eda3da332add19d87b9 upstream. + +cfi_ppb_unlock() walks all flash chips when unlocking sectors, +avoid walking chips unaffected by the unlock operation. + +Fixes: 1648eaaa1575 ("mtd: cfi_cmdset_0002: Support Persistent Protection Bits (PPB) locking") +Cc: stable@vger.kernel.org +Signed-off-by: Joakim Tjernlund +Signed-off-by: Boris Brezillon +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 2 ++ + 1 file changed, 2 insertions(+) + +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -2693,6 +2693,8 @@ static int __maybe_unused cfi_ppb_unlock + i++; + + if (adr >> cfi->chipshift) { ++ if (offset >= (ofs + len)) ++ break; + adr = 0; + chipnum++; + diff --git a/queue-3.18/mtd-cfi_cmdset_0002-change-erase-functions-to-retry-for-error.patch b/queue-3.18/mtd-cfi_cmdset_0002-change-erase-functions-to-retry-for-error.patch new file mode 100644 index 00000000000..7dac97746fb --- /dev/null +++ b/queue-3.18/mtd-cfi_cmdset_0002-change-erase-functions-to-retry-for-error.patch @@ -0,0 +1,91 @@ +From 45f75b8a919a4255f52df454f1ffdee0e42443b2 Mon Sep 17 00:00:00 2001 +From: Tokunori Ikegami +Date: Wed, 30 May 2018 18:32:28 +0900 +Subject: mtd: cfi_cmdset_0002: Change erase functions to retry for error + +From: Tokunori Ikegami + +commit 45f75b8a919a4255f52df454f1ffdee0e42443b2 upstream. + +For the word write functions it is retried for error. +But it is not implemented to retry for the erase functions. +To make sure for the erase functions change to retry as same. + +This is needed to prevent the flash erase error caused only once. +It was caused by the error case of chip_good() in the do_erase_oneblock(). +Also it was confirmed on the MACRONIX flash device MX29GL512FHT2I-11G. +But the error issue behavior is not able to reproduce at this moment. +The flash controller is parallel Flash interface integrated on BCM53003. + +Signed-off-by: Tokunori Ikegami +Reviewed-by: Joakim Tjernlund +Cc: Chris Packham +Cc: Brian Norris +Cc: David Woodhouse +Cc: Boris Brezillon +Cc: Marek Vasut +Cc: Richard Weinberger +Cc: Cyrille Pitchen +Cc: linux-mtd@lists.infradead.org +Cc: stable@vger.kernel.org +Signed-off-by: Boris Brezillon +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 10 ++++++++++ + 1 file changed, 10 insertions(+) + +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -2239,6 +2239,7 @@ static int __xipram do_erase_chip(struct + unsigned long int adr; + DECLARE_WAITQUEUE(wait, current); + int ret = 0; ++ int retry_cnt = 0; + + adr = cfi->addr_unlock1; + +@@ -2256,6 +2257,7 @@ static int __xipram do_erase_chip(struct + ENABLE_VPP(map); + xip_disable(map, chip, adr); + ++ retry: + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); + cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); +@@ -2310,6 +2312,9 @@ static int __xipram do_erase_chip(struct + map_write( map, CMD(0xF0), chip->start ); + /* FIXME - should have reset delay before continuing */ + ++ if (++retry_cnt <= MAX_RETRIES) ++ goto retry; ++ + ret = -EIO; + } + +@@ -2329,6 +2334,7 @@ static int __xipram do_erase_oneblock(st + unsigned long timeo = jiffies + HZ; + DECLARE_WAITQUEUE(wait, current); + int ret = 0; ++ int retry_cnt = 0; + + adr += chip->start; + +@@ -2346,6 +2352,7 @@ static int __xipram do_erase_oneblock(st + ENABLE_VPP(map); + xip_disable(map, chip, adr); + ++ retry: + cfi_send_gen_cmd(0xAA, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); + cfi_send_gen_cmd(0x55, cfi->addr_unlock2, chip->start, map, cfi, cfi->device_type, NULL); + cfi_send_gen_cmd(0x80, cfi->addr_unlock1, chip->start, map, cfi, cfi->device_type, NULL); +@@ -2403,6 +2410,9 @@ static int __xipram do_erase_oneblock(st + map_write( map, CMD(0xF0), chip->start ); + /* FIXME - should have reset delay before continuing */ + ++ if (++retry_cnt <= MAX_RETRIES) ++ goto retry; ++ + ret = -EIO; + } + diff --git a/queue-3.18/mtd-cfi_cmdset_0002-change-write-buffer-to-check-correct-value.patch b/queue-3.18/mtd-cfi_cmdset_0002-change-write-buffer-to-check-correct-value.patch new file mode 100644 index 00000000000..94ee0799a72 --- /dev/null +++ b/queue-3.18/mtd-cfi_cmdset_0002-change-write-buffer-to-check-correct-value.patch @@ -0,0 +1,45 @@ +From dfeae1073583dc35c33b32150e18b7048bbb37e6 Mon Sep 17 00:00:00 2001 +From: Tokunori Ikegami +Date: Wed, 30 May 2018 18:32:26 +0900 +Subject: mtd: cfi_cmdset_0002: Change write buffer to check correct value + +From: Tokunori Ikegami + +commit dfeae1073583dc35c33b32150e18b7048bbb37e6 upstream. + +For the word write it is checked if the chip has the correct value. +But it is not checked for the write buffer as only checked if ready. +To make sure for the write buffer change to check the value. + +It is enough as this patch is only checking the last written word. +Since it is described by data sheets to check the operation status. + +Signed-off-by: Tokunori Ikegami +Reviewed-by: Joakim Tjernlund +Cc: Chris Packham +Cc: Brian Norris +Cc: David Woodhouse +Cc: Boris Brezillon +Cc: Marek Vasut +Cc: Richard Weinberger +Cc: Cyrille Pitchen +Cc: linux-mtd@lists.infradead.org +Cc: stable@vger.kernel.org +Signed-off-by: Boris Brezillon +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -1878,7 +1878,7 @@ static int __xipram do_write_buffer(stru + if (time_after(jiffies, timeo) && !chip_ready(map, adr)) + break; + +- if (chip_ready(map, adr)) { ++ if (chip_good(map, adr, datum)) { + xip_enable(map, chip, adr); + goto op_done; + } diff --git a/queue-3.18/mtd-cfi_cmdset_0002-fix-segv-unlocking-multiple-chips.patch b/queue-3.18/mtd-cfi_cmdset_0002-fix-segv-unlocking-multiple-chips.patch new file mode 100644 index 00000000000..06a72f8267c --- /dev/null +++ b/queue-3.18/mtd-cfi_cmdset_0002-fix-segv-unlocking-multiple-chips.patch @@ -0,0 +1,54 @@ +From 5fdfc3dbad099281bf027a353d5786c09408a8e5 Mon Sep 17 00:00:00 2001 +From: Joakim Tjernlund +Date: Wed, 6 Jun 2018 12:13:28 +0200 +Subject: mtd: cfi_cmdset_0002: fix SEGV unlocking multiple chips + +From: Joakim Tjernlund + +commit 5fdfc3dbad099281bf027a353d5786c09408a8e5 upstream. + +cfi_ppb_unlock() tries to relock all sectors that were locked before +unlocking the whole chip. +This locking used the chip start address + the FULL offset from the +first flash chip, thereby forming an illegal address. Fix that by using +the chip offset(adr). + +Fixes: 1648eaaa1575 ("mtd: cfi_cmdset_0002: Support Persistent Protection Bits (PPB) locking") +Cc: stable@vger.kernel.org +Signed-off-by: Joakim Tjernlund +Signed-off-by: Boris Brezillon +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 6 +++--- + 1 file changed, 3 insertions(+), 3 deletions(-) + +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -2543,7 +2543,7 @@ static int cfi_atmel_unlock(struct mtd_i + + struct ppb_lock { + struct flchip *chip; +- loff_t offset; ++ unsigned long adr; + int locked; + }; + +@@ -2679,7 +2679,7 @@ static int __maybe_unused cfi_ppb_unlock + */ + if ((adr < ofs) || (adr >= (ofs + len))) { + sect[sectors].chip = &cfi->chips[chipnum]; +- sect[sectors].offset = offset; ++ sect[sectors].adr = adr; + sect[sectors].locked = do_ppb_xxlock( + map, &cfi->chips[chipnum], adr, 0, + DO_XXLOCK_ONEBLOCK_GETLOCK); +@@ -2723,7 +2723,7 @@ static int __maybe_unused cfi_ppb_unlock + */ + for (i = 0; i < sectors; i++) { + if (sect[i].locked) +- do_ppb_xxlock(map, sect[i].chip, sect[i].offset, 0, ++ do_ppb_xxlock(map, sect[i].chip, sect[i].adr, 0, + DO_XXLOCK_ONEBLOCK_LOCK); + } + diff --git a/queue-3.18/mtd-cfi_cmdset_0002-fix-unlocking-requests-crossing-a-chip-boudary.patch b/queue-3.18/mtd-cfi_cmdset_0002-fix-unlocking-requests-crossing-a-chip-boudary.patch new file mode 100644 index 00000000000..cffa2615138 --- /dev/null +++ b/queue-3.18/mtd-cfi_cmdset_0002-fix-unlocking-requests-crossing-a-chip-boudary.patch @@ -0,0 +1,36 @@ +From 0cd8116f172eed018907303dbff5c112690eeb91 Mon Sep 17 00:00:00 2001 +From: Joakim Tjernlund +Date: Wed, 6 Jun 2018 12:13:29 +0200 +Subject: mtd: cfi_cmdset_0002: Fix unlocking requests crossing a chip boudary + +From: Joakim Tjernlund + +commit 0cd8116f172eed018907303dbff5c112690eeb91 upstream. + +The "sector is in requested range" test used to determine whether +sectors should be re-locked or not is done on a variable that is reset +everytime we cross a chip boundary, which can lead to some blocks being +re-locked while the caller expect them to be unlocked. +Fix the check to make sure this cannot happen. + +Fixes: 1648eaaa1575 ("mtd: cfi_cmdset_0002: Support Persistent Protection Bits (PPB) locking") +Cc: stable@vger.kernel.org +Signed-off-by: Joakim Tjernlund +Signed-off-by: Boris Brezillon +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 2 +- + 1 file changed, 1 insertion(+), 1 deletion(-) + +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -2677,7 +2677,7 @@ static int __maybe_unused cfi_ppb_unlock + * sectors shall be unlocked, so lets keep their locking + * status at "unlocked" (locked=0) for the final re-locking. + */ +- if ((adr < ofs) || (adr >= (ofs + len))) { ++ if ((offset < ofs) || (offset >= (ofs + len))) { + sect[sectors].chip = &cfi->chips[chipnum]; + sect[sectors].adr = adr; + sect[sectors].locked = do_ppb_xxlock( diff --git a/queue-3.18/mtd-cfi_cmdset_0002-use-right-chip-in-do_ppb_xxlock.patch b/queue-3.18/mtd-cfi_cmdset_0002-use-right-chip-in-do_ppb_xxlock.patch new file mode 100644 index 00000000000..1777e61fba5 --- /dev/null +++ b/queue-3.18/mtd-cfi_cmdset_0002-use-right-chip-in-do_ppb_xxlock.patch @@ -0,0 +1,57 @@ +From f93aa8c4de307069c270b2d81741961162bead6c Mon Sep 17 00:00:00 2001 +From: Joakim Tjernlund +Date: Wed, 6 Jun 2018 12:13:27 +0200 +Subject: mtd: cfi_cmdset_0002: Use right chip in do_ppb_xxlock() + +From: Joakim Tjernlund + +commit f93aa8c4de307069c270b2d81741961162bead6c upstream. + +do_ppb_xxlock() fails to add chip->start when querying for lock status +(and chip_ready test), which caused false status reports. +Fix that by adding adr += chip->start and adjust call sites +accordingly. + +Fixes: 1648eaaa1575 ("mtd: cfi_cmdset_0002: Support Persistent Protection Bits (PPB) locking") +Cc: stable@vger.kernel.org +Signed-off-by: Joakim Tjernlund +Signed-off-by: Boris Brezillon +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/mtd/chips/cfi_cmdset_0002.c | 9 +++++---- + 1 file changed, 5 insertions(+), 4 deletions(-) + +--- a/drivers/mtd/chips/cfi_cmdset_0002.c ++++ b/drivers/mtd/chips/cfi_cmdset_0002.c +@@ -2561,8 +2561,9 @@ static int __maybe_unused do_ppb_xxlock( + unsigned long timeo; + int ret; + ++ adr += chip->start; + mutex_lock(&chip->mutex); +- ret = get_chip(map, chip, adr + chip->start, FL_LOCKING); ++ ret = get_chip(map, chip, adr, FL_LOCKING); + if (ret) { + mutex_unlock(&chip->mutex); + return ret; +@@ -2580,8 +2581,8 @@ static int __maybe_unused do_ppb_xxlock( + + if (thunk == DO_XXLOCK_ONEBLOCK_LOCK) { + chip->state = FL_LOCKING; +- map_write(map, CMD(0xA0), chip->start + adr); +- map_write(map, CMD(0x00), chip->start + adr); ++ map_write(map, CMD(0xA0), adr); ++ map_write(map, CMD(0x00), adr); + } else if (thunk == DO_XXLOCK_ONEBLOCK_UNLOCK) { + /* + * Unlocking of one specific sector is not supported, so we +@@ -2619,7 +2620,7 @@ static int __maybe_unused do_ppb_xxlock( + map_write(map, CMD(0x00), chip->start); + + chip->state = FL_READY; +- put_chip(map, chip, adr + chip->start); ++ put_chip(map, chip, adr); + mutex_unlock(&chip->mutex); + + return ret; diff --git a/queue-3.18/pci-pciehp-clear-presence-detect-and-data-link-layer-status-changed-on-resume.patch b/queue-3.18/pci-pciehp-clear-presence-detect-and-data-link-layer-status-changed-on-resume.patch new file mode 100644 index 00000000000..f513cb80674 --- /dev/null +++ b/queue-3.18/pci-pciehp-clear-presence-detect-and-data-link-layer-status-changed-on-resume.patch @@ -0,0 +1,83 @@ +From 13c65840feab8109194f9490c9870587173cb29d Mon Sep 17 00:00:00 2001 +From: Mika Westerberg +Date: Wed, 23 May 2018 17:14:39 -0500 +Subject: PCI: pciehp: Clear Presence Detect and Data Link Layer Status Changed on resume + +From: Mika Westerberg + +commit 13c65840feab8109194f9490c9870587173cb29d upstream. + +After a suspend/resume cycle the Presence Detect or Data Link Layer Status +Changed bits might be set. If we don't clear them those events will not +fire anymore and nothing happens for instance when a device is now +hot-unplugged. + +Fix this by clearing those bits in a newly introduced function +pcie_reenable_notification(). This should be fine because immediately +after, we check if the adapter is still present by reading directly from +the status register. + +Signed-off-by: Mika Westerberg +Signed-off-by: Bjorn Helgaas +Reviewed-by: Rafael J. Wysocki +Reviewed-by: Andy Shevchenko +Cc: stable@vger.kernel.org +Signed-off-by: Greg Kroah-Hartman + +--- + drivers/pci/hotplug/pciehp.h | 2 +- + drivers/pci/hotplug/pciehp_core.c | 2 +- + drivers/pci/hotplug/pciehp_hpc.c | 13 ++++++++++++- + 3 files changed, 14 insertions(+), 3 deletions(-) + +--- a/drivers/pci/hotplug/pciehp.h ++++ b/drivers/pci/hotplug/pciehp.h +@@ -144,7 +144,7 @@ struct controller *pcie_init(struct pcie + int pcie_init_notification(struct controller *ctrl); + int pciehp_enable_slot(struct slot *p_slot); + int pciehp_disable_slot(struct slot *p_slot); +-void pcie_enable_notification(struct controller *ctrl); ++void pcie_reenable_notification(struct controller *ctrl); + int pciehp_power_on_slot(struct slot *slot); + void pciehp_power_off_slot(struct slot *slot); + void pciehp_get_power_status(struct slot *slot, u8 *status); +--- a/drivers/pci/hotplug/pciehp_core.c ++++ b/drivers/pci/hotplug/pciehp_core.c +@@ -332,7 +332,7 @@ static int pciehp_resume(struct pcie_dev + ctrl = get_service_data(dev); + + /* reinitialize the chipset's event detection logic */ +- pcie_enable_notification(ctrl); ++ pcie_reenable_notification(ctrl); + + slot = ctrl->slot; + +--- a/drivers/pci/hotplug/pciehp_hpc.c ++++ b/drivers/pci/hotplug/pciehp_hpc.c +@@ -602,7 +602,7 @@ static irqreturn_t pcie_isr(int irq, voi + return IRQ_HANDLED; + } + +-void pcie_enable_notification(struct controller *ctrl) ++static void pcie_enable_notification(struct controller *ctrl) + { + u16 cmd, mask; + +@@ -642,6 +642,17 @@ void pcie_enable_notification(struct con + pci_pcie_cap(ctrl->pcie->port) + PCI_EXP_SLTCTL, cmd); + } + ++void pcie_reenable_notification(struct controller *ctrl) ++{ ++ /* ++ * Clear both Presence and Data Link Layer Changed to make sure ++ * those events still fire after we have re-enabled them. ++ */ ++ pcie_capability_write_word(ctrl->pcie->port, PCI_EXP_SLTSTA, ++ PCI_EXP_SLTSTA_PDC | PCI_EXP_SLTSTA_DLLSC); ++ pcie_enable_notification(ctrl); ++} ++ + static void pcie_disable_notification(struct controller *ctrl) + { + u16 mask; diff --git a/queue-3.18/series b/queue-3.18/series index c587907ad79..53db04a5182 100644 --- a/queue-3.18/series +++ b/queue-3.18/series @@ -60,3 +60,11 @@ powerpc-ptrace-fix-setting-512b-aligned-breakpoints-with-ptrace_set_debugreg.pat powerpc-ptrace-fix-enforcement-of-dawr-constraints.patch powerpc-fadump-unregister-fadump-on-kexec-down-path.patch arm-8764-1-kgdb-fix-numregbytes-so-that-gdb_regs-is-the-correct-size.patch +mtd-cfi_cmdset_0002-change-write-buffer-to-check-correct-value.patch +mtd-cfi_cmdset_0002-change-erase-functions-to-retry-for-error.patch +mtd-cfi_cmdset_0002-use-right-chip-in-do_ppb_xxlock.patch +mtd-cfi_cmdset_0002-fix-segv-unlocking-multiple-chips.patch +mtd-cfi_cmdset_0002-fix-unlocking-requests-crossing-a-chip-boudary.patch +mtd-cfi_cmdset_0002-avoid-walking-all-chips-when-unlocking.patch +mips-bcm47xx-enable-74k-core-externalsync-for-pcie-erratum.patch +pci-pciehp-clear-presence-detect-and-data-link-layer-status-changed-on-resume.patch