From: Jonas Jelonek Date: Tue, 14 Apr 2026 11:17:43 +0000 (+0000) Subject: realtek: pcs: rtl93xx: extend USXGMII config X-Git-Url: http://git.ipfire.org/gitweb.cgi?a=commitdiff_plain;h=refs%2Fpull%2F22939%2Fhead;p=thirdparty%2Fopenwrt.git realtek: pcs: rtl93xx: extend USXGMII config Our USXGMII config only covers one single register of which kind there are actually more. We only set a value for 'CFG_QHSG_TXCFG_MAC_CH0' but there are additional registers for CH1-CH3. Those refer to the 4 USXGMII 'channels'. While the RTL930x part of the SDK doesn't set them explicitly, from RTK setup SerDes dumps we can see they are usually similarly set. The RTL931x part of the SDK actually writes those register explicitly during USXGMII. We just haven't implemented that so far. Thus, add this to the USXGMII config for both RTL93xx. Signed-off-by: Jonas Jelonek Link: https://github.com/openwrt/openwrt/pull/22939 Signed-off-by: Robert Marko --- diff --git a/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c b/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c index cf49342f0a6..3bfe8a47d7c 100644 --- a/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c +++ b/target/linux/realtek/files-6.18/drivers/net/pcs/pcs-rtl-otto.c @@ -1149,7 +1149,11 @@ static void rtpcs_93xx_sds_usxgmii_config(struct rtpcs_serdes *sds, u32 opcode, rtpcs_sds_write(sds, 0x06, 0x00, 0x0000); rtpcs_sds_write(sds, 0x06, 0x0D, 0x0F00); rtpcs_sds_write(sds, 0x06, 0x1D, 0x0600); + rtpcs_sds_write(sds, 0x07, 0x06, 0x1401); /* CFG_QHSG_TXCFG_MAC_CH0 */ + rtpcs_sds_write(sds, 0x07, 0x08, 0x1401); /* CFG_QHSG_TXCFG_MAC_CH1 */ + rtpcs_sds_write(sds, 0x07, 0x0a, 0x1401); /* CFG_QHSG_TXCFG_MAC_CH2 */ + rtpcs_sds_write(sds, 0x07, 0x0c, 0x1401); /* CFG_QHSG_TXCFG_MAC_CH3 */ /* * Controls the USXGMII AN mode. Two states are currently known: