Michal Simek [Mon, 9 Jan 2017 09:05:16 +0000 (10:05 +0100)]
ARM64: zynqmp: Generate handoff structure for ATF
Xilinx ATF extending options for passing images from BL2(FSBL)
to BL31. U-Boot SPL is FSBL replacement that's why it should generate
handoff structure the same. Support only one entry which is U-Boot in
EL2 itself. When FIT image is adopted structure generate should be data
driven.
Currently ATF is placing this structure at the beggining of OCM which is
rewriting early parts of ATF which should be unused at that time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Kamensky Ivan [Tue, 27 Dec 2016 16:12:23 +0000 (19:12 +0300)]
xilinx_phy: Pass correct pointer to fdtdec_get_int()
This patch fixes incorrect pointer on offset device in device tree blob.
When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII"
it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying
to change frequency.
Signed-off-by: Kamensky Ivan <kamensky.ivan@mail.ru> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: xilinx_axi_emac: Add support for non processor mode
Add support for non processor mode, this mode doesnt have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.
Michal Simek [Tue, 20 Dec 2016 15:26:25 +0000 (16:26 +0100)]
usb: storage: Show number of storage devices detected for DM_USB
By enabling DM_USB information about number of storage devices
was lost.
Get this information back simply by printing number of devices detected
via BLK uclass.
For example:
scanning bus 0 for devices... 7 USB Device(s) found
scanning usb for storage devices... 3 Storage Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 31 Mar 2016 11:53:58 +0000 (13:53 +0200)]
drivers: usb: Add DWC3 Xilinx ZynqMP glue logic
By enabling BLK by default this is the next driver which needs to get
support for DM_USB. Adding generic DWC3 glue logic which only
parse nodes and read device mode. Based on it probe proper
host/peripheral DWC3 drivers for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 21 Dec 2016 12:18:40 +0000 (13:18 +0100)]
drivers: usb: dwc3: add ti dwc3 peripheral driver with driver model support
Add a TI DWC3 peripheral driver with driver model support and the
driver will be bound by the DWC3 wrapper driver based on the
dr_mode device tree entry.
Mugunthan V N [Fri, 18 Nov 2016 05:36:13 +0000 (11:06 +0530)]
drivers: usb: gadget: ether: consolidate global devices to single struct
Consolidate the net device, usb eth device and gadget device
struct to single struct and a single global variable so that the
same can be passed as priv of ethernet driver.
Signed-off-by: Mugunthan V N <mugunthanvnm@ti.com> Reviewed-by: Simon Glass <sjg@chromium.org> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
Michal Simek [Tue, 20 Dec 2016 08:54:18 +0000 (09:54 +0100)]
tools: mkimage: Call fclose in error path
This patch is fixing missing fclose() calls
in error patch introduced by:
"tools: mkimage: Use fstat instead of stat to avoid malicious hacks"
(sha1: ebe0f53f48e8f9ecc823e533a85b05c13638c350)
Reported-by: Coverity (CID: 155064, 155065) Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 16 Dec 2016 12:46:20 +0000 (13:46 +0100)]
ARM: zynq: Remove ZYNQ_M29EW_WB_HACK macro
This functionality should be covered by:
"mtd: cfi_flash: Write buffer size adjustment for M29EW Numonyx devices"
(sha1: 6f13889eb03fd3ce7b643aa6134856b3a2bf8d88)
That's why remove this macro and hack.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 16 Dec 2016 11:40:16 +0000 (12:40 +0100)]
ARM: zynq: Remove unused cc108 config file
cc108 is handled via zynq-common.h config. The only missing
piece is different ENV_OFFSET setting for qspi boot mode
but this depends on user configuration. This board is tested via jtag
boot mode only that's why if qspi mode is required we can fix it later.
Comment was added to zynq-common.h not to be lost.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 16 Dec 2016 10:08:33 +0000 (11:08 +0100)]
Merge tag 'v2016.11' into master
Prepare v2016.11
- Add missing CONFIG_ macros to Kconfig. It should be fixed in future
- Fix spl_mmc fpga code
- Add missing defconfig macros
- Remove FPGA macros because it was moved to Kconfig in mainline
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jagan Teki [Thu, 5 Jan 2017 14:32:50 +0000 (15:32 +0100)]
mx6ullevk: Add missing MAINTAINERS for mx6ull_14x14_evk_plugin_defconfig
Add 'Peng Fan' as MAINTAINERS of configs/mx6ull_14x14_evk_plugin_defconfig
which is missing in below commit
"imx: mx6ull_14x14_evk: add plugin defconfig"
(sha1: b90ebf49bb8f74afe68f696f59a0e24cc79f2031)
Cc: Stefano Babic <sbabic@denx.de> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Jagan Teki <jagan@openedev.com>
Andrew F. Davis [Fri, 6 Jan 2017 22:32:12 +0000 (16:32 -0600)]
am335x: configs: Use ISW_ENTRY_ADDR to set SPL_TEXT_BASE
The SPL load address changes based on boot type in HS devices,
ISW_ENTRY_ADDR is used to set this address for AM43xx based SoCs
for similar reasons. Add this same logic for AM33xx devices.
Also make the default value for ISW_ENTRY_ADDR correct for GP
devices based on SoC, HS devices already pick the correct
value in their defconfig.
Andrew F. Davis [Fri, 6 Jan 2017 22:20:02 +0000 (16:20 -0600)]
arm: mach-omap2: Fix secure file generation
When TI_SECURE_DEV_PKG is not defined we warn that the file '*_HS' was
not generated but generate an unsigned one anyway, first fix this
warning to say that it was generated but not secured.
When the user then exports TI_SECURE_DEV_PKG after getting this warning,
and tries to re-build, 'make' will detect the build artifacts as
unchanged and so assume they do not need to be re-generated. This causes
it to fail to sign the files and it will pack unsigned files into the
final image, even though TI_SECURE_DEV_PKG is now correctly defined and
working.
Fix this by using FORCE on the targets causes them to be re-run even if
the dependent files have not changed.
This then causes another issue. We currently rename the signed dtb files
to overwrite the non-signed ones. We do this so the 'mkimage' tool gives
the packaged dtb sections the correct name. If we do not rename the files
then SPL will not find them during boot.
Fix this by renaming the dtb files by appending _HS to the end of the
filename, after the ".dtb", this causes them to still be named correctly
in the FIT blob.
York Sun [Wed, 28 Dec 2016 16:43:45 +0000 (08:43 -0800)]
ddr: fsl: Merge macro CONFIG_NUM_DDR_CONTROLLERS and CONFIG_SYS_NUM_DDR_CTRLS
These two macros are used for the same thing, the total number of DDR
controllers for a given SoC. Use SYS_NUM_DDR_CTRLS in Kconfig and
merge existing usage.
York Sun [Wed, 28 Dec 2016 16:43:44 +0000 (08:43 -0800)]
ddr: fsl: Move macro CONFIG_NUM_DDR_CONTROLLERS to Kconfig
Use option NUM_DDR_CONTROLLERS in ddr Kconfig and clean up existing
usage in ls102xa and fsl-layerscape. Remove all powerpc macros in
config header and board header files.
York Sun [Wed, 28 Dec 2016 16:43:42 +0000 (08:43 -0800)]
mmc: move CONFIG_SYS_FSL_ERRATUM_ESDHC* to Kconfig
Add option SYS_FSL_ERRATUM_ESDHC111, SYS_FSL_ERRATUM_ESDHC13,
SYS_FSL_ERRATUM_ESDHC135, SYS_FSL_ERRATUM_ESDHC_A001 to mmc Kconfig.
Move existing macros to related Kconfig.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate bk4r1] Signed-off-by: Tom Rini <trini@konsulko.com>
York Sun [Wed, 28 Dec 2016 16:43:40 +0000 (08:43 -0800)]
fsl_ddr: Move DDR config options to driver Kconfig
Create driver/ddr/fsl/Kconfig and move existing options. Clean up
existing macros.
Signed-off-by: York Sun <york.sun@nxp.com>
[trini: Migrate sbc8641d, xpedite537x and MPC8536DS, run a moveconfig.py -s] Signed-off-by: Tom Rini <trini@konsulko.com>
Vignesh R [Wed, 21 Dec 2016 05:12:33 +0000 (10:42 +0530)]
spi: cadence_qspi_apb: Use 32 bit indirect read transaction when possible
According to Section 11.15.4.9.1 Indirect Read Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface reads until the last word of an indirect transfer
So, make sure that QSPI indirect reads are 32 bit sized except for the
final read. If the rxbuf is unaligned then use bounce buffer, so that
readsl() can be used instead of readsb() to avoid non 32-bit accesses.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
Vignesh R [Wed, 21 Dec 2016 05:12:32 +0000 (10:42 +0530)]
spi: cadence_qspi_apb: Use 32 bit indirect write transaction when possible
According to Section 11.15.4.9.2 Indirect Write Controller of K2G SoC
TRM SPRUHY8D[1], the external master is only permitted to issue 32-bit
data interface writes until the last word of an indirect transfer
otherwise indirect writes is known to fails sometimes. So, make sure
that QSPI indirect writes are 32 bit sized except for the last write. If
the txbuf is unaligned then use bounce buffer to avoid data aborts.
So, now that the driver uses bounce_buffer, enable CONFIG_BOUNCE_BUFFER
for all boards that use Cadence QSPI driver.
[1]www.ti.com/lit/ug/spruhy8d/spruhy8d.pdf
Signed-off-by: Vignesh R <vigneshr@ti.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Jagan Teki <jagan@openedev.com>
Stephen Warren [Fri, 2 Dec 2016 19:26:42 +0000 (12:26 -0700)]
ARM: tegra: allow passing cboot DTB to the kernel
Some users may wish to pass the cboot-supplied DTB to the booted kernel
rather than having U-Boot load the DTB itself. To allow this, expose the
address of the cboot-supplied DTB in environment variable $fdt_addr. At
least when using extlinux.conf, if the user doesn't explicitly specify
which DTB to pass to the kernel, U-Boot passes the DTB referred to by
this variable.
Signed-off-by: Stephen Warren <swarren@nvidia.com> Reviewed-by: Simon Glass <sjg@chromium.org> Signed-off-by: Tom Warren <twarren@nvidia.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:29 +0000 (12:00 +0100)]
configs: engicam: Add fitboot env support
Add FIT image booting from MMC device, during MMC bootcmd
u-boot env script look for bootscript, else fit image or else
finally look for legacy image uImage.
Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Enabling FIT along with Signature will make bootm to
not-understanding u-boot legacy image formats like uImage, etc.
So this patch enabling legacy image format for backward compatibility.
Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:23 +0000 (12:00 +0100)]
defconfigs: engicam: Enable MMC commands in nand
For writing Linux or rootfs on to NAND, the best suitable way
is to use MMC commands since MMC driver by default enabled by
mx6_common.h, hence enabled MMC commands in nand defconfigs.
Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Jagan Teki [Wed, 21 Dec 2016 11:00:22 +0000 (12:00 +0100)]
configs: engicam: Rename nand with gpmi-name in mtdparts
gpmi-nand is the proper name used in nand driver from Linux for all
imx related nand boards, so rename mtdparts name as gpmi-nand instead
of nand, this will eventually reflects all nand info to Linux from
u-boot like mtdparts.
Cc: Stefano Babic <sbabic@denx.de> Cc: Matteo Lisi <matteo.lisi@engicam.com> Cc: Michael Trimarchi <michael@amarulasolutions.com> Signed-off-by: Jagan Teki <jagan@amarulasolutions.com>
Emmanuel Vadot [Tue, 27 Dec 2016 21:36:08 +0000 (22:36 +0100)]
tools: binman: Use /usr/bin/env to find python executable
Some OS (all BSD and probably others) do not have python in /usr/bin
but in another directory.
It is a common usage to use /usr/bin/env python as shebang for python
scripts so use this for binman.
Robert P. J. Day [Thu, 29 Dec 2016 10:23:19 +0000 (05:23 -0500)]
doc/README.cfi: Update code snippet, and add example.
First, update the code snippet referenced in the README file. And
since there are only two boards that override flash_cmd_reset(),
might as well show them both.
Signed-off-by: Robert P. J. Day <rpjday@crashcourse.ca>
Fabio Estevam [Tue, 27 Dec 2016 01:04:41 +0000 (23:04 -0200)]
mx6qsabreauto: Fix the EIM clock for the mx6qp variant
On the MX6Q the aclk_eim_slow_podf field is '1' after POR, while on the
MX6DQP it is '3'.
This makes the EIM clock to be only 66MHz on the mx6qp variant, instead of
132 MHz.
Instead of relying on the POR values for the CSMR1 register, make sure to
manually configure the clk_eim_slow_sel field as '00' so that EIM clock is
derived from AXI clock and the aclk_eim_slow_podf field as '1' so that EIM
clock can be AXI clock divided by 2.
This way a consistent EIM clock frequency is configured for all the mx6
variants.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
projects / thirdparty / u-boot.git / log
