Jakub Jelinek [Tue, 26 Nov 2013 21:29:30 +0000 (22:29 +0100)]
re PR tree-optimization/59014 (wrong code at -Os and above on x86_64-linux-gnu)
PR tree-optimization/59014
* tree-vrp.c (register_edge_assert_for_1): Don't look
through conversions from non-integral types or through
narrowing conversions.
Jakub Jelinek [Tue, 26 Nov 2013 21:27:19 +0000 (22:27 +0100)]
re PR sanitizer/59258 (ubsan: ICE(segfault): stack-buffer-overflow with -fsanitize=undefined)
PR sanitizer/59258
* ubsan.c (ubsan_source_location): Don't add any location
to ADDR_EXPR in the ctor. Revert 2013-11-22 change.
(ubsan_create_data): Strip block info from LOC.
Jakub Jelinek [Tue, 26 Nov 2013 20:55:39 +0000 (21:55 +0100)]
re PR middle-end/59273 (ICE in expand_expr_real_2, at expr.c:9188 on alpha)
PR middle-end/59273
* tree-vect-generic.c (optimize_vector_constructor): Don't optimize
if there isn't optab handler for the corresponding vector PLUS_EXPR.
Jakub Jelinek [Tue, 26 Nov 2013 20:54:37 +0000 (21:54 +0100)]
re PR rtl-optimization/59166 (ICE in simplify_subreg, at simplify-rtx.c:5901 on valid code (at -O1 and above with -g enabled))
PR rtl-optimization/59166
* ira.c (find_moveable_pseudos): Use DF_REF_REAL_LOC instead of
DF_REF_LOC in validate_change call.
(split_live_ranges_for_shrink_wrap): Likewise.
Jakub Jelinek [Tue, 26 Nov 2013 20:38:59 +0000 (21:38 +0100)]
re PR middle-end/59150 (ICE: in expand_one_var, at cfgexpand.c:1242 with -fopenmp)
PR middle-end/59150
* omp-low.c (lower_rec_input_clause): For reduction with placeholder
of references to constant size types in simd loops, defer emitting
initializer for the new_var, emit it later on only if not using
SIMD arrays for it.
Jakub Jelinek [Tue, 26 Nov 2013 20:38:10 +0000 (21:38 +0100)]
re PR middle-end/59152 (ICE: loop 2's latch does not have an edge to its header with -fopenmp -fipa-pure-const)
PR middle-end/59152
* omp-low.c (expand_omp_for_static_chunk): Don't set loop->latch
for the inner loop if collapse_bb is non-NULL.
(expand_omp_simd): Use cont_bb rather than e->dest as latch.
Richard Biener [Tue, 26 Nov 2013 15:14:52 +0000 (15:14 +0000)]
re PR tree-optimization/59245 (ICE on valid code at -O3 on x86_64-linux-gnu in set_value_range, at tree-vrp.c:443)
2013-11-26 Richard Biener <rguenther@suse.de>
PR tree-optimization/59245
* tree-vrp.c (set_value_range): Assert that we don't have
overflowed constants (but our infinities).
(set_value_range_to_value): Drop all overflow flags.
(vrp_visit_phi_node): Likewise.
(vrp_visit_assignment_or_call): Use set_value_range_to_value
to set a constant range.
H.J. Lu [Tue, 26 Nov 2013 13:31:25 +0000 (13:31 +0000)]
Add -fuse-ld=bfd/-fuse-ld=gold support to exec-tool.in
PR bootstrap/55552
* configure.ac (install_gold_as_default): New. Set to yes for
--disable-ld or --enable-gold=default.
(gcc_cv_ld_gold_srcdir): New.
(gcc_cv_ld): Also check in-tree gold if install_gold_as_default
is yes.
(ORIGINAL_LD_BFD_FOR_TARGET): New AC_SUBST.
(ORIGINAL_LD_GOLD_FOR_TARGET): Likewise.
* configure: Regenerated.
* exec-tool.in (ORIGINAL_LD_BFD_FOR_TARGET): New variable.
(ORIGINAL_LD_GOLD_FOR_TARGET): Likewise.
(original) [collect-ld && -fuse-ld=bfd]: Set to
$ORIGINAL_LD_BFD_FOR_TARGET.
(original) [collect-ld && -fuse-ld=gold]: Set to
$ORIGINAL_LD_GOLD_FOR_TARGET.
(dir) [collect-ld && ../gold/ld-new]: Set to gold.
(fast_install) [collect-ld && ../gold/ld-new]: Set to yes.
Terry Guo [Tue, 26 Nov 2013 11:58:37 +0000 (11:58 +0000)]
arm.c (require_pic_register): Handle high pic base register for thumb-1.
gcc/ChangeLog
2013-11-26 Terry Guo <terry.guo@arm.com>
* config/arm/arm.c (require_pic_register): Handle high pic base
register for thumb-1.
(arm_load_pic_register): Also initialize high pic base register.
* doc/invoke.texi: Update documentation for option -mpic-register.
gcc/testsuite/ChangeLog
2013-11-26 Terry Guo <terry.guo@arm.com>
* gcc.target/arm/thumb1-pic-high-reg.c: New case.
* gcc.target/arm/thumb1-pic-single-base.c: New case.
Oleg Endo [Tue, 26 Nov 2013 11:48:16 +0000 (11:48 +0000)]
re PR target/58314 (SH4 error: 'asm' operand requires impossible reload)
PR target/58314
PR target/50751
* config/sh/sh.c (max_mov_insn_displacement, disp_addr_displacement):
Prefix function names with 'sh_'. Make them non-static.
* config/sh/sh-protos.h (sh_disp_addr_displacement,
sh_max_mov_insn_displacement): Add declarations.
* config/sh/constraints.md (Q): Reject QImode.
(Sdd): Use match_code "mem".
(Snd): Fix erroneous matching of non-memory operands.
* config/sh/predicates.md (short_displacement_mem_operand): New
predicate.
(general_movsrc_operand): Disallow PC relative QImode loads.
* config/sh/sh.md (*mov<mode>_reg_reg): Remove it.
(*movqi, *movhi): Merge both insns into...
(*mov<mode>): ... this new insn. Replace generic 'm' constraints with
'Snd' and 'Sdd' constraints. Calculate insn length dynamically based
on the operand types.
James Greenhalgh [Tue, 26 Nov 2013 09:59:10 +0000 (09:59 +0000)]
[AArch64] [1/4 Fix vtbx1] Allow signed and unsigned versions of intrinsics
to coexist.
gcc/
* config/aarch64/aarch64-builtins.c
(VAR1): Use new naming scheme for aarch64_builtins.
(aarch64_builtin_vectorized_function): Use new
aarch64_builtins names.
Adam Butcher [Mon, 25 Nov 2013 07:43:55 +0000 (07:43 +0000)]
Disallow implicit function templates in local functions unless defining a lambda.
gcc/cp/
PR c++/59112
PR c++/59113
* parser.c (cp_parser_parameter_declaration_clause): Disallow implicit
function templates in local functions unless defining a lambda.
gcc/testsuite/
PR c++/59112
PR c++/59113
g++.dg/cpp1y/pr58533.C: Updated testcase.
g++.dg/cpp1y/pr59112.C: New testcase.
g++.dg/cpp1y/pr59113.C: New testcase.
Terry Guo [Mon, 25 Nov 2013 06:41:20 +0000 (06:41 +0000)]
invoke.texi (-mslow-flash-data): Document new option.
gcc/ChangeLog
2013-11-25 Terry Guo <terry.guo@arm.com>
* doc/invoke.texi (-mslow-flash-data): Document new option.
* config/arm/arm.opt (mslow-flash-data): New option.
* config/arm/arm-protos.h (arm_max_const_double_inline_cost): Declare
it.
* config/arm/arm.h (TARGET_USE_MOVT): Always true when literal pools
are disabled.
(arm_disable_literal_pool): Declare it.
* config/arm/arm.c (arm_disable_literal_pool): New variable.
(arm_option_override): Handle new option.
(thumb2_legitimate_address_p): Don't allow symbol references when
literal pools are disabled.
(arm_max_const_double_inline_cost): New function.
* config/arm/arm.md (types.md): Include it before ...
(use_literal_pool): New attribute.
(enabled): Use new attribute.
(split pattern): Replace symbol+offset with MOVW/MOVT.
gcc/testsuite/ChangeLog
2013-11-25 Terry Guo <terry.guo@arm.com>
Steven Bosscher [Sun, 24 Nov 2013 19:15:36 +0000 (19:15 +0000)]
jump.c (reset_insn_reg_label_operand_notes): New function, split out from ...
* jump.c (reset_insn_reg_label_operand_notes): New function,
split out from ...
(init_label_info): ... here. Reset LABEL_NUSES in cfglayout mode.
* cfgcleanup.c (delete_dead_jump_tables_between): New function,
split out from ...
(delete_dead_jumptables): ... here. Handle cfglayout mode.
(cleanup_cfg): Delete dead jump tables in cfglayout mode if an
expensive CFG cleanup is called for.
* cfgrtl.c (fixup_reorder_chain): Remove BARRIERs from fallthru paths.
(cfg_layout_finalize): Delete dead jump tables before re-building
the insns chain.
* ira.c (ira): Rebuild jump labels *after* deleting unreachable
basic blocks, not before.
* loop-init.c (rtl_loop_done): Call for an expensive CFG cleanup.
* modulo-sched.c (sms_schedule): Do not look for BARRIERs in the
insns chain of a scheduling extended basic block, they cannot appear
there in cfglayout mode.
Easwaran Raman [Sat, 23 Nov 2013 21:01:46 +0000 (21:01 +0000)]
re PR c++/59031 (vtable lookup not optimized away)
PR c++/59031
* call.c (build_new_method_call_1): Comnpare function context
with BASELINK_BINFO type rather than instance type before
marking the call with LOOKUP_NONVIRTUAL.
Jason Merrill [Sat, 23 Nov 2013 16:28:57 +0000 (11:28 -0500)]
re PR c++/58868 (ICE: in count_type_elements, at expr.c:5495 with -std=gnu++0x)
PR c++/58868
* init.c (build_aggr_init): Don't clobber the type of init
if we got an INIT_EXPR back from build_vec_init.
(build_vec_init): Do digest_init on trivial initialization.
David Edelsohn [Sat, 23 Nov 2013 15:25:09 +0000 (15:25 +0000)]
rs6000.c (IN_NAMED_SECTION): New macro.
* config/rs6000/rs6000.c (IN_NAMED_SECTION): New macro.
(rs6000_xcoff_select_section): Place decls with stricter alignment
into named sections.
(rs6000_xcoff_unique_section): Allow unique sections for
uninitialized data with strict alignment.
Jakub Jelinek [Sat, 23 Nov 2013 14:21:46 +0000 (15:21 +0100)]
re PR tree-optimization/59154 (internal compiler error: tree check: expected ssa_name, have integer_cst)
PR tree-optimization/59154
* tree-ssa-reassoc.c (maybe_optimize_range_tests): When changing
rhs1 of a cast and new_op is invariant, fold_convert it.
* tree-ssa-forwprop.c (ssa_forward_propagate_and_combine): Only call
simplify_conversion_from_bitmask if rhs1 is a SSA_NAME.
Uros Bizjak [Sat, 23 Nov 2013 13:24:19 +0000 (14:24 +0100)]
re PR target/56788 (_mm_frcz_sd and _mm_frcz_ss ignore their second argument)
PR target/56788
* config/i386/i386.c (bdesc_multi_arg) <IX86_BUILTIN_VFRCZSS>:
Declare as MULTI_ARG_1_SF instruction.
<IX86_BUILTIN_VFRCZSD>: Decleare as MULTI_ARG_1_DF instruction.
* config/i386/sse.md (*xop_vmfrcz<mode>2): Rename
from *xop_vmfrcz_<mode>.
* config/i386/xopintrin.h (_mm_frcz_ss): Use __builtin_ia32_movss
to merge scalar result with __A.
(_mm_frcz_sd): Use __builtin_ia32_movsd to merge scalar
result with __A.
Eric Botcazou [Sat, 23 Nov 2013 10:23:02 +0000 (10:23 +0000)]
gimplify.h (recalculate_side_effects): Delete.
* gimplify.h (recalculate_side_effects): Delete.
* gimplify.c (recalculate_side_effects): Make static and add comment.
ada/
* gcc-interface/trans.c (Loop_Statement_to_gnu): Set TREE_SIDE_EFFECTS
on the conditional expression directly.
sh.md: Use nonimmediate_operand rather than general_operand for the destination of a...
gcc/
* config/sh/sh.md: Use nonimmediate_operand rather than general_operand
for the destination of a define_peephole2. Likewise register_operand
rather than arith_reg_operand. Remove constraints from
define_peephole2s.
Cary Coutant [Fri, 22 Nov 2013 22:25:49 +0000 (22:25 +0000)]
Fix demangler to handle conversion operators correctly.
libiberty/
PR other/59195
* cp-demangle.c (struct d_info_checkpoint): New struct.
(struct d_print_info): Add current_template field.
(d_operator_name): Set flag when processing a conversion
operator.
(cplus_demangle_type): When processing <template-args> for
a conversion operator, backtrack if necessary.
(d_expression_1): Renamed from d_expression.
(d_expression): New wrapper around d_expression_1.
(d_checkpoint): New function.
(d_backtrack): New function.
(d_print_init): Initialize current_template.
(d_print_comp): Set current_template.
(d_print_cast): Put current_template in scope for
printing conversion operator name.
(cplus_demangle_init_info): Initialize is_expression and
is_conversion.
* cp-demangle.h (struct d_info): Add is_expression and
is_conversion fields.
* testsuite/demangle-expected: New test cases.
François Dumont [Fri, 22 Nov 2013 20:55:53 +0000 (20:55 +0000)]
safe_local_iterator.h (_Safe_local_iterator<>): Remove _M_bucket, use same information in normal local_iterator.
2013-11-22 François Dumont <fdumont@gcc.gnu.org>
* include/debug/safe_local_iterator.h (_Safe_local_iterator<>):
Remove _M_bucket, use same information in normal local_iterator.
(operator==): Remove redundant _M_can_compare check.
* include/debug/safe_local_iterator.tcc: Adapt.
* include/debug/unordered_set: Likewise.
* include/debug/unordered_map: Likewise.
* testsuite/Makefile.am (check_DEJAGNU_normal_targets): Add 10.
(check-DEJAGNU): Add normal10, run 28_regex/[ab]*
tests as another separate job.
* testsuite/Makefile.in: Regenerated.
Aldy Hernandez [Fri, 22 Nov 2013 20:08:44 +0000 (20:08 +0000)]
ipa.c (symtab_remove_unreachable_nodes): Fix up comment typos.
* ipa.c (symtab_remove_unreachable_nodes): Fix up comment typos.
* ipa-prop.c (get_vector_of_formal_parm_types): Renamed to ...
(ipa_get_vector_of_formal_parm_types): ... this. No longer static.
(ipa_modify_formal_parameters): Adjust caller. Remove
synth_parm_prefix argument. Use operator enum instead of bit fields.
Add assert for properly handling vector of references. Handle
creating brand new parameters.
(ipa_modify_call_arguments): Use operator enum instead of bit
fields.
(ipa_combine_adjustments): Same. Assert that IPA_PARM_OP_NEW is not
used.
(ipa_modify_expr, get_ssa_base_param, ipa_get_adjustment_candidate):
New functions.
(ipa_dump_param_adjustments): Rename reduction to new_decl.
Use operator enum instead of bit fields.
* ipa-prop.h (enum ipa_parm_op): New.
(struct ipa_parm_adjustment): New field op. Rename reduction
to new_decl, new_arg_prefix to arg_prefix and remove remove_param
and copy_param.
(ipa_modify_formal_parameters): Remove last argument.
(ipa_get_vector_of_formal_parm_types, ipa_modify_expr,
ipa_get_adjustment_candidate): New prototypes.
* tree-sra.c (turn_representatives_into_adjustments): Use operator
enum. Set arg_prefix.
(get_adjustment_for_base): Use operator enum.
(sra_ipa_modify_expr): Rename to ipa_modify_expr and move to
ipa-prop.c.
(sra_ipa_modify_assign): Rename sra_ipa_modify_expr to
ipa_modify_expr.
(ipa_sra_modify_function_body): Same. No longer static.
(sra_ipa_reset_debug_stmts): Use operator enum.
(modify_function): Do not pass prefix argument.
Co-Authored-By: Jakub Jelinek <jakub@redhat.com>
From-SVN: r205284
* sanitizer.def (BUILT_IN_UBSAN_HANDLE_MISSING_RETURN): New built-in.
* opts.c (common_handle_option): Add -fsanitize=return.
* flag-types.h (enum sanitize_code): Add SANITIZE_RETURN and
or it into SANITIZE_UNDEFINED.
c-family/
* c-ubsan.h (ubsan_instrument_return): New prototype.
* c-ubsan.c (ubsan_instrument_return): New function.
cp/
* cp-gimplify.c: Include target.h and c-family/c-ubsan.h.
(cp_ubsan_maybe_instrument_return): New function.
(cp_genericize): Call it if -fsanitize=return.
testsuite/
* g++.dg/ubsan/return-1.C: New test.
* g++.dg/ubsan/return-2.C: New test.
* sanitizer.def (BUILT_IN_ASAN_BEFORE_DYNAMIC_INIT,
BUILT_IN_ASAN_AFTER_DYNAMIC_INIT): New.
* asan.c (instrument_derefs): Handle also VAR_DECL loads/stores.
Don't instrument accesses to VAR_DECLs which are known to fit
into their bounds and the vars are known to have shadow bytes
indicating allowed access.
(asan_dynamic_init_call): New function.
(asan_add_global): If vnode->dynamically_initialized,
set __has_dynamic_init to 1 instead of 0.
(initialize_sanitizer_builtins): Add BT_FN_VOID_CONST_PTR var.
* asan.h (asan_dynamic_init_call): New prototype.
* cgraph.h (varpool_node): Add dynamically_initialized bitfield.
cp/
* decl2.c: Include asan.h.
(one_static_initialization_or_destruction): If -fsanitize=address,
init is non-NULL and guard is NULL, set
vnode->dynamically_initialized.
(do_static_initialization_or_destruction): Call
__asan_{before,after}_dynamic_init around the static initialization.
testsuite/
* c-c++-common/asan/no-redundant-instrumentation-1.c: Tweak to avoid
optimizing away some __asan_report* calls.
Martin Jambor [Fri, 22 Nov 2013 19:37:00 +0000 (20:37 +0100)]
re PR rtl-optimization/10474 (shrink wrapping for functions)
PR rtl-optimization/10474
* ira.c (interesting_dest_for_shprep_1): New function.
(interesting_dest_for_shprep): Use interesting_dest_for_shprep_1,
also check parallels.
testsuite/
* gcc.dg/pr10474.c: Also test ppc64.
* gcc.dg/ira-shrinkwrap-prep-1.c: Also tes ppc64, changed all ints
to longs.
* gcc.dg/ira-shrinkwrap-prep-2.c: Likewise.
Jeff Law [Fri, 22 Nov 2013 18:52:23 +0000 (11:52 -0700)]
tree-ssa-threadedge.c (record_temporary_equivalence): Handle NULL for RHS, which we used to invalidate equivalences.
* tree-ssa-threadedge.c (record_temporary_equivalence): Handle
NULL for RHS, which we used to invalidate equivalences.
(record_temporary_equivalences_from_phis): New bitmap arguments
and a boolean indicating if we have passed a backedge. If we
have passed a backedge, then set the appropriate bit in the
bitmaps for the SRC & DEST of PHIs creating equivalences.
(invalidate_equivalences, dummy_simplify): New functions.
(cond_arg_set_in_b): Remove.
(record_temporary_equivalences_from_stmts_at_dest): New bitmap
arguments and a boolean indicating if we have passed a backedge.
If we have passed a backedge, then perform invalidations as
needed.
(thread_around_empty_blocks): If we have seen a backedge, then
use the dummy simplify routine.
(thread_through_normal_block): Likewise. Pass bitmaps and
backedge status to children. Do not pessimize so much when
traversing backedges in the CFG.
(thread_across_edge): Manage the SRC_MAP/DST_MAP bitmaps.
If we have seen a backedge, then use the dummy simplify routine.
Do not pessimize so much when traversing backedges.
Michael Meissner [Fri, 22 Nov 2013 17:24:32 +0000 (17:24 +0000)]
re PR target/59054 (Powerpc -O0 -mcpu=power7 generates sub-optimal code to load 0)
2013-11-22 Michael Meissner <meissner@linux.vnet.ibm.com>
PR target/59054
* gcc.target/powerpc/direct-move.h (VSX_REG_ATTR): Allow test to
specify an appropriate register class for VSX operations.
(load_vsx): Use it.
(load_gpr_to_vsx): Likewise.
(load_vsx_to_gpr): Likewise.
* gcc.target/powerpc/direct-move-vint1.c: Use an appropriate
register class for VSX registers that the type can handle. Remove
checks for explicit number of instructions generated, just check
if the instruction is generated.
* gcc.target/powerpc/direct-move-vint2.c: Likewise.
* gcc.target/powerpc/direct-move-float1.c: Likewise.
* gcc.target/powerpc/direct-move-float2.c: Likewise.
* gcc.target/powerpc/direct-move-double1.c: Likewise.
* gcc.target/powerpc/direct-move-double2.c: Likewise.
* gcc.target/powerpc/direct-move-long1.c: Likewise.
* gcc.target/powerpc/direct-move-long2.c: Likewise.
Yuri Rumyantsev [Fri, 22 Nov 2013 16:33:40 +0000 (16:33 +0000)]
Enable AES, PCLMUL and RDRND for Silvermont
gcc/
2013-11-22 Yuri Rumyantsev <ysrumyan@gmail.com>
* config/i386/i386.c(processor_alias_table): Enable PTA_AES,
PTA_PCLMUL and PTA_RDRND for Silvermont.
* config/i386/driver-i386.c (host_detect_local_cpu): Set up cpu
for Silvermont.
* doc/invoke.texi: Mention AES, PCLMUL and RDRND for Silvermont.
Tejas Belagod [Fri, 22 Nov 2013 15:34:36 +0000 (15:34 +0000)]
aarch64-simd.md (vec_pack_trunc_<mode>, [...]): Swap for big-endian.
2013-11-22 Tejas Belagod <tejas.belagod@arm.com>
gcc/
* config/aarch64/aarch64-simd.md (vec_pack_trunc_<mode>,
vec_pack_trunc_v2df, vec_pack_trunc_df): Swap for big-endian.
(reduc_<sur>plus_<mode>): Factorize V2DI into this.
(reduc_<sur>plus_<mode>): Change this to reduc_splus_<mode> for floats
and also change to float UNSPEC.
(reduc_maxmin_uns>_<mode>): Remove V2DI.
* config/aarch64/arm_neon.h (vaddv<q>_<suf><8,16,32,64>,
vmaxv<q>_<suf><8,16,32,64>, vminv<q>_<suf><8,16,32,64>): Fix up scalar
result access for big-endian.
(__LANE0): New macro used to fix up lane access of 'across-lanes'
intrinsics for big-endian.
* config/aarch64/iterators.md (VDQV): Add V2DI.
(VDQV_S): New.
(vp): New mode attribute.
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