Neil Armstrong [Wed, 20 Aug 2025 09:49:23 +0000 (11:49 +0200)]
arm64: dts: qcom: sm8550: add PPI interrupt partitions for the ARM PMUs
The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper
interrupt partition maps and use the 4th interrupt cell to pass the
partition phandle for each ARM PMU node.
Neil Armstrong [Wed, 20 Aug 2025 09:49:22 +0000 (11:49 +0200)]
arm64: dts: qcom: sm8550: switch to interrupt-cells 4 to add PPI partitions
The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch
to interrupt-cells = <4> in the GIC node to allow adding an interrupt
partition map phandle as the 4th cell value for GIC_PPI interrupts.
Reading the hardware registers of the &slimbam on RB3 reveals that the BAM
supports only 23 pipes (channels) and supports 4 EEs instead of 2. This
hasn't caused problems so far since nothing is using the extra channels,
but attempting to use them would lead to crashes.
The bam_dma driver might warn in the future if the num-channels in the DT
are wrong, so correct the properties in the DT to avoid future regressions.
Shashank Maurya [Thu, 21 Aug 2025 17:54:28 +0000 (23:24 +0530)]
arm64: dts: qcom: lemans-evk: Enable Display Port
Lemans EVK board has two mini-DP connectors, connected to EDP0
and EDP1 phys. Other EDP phys are available on expansion
connectors for the mezzanine boards.
Enable EDP0 and EDP1 along with their corresponding PHYs.
Kamal Wadhwa [Fri, 20 Jun 2025 15:29:57 +0000 (20:59 +0530)]
arm64: dts: qcom: sm8550: Correct the min/max voltages for vreg_l6n_3p3
Voltage regulator 'vreg_l6n_3p3' max-microvolt prop is currently
configured at 3304000uV in different sm8550 board files. However this
is not a valid voltage value for 'pmic5_pldo502ln' type voltage
regulators.
Check below the max value(3200mV) in the regulator summary for min/max
used as 2800mV/3304mV in DT:-
regulator use open bypass opmode voltage current min max
---------------------------------------------------------------------
..
vreg_l6n_3p3 0 0 0 normal 2800mV 0mA 2800mV 3200mV
..
Correct the min/max value to 3200000uV, as that is the closest valid
value to 3.3V and Hardware team has also confirmed that its good to
support the consumers(camera sensors) of this regulator.
Casey Connolly [Thu, 19 Jun 2025 14:55:10 +0000 (16:55 +0200)]
arm64: dts: qcom: sdm845-oneplus-*: set constant-charge-current-max-microamp
Set the maximum constant charge current to use for this battery. While
the battery is likely comfortably capable of 4A or so, OnePlus didn't
include a secondary charger IC for parallel charging (instead they have
their proprietary Dash Charging). It's possible that this value could be
safely increased after some testing (and when we have support for
modelling the charger as a cooling device properly), but for now this
value is acceptable.
This is references from qcom,usb-icl-ua property in the downstream
vendor devicetree.
Gabor Juhos [Wed, 18 Jun 2025 20:14:09 +0000 (22:14 +0200)]
arm64: dts: qcom: ipq9574: use 'pcie' as node name for 'pcie0'
The PCI controller at address 28000000 supports PCIe only, so use 'pcie'
as node name for that. This ensures that all PCIe controller instance
nodes are using the same name.
SPI on SC8280XP requires DMA (GSI) mode to function properly. Without
it, SPI controllers fall back to FIFO mode, which causes:
[ 0.901296] geni_spi 898000.spi: error -ENODEV: Failed to get tx DMA ch
[ 0.901305] geni_spi 898000.spi: FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode
...
[ 45.605974] goodix-spi-hid spi0.0: SPI transfer timed out
[ 45.605988] geni_spi 898000.spi: Can't set CS when prev xfer running
[ 46.621555] spi_master spi0: failed to transfer one message from queue
[ 46.621568] spi_master spi0: noqueue transfer failed
[ 46.621577] goodix-spi-hid spi0.0: spi transfer error: -110
[ 46.621585] goodix-spi-hid spi0.0: probe with driver goodix-spi-hid failed with error -110
Therefore, describe GPI DMA controller nodes for qup{0,1,2}, and
describe DMA channels for SPI and I2C, UART is excluded for now, as
it does not yet support this mode.
Note that, since there is no public schematic, this is derived from
Windows drivers. The drivers do not expose any DMA channel mask
information, so all available channels are enabled.
arm64: dts: qcom: x1e80100-pmics: Disable pm8010 by default
pm8010 is a camera specific PMIC, and may not be present on some
devices. These may instead use a dedicated vreg for this purpose (Dell
XPS 9345, Dell Inspiron..) or use USB webcam instead of a MIPI one
alltogether (Lenovo Thinbook 16, Lenovo Yoga..).
Disable pm8010 by default, let platforms that actually have one onboard
enable it instead.
Cc: stable@vger.kernel.org Fixes: 2559e61e7ef4 ("arm64: dts: qcom: x1e80100-pmics: Add the missing PMICs") Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Link: https://lore.kernel.org/r/20250701183625.1968246-2-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Konrad Dybcio [Tue, 8 Jul 2025 10:28:42 +0000 (12:28 +0200)]
arm64: dts: qcom: qcm2290: Disable USB SS bus instances in park mode
2290 was found in the field to also require this quirk, as long &
high-bandwidth workloads (e.g. USB ethernet) are consistently able to
crash the controller otherwise.
The same change has been made for a number of SoCs in [1], but QCM2290
somehow escaped the list (even though the very closely related SM6115
was there).
Upon a controller crash, the log would read:
xhci-hcd.12.auto: xHCI host not responding to stop endpoint command
xhci-hcd.12.auto: xHCI host controller not responding, assume dead
xhci-hcd.12.auto: HC died; cleaning up
Add snps,parkmode-disable-ss-quirk to the DWC3 instance in order to
prevent the aforementioned breakage.
Bjorn Andersson [Fri, 15 Aug 2025 13:51:32 +0000 (08:51 -0500)]
Revert "arm64: dts: qcom: sm8450: add initial device tree for Samsung Galaxy S22"
This reverts commit 46952305d2b6 ("arm64: dts: qcom: sm8450: add initial
device tree for Samsung Galaxy S22"), as the merged version had been
superseded and received further feedback.
Luca Weiss [Wed, 11 Jun 2025 16:33:18 +0000 (18:33 +0200)]
arm64: dts: qcom: sdm632-fairphone-fp3: Enable display and GPU
Add the description for the display panel found on this phone.
Unfortunately the LCDB module on PMI632 isn't yet supported upstream so
we need to use a dummy regulator-fixed in the meantime.
And with this done we can also enable the GPU and set the zap shader
firmware path.
arm64: dts: qcom: ipq5424: Describe the 4-wire UART SE
QUPv3 in IPQ5424 consists of six Serial Engines (SEs). Describe the
first SE, which supports a 4-wire UART configuration suitable for
applications such as HS-UART.
Note that the required initialization for this SE is not handled by the
bootloader. Therefore, add the SE node in the device tree but keep it
reserved. Enable it once Linux gains support for configuring the SE,
allowing to use in relevant RDPs.
arm64: dts: qcom: sc7280: Add support for two additional DDR frequencies
The SC7280 SoC now supports two additional frequencies. This patch
add those frequencies to the BWMON OPP table and updates the frequency
mapping table accordingly.
These changes do not impact existing platforms, as the updated mapping
only affects the highest OPP. On any given platform, this will continue
to vote for the maximum available OPP.
Bjorn Andersson [Tue, 12 Aug 2025 03:11:35 +0000 (22:11 -0500)]
arm64: dts: qcom: sc7280: Add MDSS_CORE reset to mdss
Like on other platforms, if the OS does not support recovering the state
left by the bootloader it needs access to MDSS_CORE, so that it can
clear the MDSS configuration.
Until now it seems no version of the bootloaders have done so, but e.g.
the Particle Tachyon ships with a bootloader that does leave the display
in a state that results in a series of iommu faults.
So let's provide the reset, to allow the OS to clear that state.
Luca Weiss [Fri, 1 Aug 2025 13:51:05 +0000 (15:51 +0200)]
arm64: dts: qcom: sc7280: Add q6usbdai node
Add a node for q6usb which handles USB audio offloading, allowing to
play audio via a USB-C headset with lower power consumption and enabling
some other features.
We also need to set num-hc-interrupters for the dwc3 for the q6usb to be
able to use its sideband interrupter.
arm64: dts: qcom: move data-lanes to the DP-out endpoint
Support for the data-lanes declaration in the DP node is deprecated.
Move them to the corresponding endpoint as recommended by the current DP
bindings.
Follow the example of other DP controllers and also eDP controller on
SC7280 and move mdss_dp3_out endpoint declaration to the SoC
DTSI. This slightly reduces the boilerplate in the platform DT files and
also reduces the difference between DP and eDP controllers.
Follow the example of other DP controllers and also eDP controller on
SC7280 and move all mdss[01]_dp[0123]_out endpoints declaration to the
SoC DTSI. This slightly reduces the boilerplate in the platform DT files
and also reduces the difference between DP and eDP controllers.
Follow the example of other DP controllers and also eDP controller on
SC7280 and move mdss_edp_out endpoint declaration to the SoC DTSI. This
slightly reduces the boilerplate in the platform DT files and also
reduces the difference between DP and eDP controllers.
arm64: dts: qcom: sa8775p: remove aux clock from pcie phy
The gcc_aux_clk is used by the PCIe Root Complex (RC) and is not required
by the PHY. The correct clock for the PHY is gcc_phy_aux_clk, which this
patch uses to replace the incorrect reference.
The distinction between AUX_CLK and PHY_AUX_CLK is important: AUX_CLK is
typically used by the controller, while PHY_AUX_CLK is required by certain
PHYs—particularly Gen4 QMP PHYs—for internal operations such as clock
gating and power management. Some non-Gen4 Qualcomm PHYs also use
PHY_AUX_CLK, but they do not require AUX_CLK.
This change ensures proper clock configuration and avoids unnecessary
dependencies.
Signed-off-by: Ziyue Zhang <ziyue.zhang@oss.qualcomm.com> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Fixes: 489f14be0e0a ("arm64: dts: qcom: sa8775p: Add pcie0 and pcie1 nodes") Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250725102231.3608298-3-ziyue.zhang@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
sc7280.dtsi already includes the very same definition (bar 'memory@'
vs 'video@', which doesn't matter). Remove the duplicate to fix a lot
of dtbs W=1 warning instances (unique_unit_address_if_enabled).
Allow configuration of download mode via qcom_scm driver via specifying
download mode register address in the TCSR space. It is especially useful
for a clean watchdog reset without entry into download mode.
The problem remained un-noticed until now since error reporting for
missing download mode configuration feature was explicitly suppressed.
arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Enable HBR3 on external DPs
When no link frequencies are set, msm/dp driver defaults to HBR2 speed.
Explicitly list supported frequencies including HBR3/8.1Gbps for all
external DisplayPort(s).
arm64: dts: qcom: x1-crd: Enable HBR3 on external DPs
When no link frequencies are set, msm/dp driver defaults to HBR2 speed.
Explicitly list supported frequencies including HBR3/8.1Gbps for all
external DisplayPort(s).
arm64: dts: qcom: sdm845-db845c-navigation-mezzanine: Replace clock-frequency in camera sensor node
The clock-frequency for camera sensors has been deprecated in favour of
the assigned-clocks and assigned-clock-rates properties. Replace it in
the device tree.
Stephan Gerhold [Mon, 14 Jul 2025 11:48:15 +0000 (13:48 +0200)]
arm64: dts: qcom: x1e80100-crd: Add USB multiport fingerprint reader
The X1E80100 CRD has a Goodix fingerprint reader connected to the USB
multiport controller on eUSB6. All other ports (including USB super-speed
pins) are unused.
Set it up in the device tree together with the NXP PTN3222 repeater.
Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Tested-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250714-x1e80100-crd-fp-v2-1-3246eb02b679@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Notably, the one related to cluster0 requires that it's mapped with
the nE memory attribute. This is specific to a single instance, on this
platform only and should not be mimicked elsewhere.
dt-bindings: arm: qcom-soc: Document new Milos and Glymur SoCs
Extend the schema enforcing correct SoC-block naming to cover Milos
(compatibles already accepted by some maintainers for next release) and
Glymur (posted on mailing lists [1]) SoCs.
arm64: dts: qcom: qcs615: Set LDO12A regulator to HPM to avoid boot hang
On certain platforms (e.g., QCS615), consumers of LDO12A—such as PCIe,
UFS, and eMMC—may draw more than 10mA of current during boot. This can
exceed the regulator's limit in Low Power Mode (LPM), triggering current
limit protection and causing the system to hang.
To address this, there are two possible approaches:
a) Set the regulator's initial mode to High Performance Mode (HPM) in
the device tree.
b) Keep the default LPM setting and have each consumer driver explicitly
set its current load.
Since some regulators are shared among multiple consumers, and setting
the current must be coordinated across all of them, we will initially
adopt option a by setting the regulator to HPM. We can later migrate to
option b when the timing is appropriate and all consumer drivers are
ready.
Add the missing clkreq pinctrl entry to the PCIe1 node. This ensures proper
configuration of the CLKREQ# signal, which is needed for proper functioning
of PCIe ASPM.
George Moussalem [Mon, 21 Jul 2025 06:04:36 +0000 (10:04 +0400)]
arm64: dts: qcom: Update IPQ5018 xo_board_clk to use fixed factor clock
The xo_board_clk is fixed to 24 MHZ, which is routed from WiFi output
clock 96 MHZ (also being the reference clock of CMN PLL) divided by 4
to the analog block routing channel. Update the xo_board_clk nodes in
the board DTS files to use clock-div/clock-mult accordingly.
George Moussalem [Mon, 21 Jul 2025 06:04:35 +0000 (10:04 +0400)]
arm64: dts: ipq5018: Add CMN PLL node
Add CMN PLL node for enabling output clocks to the networking
hardware blocks on IPQ5018 devices.
The reference clock of CMN PLL is routed from XO to the CMN PLL
through the internal WiFi block.
.XO (48 MHZ) --> WiFi (multiplier/divider)--> 96 MHZ to CMN PLL.
arm64: dts: qcom: qcs8300: Add EPSS l3 interconnect provider node and CPUCP OPP tables to scale DDR/L3
Add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP tables
required to scale DDR and L3 per freq-domain on QCS8300 platform.
As QCS8300 and SA8775P SoCs have same EPSS hardware, added SA8775P
compatible as fallback for QCS8300 EPSS device node.
arm64: dts: qcom: x1e80100-qcp: enable pcie3 x8 slot for X1E80100-QCP
Add perst, wake and clkreq sideband signals and required regulators in
PCIe3 controller and PHY device tree node. Describe the voltage rails of
the x8 PCI slots for PCIe3 port.
Signed-off-by: Qiang Yu <qiang.yu@oss.qualcomm.com> Signed-off-by: Wenbin Yao <quic_wenbyao@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250722091151.1423332-4-quic_wenbyao@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
dt-bindings: arm: qcom: Drop redundant free-form SoC list
The schema and Devicetree specification defines how list of top-level
compatibles should be created, thus first paragraph explaining this is
completely redundant.
The list of SoCs is redundant as well, because the schema lists them.
On the other hand, Linux kernel should not be place to store marketing
names of some company products, so such list is irrelevant here.
arm64: dts: qcom: sdm845-samsung-starqltechn: fix GPIO lookup flags for i2c SDA and SCL
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.
arm64: dts: qcom: qrb4210-rb2: fix GPIO lookup flags for i2c SDA and SCL
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.
arm64: dts: qcom: qrb2210-rb1: fix GPIO lookup flags for i2c SDA and SCL
The I2C GPIO bus driver enforces the SDA and SCL pins as open-drain
outputs but the lookup flags in the DTS don't reflect that triggering
warnings from GPIO core. Add the appropriate flags.
George Moussalem [Mon, 30 Jun 2025 12:35:02 +0000 (16:35 +0400)]
arm64: dts: qcom: ipq5018: Add GE PHY to internal mdio bus
The IPQ5018 SoC contains an internal GE PHY, always at phy address 7.
As such, let's add the GE PHY node to the SoC dtsi.
The LDO controller found in the SoC must be enabled to provide constant
low voltages to the PHY. The mdio-ipq4019 driver already has support
for this, so adding the appropriate TCSR register offset.
In addition, the GE PHY outputs both the RX and TX clocks to the GCC
which gate controls them and routes them back to the PHY itself.
So let's create two DT fixed clocks and register them in the GCC node.
George Moussalem [Mon, 30 Jun 2025 12:35:01 +0000 (16:35 +0400)]
arm64: dts: qcom: ipq5018: Add MDIO buses
IPQ5018 contains two mdio buses of which one bus is used to control the
SoC's internal GE PHY, while the other bus is connected to external PHYs
or switches.
There's already support for IPQ5018 in the mdio-ipq4019 driver, so let's
simply add the mdio nodes for them.
Luo Jie [Tue, 10 Jun 2025 10:35:21 +0000 (18:35 +0800)]
arm64: dts: qcom: Update IPQ5424 xo_board to use fixed factor clock
xo_board is fixed to 24 MHZ, which is routed from WiFi output clock
48 MHZ (also being the reference clock of CMN PLL) divided 2 by
analog block routing channel.
Luo Jie [Tue, 10 Jun 2025 10:35:20 +0000 (18:35 +0800)]
arm64: dts: qcom: ipq5424: Add CMN PLL node
Add CMN PLL node for enabling output clocks to the networking
hardware blocks on IPQ5424 devices.
The reference clock of CMN PLL is routed from XO to the CMN PLL
through the internal WiFi block.
.XO (48 MHZ or 96 MHZ or 192 MHZ)-->WiFi (multiplier/divider)-->
48 MHZ to CMN PLL.
Luca Weiss [Thu, 1 May 2025 06:48:50 +0000 (08:48 +0200)]
arm64: dts: qcom: sm6350: Add q6usbdai node
Add a node for q6usb which handles USB audio offloading, allowing to
play audio via a USB-C headset with lower power consumption and enabling
some other features.
We also need to set num-hc-interrupters for the dwc3 for the q6usb to be
able to use its sideband interrupter.
Jens Glathe [Tue, 24 Jun 2025 06:46:00 +0000 (08:46 +0200)]
arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: add Bluetooth support
To enable Bluetooth pwrseq appears to be required for the WCN7850.
Add the nodes from QCP, add the TODO hint for vreg_wcn_0p95 and
vreg_wcn_1p9
Add uart14 for the BT interface.
Akhil P Oommen [Mon, 23 Jun 2025 14:12:09 +0000 (19:42 +0530)]
arm64: dts: qcom: x1p42100: Add GPU support
X1P42100 SoC has a new GPU called Adreno X1-45 which is a smaller
version of Adreno X1-85 GPU. Describe this new GPU and also add
the secure gpu firmware path that should used for X1P42100 CRD.
Tested-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> # x1-26-100 Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250623-x1p-adreno-v4-4-d2575c839cbb@oss.qualcomm.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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