Paolo Carlini [Thu, 4 Aug 2016 19:22:58 +0000 (19:22 +0000)]
re PR c++/72800 (ICE on invalid C++14 code with initialized lambda capture: tree check: expected class ‘type’, have ‘exceptional’ (error_mark) in add_capture, at cp/lambda.c:505)
/cp
2016-08-04 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/72800
* lambda.c (add_capture): Check lambda_capture_field_type return
value for error_mark_node.
/testsuite
2016-08-04 Paolo Carlini <paolo.carlini@oracle.com>
Patrick Palka [Thu, 4 Aug 2016 18:11:08 +0000 (18:11 +0000)]
Designate the widest case label to be the default label
gcc/ChangeLog:
* gimple.c (preprocess_case_label_vec_for_gimple): When the case
labels are exhaustive, designate the label with the widest
range to be the default label.
Marcel Böhme [Thu, 4 Aug 2016 16:53:18 +0000 (16:53 +0000)]
re PR c++/71696 (Libiberty Demangler segfaults (6))
2016-08-04 Marcel Böhme <boehme.marcel@gmail.com>
PR c++/71696
* cplus-dem.c: Prevent infinite recursion when there is a cycle
in the referencing of remembered mangled types.
(work_stuff): New stack to keep track of the remembered mangled
types that are currently being processed.
(push_processed_type): New method to push currently processed
remembered type onto the stack.
(pop_processed_type): New method to pop currently processed
remembered type from the stack.
(work_stuff_copy_to_from): Copy values of new variables.
(delete_non_B_K_work_stuff): Free stack memory.
(demangle_args): Push/Pop currently processed remembered type.
(do_type): Do not demangle a cyclic reference and push/pop
referenced remembered type.
When using gccgo on systems without full support for split stacks a
recursive template can overrun the available stack space. Reduce the
limit from 100000 to 10000 to make this less likely. It's still high
enough that real uses will work.
Thomas Schwinge [Thu, 4 Aug 2016 13:35:19 +0000 (15:35 +0200)]
C/C++: Simplify handling of location information for OpenACC routine directives
gcc/c/
* c-parser.c (struct oacc_routine_data): New.
(c_parser_declaration_or_fndef, c_parser_oacc_routine): Use it.
Simplify code.
(c_finish_oacc_routine): Likewise. Don't attach clauses to "omp
declare target" attribute.
gcc/cp/
* parser.h (struct cp_omp_declare_simd_data): New.
(struct cp_parser): Use it for oacc_routine member.
* parser.c (cp_ensure_no_oacc_routine, cp_parser_oacc_routine)
(cp_parser_late_parsing_oacc_routine, cp_finalize_oacc_routine):
Use it. Simplify code.
(cp_parser_new): Initialize all members pointing to special
parsing data structures.
(cp_parser_cilk_simd_fn_vector_attrs): Initialize
parser->cilk_simd_fn_info->clauses.
(cp_parser_omp_declare_simd): Initialize
parser->omp_declare_simd->clauses.
(cp_parser_late_parsing_omp_declare_simd): Simplify code.
PR rtl-optimization/71779
* emit-rtl.c (set_reg_attrs_from_value): Only propagate REG_POINTER,
if the value was sign-extended according to POINTERS_EXTEND_UNSIGNED
or if it was truncated.
* testsuite/20_util/enable_shared_from_this/members/reinit.cc: Use
effective target not dg-options. Move check for feature-test macro to:
* testsuite/20_util/enable_shared_from_this/members/weak_from_this.cc:
New test.
* tree-vrp.c (set_value_range): Use vrp_equiv_obstack with
BITMAP_ALLOC.
(add_equivalence): Likewise.
(get_value_range): Allocate value range with vrp_value_range_pool.
(vrp_initialize): Initialize vrp_equiv_obstack for equiv allocation.
(vrp_finalize): Relase vrp_equiv_obstack and vrp_value_range_pool.
The code that handled +build lines did not correctly require them to all
be true. While looking into this I discovered that multiple +build
lines were mishandled in a different way, because the shell does not
preseve line breaks in backquoted data. Look for the +build token to
tell us when we are switching from one +build line to another.
compiler: improve type caching for interface types
Add a cached to Interface_info_expression::do_type() so as to reuse
previously created interface types. This change reduces gccgo peak heap
usage when compiling the "fmt" package from around 16mb to around 10mb.
Jonathan Wakely [Wed, 3 Aug 2016 19:10:06 +0000 (20:10 +0100)]
Define feature-test macro for std::enable_shared_from_this
* include/bits/shared_ptr_base.h (__cpp_lib_enable_shared_from_this):
Define feature-test macro.
* testsuite/20_util/enable_shared_from_this/members/reinit.cc: Test
for the macro.
PR middle-end/71876
* calls.c (special_function_p): Remove special handling of
"setjmp_syscall", "qsetjmp", "longjmp", "siglongjmp" and the
prefix "__x". Recognize "savectx", "vfork" and "getcontext" only
without prefix. Remove potentially unsafe ECF_LEAF and ECF_NORETURN.
Alan Modra [Wed, 3 Aug 2016 00:42:06 +0000 (10:12 +0930)]
[RS6000] power8 unaligned fp load/store
According to the POWER8 Processor User’s Manual and some
experimentation on power8 hardware, unaligned fp load/store on power8
does not invoke the alignment interrupt.
* config/rs6000/rs6000.h (SLOW_UNALIGNED_ACCESS): Make scalar
float access depend on TARGET_EFFICIENT_UNALIGNED_VSX.
* config/rs6000/rs6000.opt (-mefficient-unaligned-vsx): Renamed
from -mefficient-unaligned-vector. Note that this affects fp too.
Roger Sayle [Tue, 2 Aug 2016 18:01:14 +0000 (18:01 +0000)]
expr.c (push_value): Only call flush_quick_stack for non-constant arguments.
2016-08-02 Roger Sayle <roger@nextmovesoftware.com>
* expr.c (push_value): Only call flush_quick_stack for non-constant
arguments.
(build_java_throw_out_of_bounds_exception): No longer wrap calls
to _Jv_ThowBadArrayIndex in a COMPOUND_EXPR as no longer needed.
(java_check_reference): Annotate COND_EXPR with __builtin_expect
to indicate that calling _Jv_ThrowNullPointerException is unlikely.
(build_java_arrayaccess): Construct an unlikely COND_EXPR instead
of a TRUTH_ANDIF_EXPR in a COMPOUND_EXPR. Only generate array
index MULT_EXPR when size_exp is not unity.
(build_array_length_annotation): When optimizing, generate a write
to the allocated array's length field to expose constant lengths
to GCC's optimizers.
(build_newarray): Call new build_array_length_annotation.
(build_anewarray): Likewise.
re PR rtl-optimization/69847 (Spec 2006 403.gcc slows down with -mlra vs. reload on PowerPC)
2016-08-02 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/69847
* lra-int.h (struct lra-reg): Use restore_rtx instead of
restore_regno.
(lra_rtx_hash): New.
* lra.c (initialize_lra_reg_info_element): Use restore_rtx instead
of restore_regno.
(lra_rtx_hash): Rename and move lra-remat.c::rtx_hash.
* lra-remat.c (rtx_hash): Rename and Move to lra.c.
* lra-spills.c (lra_final_code_change): Don't delete insn when the
next insn is USE with the same reg as the current insn source.
* lra-constraints.c (curr_insn_transform): Use restore_rtx instead
of restore_regno.
(lra_constraints_init): Call initiate_invariants.
(lra_constraints_finish): Call finish_invariants.
(struct invariant, invariant_t, invariant_ptr_t): New.
(const_invariant_ptr_t, invariants, invariants_pool): New.
(invariant_table, invariant_hash, invariant_eq_p): New.
(insert_invariant, initiate_invariants, finish_invariants): New.
(clear_invariants, invalid_invariant_regs): New.
(inherit_reload_reg, split_reg, fix_bb_live_info): Use restore_rtx
instead of restore_regno.
(invariant_p, process_invariant_for_inheritance): New.
(inherit_in_ebb): Implement invariant inheritance.
(lra_inheritance): Initialize and finalize invalid_invariant_regs.
(remove_inheritance_pseudos): Implement undoing invariant
inheritance.
(undo_optional_reloads, lra_undo_inheritance): Use restore_rtx
instead of restore_regno.
* lra-assigns.c (regno_live_length): New.
(reload_pseudo_compare_func): Use regno_live_length.
(assign_by_spills): Use restore_rtx instead of restore_regno.
(lra_assign): Ditto. Initiate regno_live_length.
Jonathan Wakely [Tue, 2 Aug 2016 13:32:26 +0000 (14:32 +0100)]
Skip C tests if test flags include C++ options
* testsuite/18_support/bad_exception/23591_thread-1.c: Skip test if
options are present that aren't valid for C.
* testsuite/abi/header_cxxabi.c: Likewise.
rs6000-c.c (altivec_resolve_overloaded_builtin): Add support for vec_extract on vector float...
[gcc]
2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/rs6000-c.c (altivec_resolve_overloaded_builtin):
Add support for vec_extract on vector float, vector int, vector
short, and vector char vector types.
* config/rs6000/rs6000.c (rs6000_expand_vector_extract): Add
vector float, vector int, vector short, and vector char
optimizations on 64-bit ISA 2.07 systems for both constant and
variable element numbers.
(rs6000_split_vec_extract_var): Likewise.
* config/rs6000/vsx.md (vsx_xscvspdp_scalar2): Allow SFmode to be
Altivec registers on ISA 2.07 and above.
(vsx_extract_v4sf): Delete alternative that hard coded element 0,
which never was matched due to the split occuring before register
allocation (and the code would not have worked on little endian
systems if it did match). Allow extracts to go to the Altivec
registers if ISA 2.07 (power8). Change from using "" around the
C++ code to using {}'s.
(vsx_extract_v4sf_<mode>_load): New insn to optimize vector float
vec_extracts when the vector is in memory.
(vsx_extract_v4sf_var): New insn to optimize vector float
vec_extracts when the element number is variable on 64-bit ISA
2.07 systems.
(vsx_extract_<mode>, VSX_EXTRACT_I iterator): Add optimizations
for 64-bit ISA 2.07 as well as ISA 3.0.
(vsx_extract_<mode>_p9, VSX_EXTRACT_I iterator): Likewise.
(vsx_extract_<mode>_p8, VSX_EXTRACT_I iterator): Likewise.
(vsx_extract_<mode>_load, VSX_EXTRACT_I iterator): New insn to
optimize vector int, vector short, and vector char vec_extracts
when the vector is in memory.
(vsx_extract_<mode>_var, VSX_EXTRACT_I iterator): New insn to
optimize vector int, vector short, and vector char vec_extracts
when the element number is variable.
[gcc/testsuite]
2016-08-01 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/vec-extract-5.c: New tests to test
vec_extract for vector float, vector int, vector short, and vector
char.
* gcc.target/powerpc/vec-extract-6.c: Likewise.
* gcc.target/powerpc/vec-extract-7.c: Likewise.
* gcc.target/powerpc/vec-extract-8.c: Likewise.
* gcc.target/powerpc/vec-extract-9.c: Likewise.
Wilco Dijkstra [Mon, 1 Aug 2016 16:37:24 +0000 (16:37 +0000)]
This patch optimizes the prolog and epilog code to reduce the number of instructions and avoid multiple writes to SP.
This patch optimizes the prolog and epilog code to reduce the number of
instructions and avoid multiple writes to SP. The key idea is that epilogs
are almost exact reverses of prologs, and thus all the decisions only need
to be taken once. The frame layout is decided in aarch64_layout_frame()
and decisions recorded in the new aarch64_frame fields initial_adjust,
callee_adjust, callee_offset and final_adjust.
The epilog reverses this, and may omit step 3 if alloca wasn't used.
gcc/
* config/aarch64/aarch64.h (aarch64_frame):
Remove padding0 and hardfp_offset. Add locals_offset,
initial_adjust, callee_adjust, callee_offset and final_adjust.
* config/aarch64/aarch64.c (aarch64_layout_frame):
Remove unused padding0 and hardfp_offset initializations.
Choose frame layout and set frame variables accordingly.
Use INVALID_REGNUM instead of FIRST_PSEUDO_REGISTER.
(aarch64_push_regs): Use INVALID_REGNUM, not FIRST_PSEUDO_REGISTER.
(aarch64_pop_regs): Likewise.
(aarch64_expand_prologue): Remove all decision code, just emit
prolog according to frame variables.
(aarch64_expand_epilogue): Remove all decision code, just emit
epilog according to frame variables.
(aarch64_initial_elimination_offset): Use offset to local/arg area.
testsuite/
* gcc.target/aarch64/test_frame_10.c: Fix test to check for a
single stack adjustment, no writeback.
* gcc.target/aarch64/test_frame_12.c: Likewise.
* gcc.target/aarch64/test_frame_13.c: Likewise.
* gcc.target/aarch64/test_frame_15.c: Likewise.
* gcc.target/aarch64/test_frame_6.c: Likewise.
* gcc.target/aarch64/test_frame_7.c: Likewise.
* gcc.target/aarch64/test_frame_8.c: Likewise.
* gcc.target/aarch64/test_frame_16.c: New test.
Jason Merrill [Mon, 1 Aug 2016 15:01:03 +0000 (11:01 -0400)]
PR c++/72766 - ICE with VLA
* constexpr.c (cxx_eval_pointer_plus_expression): Check constancy
of nelts.
* cp-gimplify.c (cp_fully_fold): Only maybe_constant_value in
C++11 and up.
H.J. Lu [Mon, 1 Aug 2016 14:46:01 +0000 (14:46 +0000)]
Convert V1TImode register to TImode in debug insn
TImode register referenced in debug insn can be converted to V1TImode by
scalar to vector optimization. When converting a TImode store to V1TImode,
we need to check all debug insns on its use chain to convert the V1TImode
register to SUBREG TImode if source register is undefined.
gcc/
PR target/72748
* config/i386/i386.c (timode_scalar_chain::convert_insn): Call
fix_debug_reg_uses after changing source register mode to
V1TImode if source register is undefined.
gcc/testsuite/
PR target/72748
* gcc.target/i386/pr72748.c: New test.
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