Michael Meissner [Wed, 12 Jun 2013 22:41:38 +0000 (22:41 +0000)]
rs6000.c (emit_load_locked): Add support for power8 byte, half-word, and quad-word atomic instructions.
[gcc]
2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* config/rs6000/rs6000.c (emit_load_locked): Add support for
power8 byte, half-word, and quad-word atomic instructions.
(emit_store_conditional): Likewise.
(rs6000_expand_atomic_compare_and_swap): Likewise.
(rs6000_expand_atomic_op): Likewise.
* config/rs6000/sync.md (larx): Add new modes for power8.
(stcx): Likewise.
(AINT): New mode iterator to include TImode as well as normal
integer modes on power8.
(fetchop_pred): Use int_reg_operand instead of gpc_reg_operand so
that VSX registers are not considered. Use AINT mode iterator
instead of INT1 to allow inclusion of quad word atomic operations
on power8.
(load_locked<mode>): Likewise.
(store_conditional<mode>): Likewise.
(atomic_compare_and_swap<mode>): Likewise.
(atomic_exchange<mode>): Likewise.
(atomic_nand<mode>): Likewise.
(atomic_fetch_<fetchop_name><mode>): Likewise.
(atomic_nand_fetch<mode>): Likewise.
(mem_thread_fence): Use gen_loadsync_<mode> instead of enumerating
each type.
(ATOMIC): On power8, add QImode, HImode modes.
(load_locked<QHI:mode>_si): Varients of load_locked for QI/HI
modes that promote to SImode.
(load_lockedti): Convert TImode arguments to PTImode, so that we
get a guaranteed even/odd register pair.
(load_lockedpti): Likewise.
(store_conditionalti): Likewise.
(store_conditionalpti): Likewise.
* config/rs6000/rs6000.md (QHI): New mode iterator for power8
atomic load/store instructions.
(HSI): Likewise.
[gcc/testsuite]
2013-06-12 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* gcc.target/powerpc/atomic-p7.c: New file, add tests for atomic
load/store instructions on power7, power8.
* gcc.target/powerpc/atomic-p8.c: Likewise.
Co-Authored-By: Pat Haugen <pthaugen@us.ibm.com> Co-Authored-By: Peter Bergner <bergner@vnet.ibm.com>
From-SVN: r200044
Balaji V. Iyer [Wed, 12 Jun 2013 22:03:20 +0000 (22:03 +0000)]
fix pr c/57577
fix pr c/57577
gcc/c/ChangeLog
+2013-06-12 Balaji V. Iyer <balaji.v.iyer@intel.com>
+
+ * c-array-notation.c (build_array_notation_expr): Reject array notation
+ mismatch between LHS and RHS even inside a call_expr. Also, removed
+ a couple while statements that were dead code.
+
gcc/testsuite/ChangeLog
+2013-06-12 Balaji V. Iyer <balaji.v.iyer@intel.com>
+
+ PR c/57577
+ * c-c++-common/cilk-plus/AN/pr57577.c: New testcase.
+
Paolo Carlini [Wed, 12 Jun 2013 21:36:36 +0000 (21:36 +0000)]
re PR c++/38958 ('unused variable' warning emitted when extending the lifetime of a returned RAII type by holding a reference to const despite delayed destructor side-effects. [dtor])
/cp
2013-06-12 Paolo Carlini <paolo.carlini@oracle.com>
PR c++/38958
* decl.c (poplevel): For the benefit of -Wunused-variable see
through references.
/testsuite
2013-06-12 Paolo Carlini <paolo.carlini@oracle.com>
Sofiane Naci [Wed, 12 Jun 2013 15:34:06 +0000 (15:34 +0000)]
aarch64-simd.md (aarch64_combine<mode>): convert to split.
* config/aarch64/aarch64-simd.md (aarch64_combine<mode>): convert to split.
(aarch64_simd_combine<mode>): New instruction expansion.
* config/aarch64/aarch64-protos.h (aarch64_split_simd_combine): New
function prototype.
* config/aarch64/aarch64.c (aarch64_split_combine): New function.
* config/aarch64/iterators.md (Vdbl): Add entry for DF.
Jan Hubicka [Wed, 12 Jun 2013 14:41:12 +0000 (16:41 +0200)]
cgraph.c (verify_edge_corresponds_to_fndecl): Be lax about decl has when in streaming stage.
* cgraph.c (verify_edge_corresponds_to_fndecl): Be lax about
decl has when in streaming stage.
* lto-symtab.c (lto_symtab_merge_symbols): Likewise.
* cgraph.h (cgraph_state): Add CGRAPH_LTO_STREAMING.
* lto.c (read_cgraph_and_symbols): Set cgraph into streaming state.
Eric Botcazou [Wed, 12 Jun 2013 08:17:58 +0000 (08:17 +0000)]
expr.c (expand_expr_real_1): Use straight-line flow.
* expr.c (expand_expr_real_1) <TARGET_MEM_REF>: Use straight-line flow.
<MEM_REF>: Use 'type' instead of TREE_TYPE (exp) and tidy up the first
part. Use straight-line flow at the end.
<COMPONENT_REF>: Remove superfluous else.
<VIEW_CONVERT_EXPR>: Use 'type' instead of TREE_TYPE (exp).
Jakub Jelinek [Wed, 12 Jun 2013 06:43:05 +0000 (08:43 +0200)]
re PR target/56564 (movdqa on possibly-8-byte-aligned struct with -O3)
PR target/56564
* varasm.c (decl_binds_to_current_def_p): Call binds_local_p
target hook even for !TREE_PUBLIC decls. If no resolution info
is available, return false for common and external decls.
Jan Hubicka [Tue, 11 Jun 2013 22:41:54 +0000 (00:41 +0200)]
c-common.c (handle_alias_ifunc_attribute): Do not set DECL_EXTERNAL for weakref variables.
* c-family/c-common.c (handle_alias_ifunc_attribute): Do not set
DECL_EXTERNAL for weakref variables.
* c-family/c-pragma.c (handle_pragma_weak): Make sure aliases
are not declared as external.
* cgraph.c (cgraph_create_function_alias): Set weakref flag.
* cgraph.h (symtab_node_base): Add weakref flag.
* cgraphunit.c (cgraph_reset_node): Clear weakref flag.
(handle_alias_pairs): Set weakref flag, do not set DECL_EXTERNAL.
(output_weakrefs): Use weakref flag.
* fold-const.c (simple_operand_p): Handle WEAK.
* gimple-fold.c (can_refer_decl_in_current_unit_p): Drop weakref.
* ipa.c (varpool_externally_visible_p): Drop weakref.
(function_and_variable_visibility): Update comment; fix weakref
sanity checks; do not clear DECL_WEAK on them.
* lto-cgraph.c (lto_output_node): update.
(lto_output_varpool_node): Update.
(input_overwrite_node): Update.
(input_node): Update.
(input_varpool_node): Update.
* lto-symtab.c (lto_symtab_symbol_p): Do not special case weakrefs.
(lto_symtab_merge_symbols): Add sanity check.
(lto_symtab_prevailing_decl): Do not special case weakrefs.
* passes.c (rest_of_decl_compilation): Set static flag, too.
* symtab.c (dump_symtab_base): Dump weakref.
(verify_symtab_base): Sanity check weakrefs.
(symtab_make_decl_local): Remove duplicated code.
(symtab_alias_ultimate_target): Simplify.
* varpool.c (varpool_create_variable_alias): Set weakref flag.
* lto-partition.c (get_symbol_class): Simplify weakref handling.
(add_symbol_to_partition_1): Likewise.
(contained_in_symbol): Likewise.
(lto_balanced_map): Likewise.
(rename_statics): Drop weakref.
* config/rs6000/rs6000.c (enum rs6000_reg_type): Simplify register
classes into bins based on the physical register type.
(reg_class_to_reg_type): Likewise.
(IS_STD_REG_TYPE): Likewise.
(IS_FP_VECT_REG_TYPE): Likewise.
(reload_fpr_gpr): Arrays to determine what insn to use if we can
use direct move instructions.
(reload_gpr_vsx): Likewise.
(reload_vsx_gpr): Likewise.
(rs6000_init_hard_regno_mode_ok): Precalculate the register type
information that is a simplification of register classes. Also
precalculate direct move reload helpers.
(direct_move_p): New function to return true if the operation can
be done as a direct move instruciton.
(quad_load_store_p): New function to return true if the operation
is a quad memory operation.
(rs6000_legitimize_address): If quad memory, only allow register
indirect for TImode addresses.
(rs6000_legitimate_address_p): Likewise.
(enum reload_reg_type): Delete, replace with rs6000_reg_type.
(rs6000_reload_register_type): Likewise.
(register_to_reg_type): Return register type.
(rs6000_secondary_reload_simple_move): New helper function for
secondary reload and secondary memory needed to identify anything
that is a simple move, and does not need reloading.
(rs6000_secondary_reload_direct_move): New helper function for
secondary reload to identify cases that can be done with several
instructions via the direct move instructions.
(rs6000_secondary_reload_move): New helper function for secondary
reload to identify moves between register types that can be done.
(rs6000_secondary_reload): Add support for quad memory operations
and for direct move.
(rs6000_secondary_memory_needed): Likewise.
(rs6000_debug_secondary_memory_needed): Change argument names.
(rs6000_output_move_128bit): New function to return the move to
use for 128-bit moves, including knowing about the various
limitations of quad memory operations.
* config/rs6000/vsx.md (vsx_mov<mode>): Add support for quad
memory operations. call rs6000_output_move_128bit for the actual
instruciton(s) to generate.
(vsx_movti_64bit): Likewise.
* config/rs6000/rs6000.md (UNSPEC_P8V_FMRGOW): New unspec values.
(UNSPEC_P8V_MTVSRWZ): Likewise.
(UNSPEC_P8V_RELOAD_FROM_GPR): Likewise.
(UNSPEC_P8V_MTVSRD): Likewise.
(UNSPEC_P8V_XXPERMDI): Likewise.
(UNSPEC_P8V_RELOAD_FROM_VSX): Likewise.
(UNSPEC_FUSION_GPR): Likewise.
(FMOVE128_GPR): New iterator for direct move.
(f32_lv): New mode attribute for load/store of SFmode/SDmode
values.
(f32_sv): Likewise.
(f32_dm): Likewise.
(zero_extend<mode>di2_internal1): Add support for power8 32-bit
loads and direct move instructions.
(zero_extendsidi2_lfiwzx): Likewise.
(extendsidi2_lfiwax): Likewise.
(extendsidi2_nocell): Likewise.
(floatsi<mode>2_lfiwax): Likewise.
(lfiwax): Likewise.
(floatunssi<mode>2_lfiwzx): Likewise.
(lfiwzx): Likewise.
(fix_trunc<mode>_stfiwx): Likewise.
(fixuns_trunc<mode>_stfiwx): Likewise.
(mov<mode>_hardfloat, 32-bit floating point): Likewise.
(mov<move>_hardfloat64, 64-bit floating point): Likewise.
(parity<mode>2_cmpb): Set length/type attr.
(unnamed shift right patterns, mov<mode>_internal2): Change type attr
for 'mr.' to fast_compare.
(bpermd_<mode>): Change type attr to popcnt.
(p8_fmrgow_<mode>): New insns for power8 direct move support.
(p8_mtvsrwz_1): Likewise.
(p8_mtvsrwz_2): Likewise.
(reload_fpr_from_gpr<mode>): Likewise.
(p8_mtvsrd_1): Likewise.
(p8_mtvsrd_2): Likewise.
(p8_xxpermdi_<mode>): Likewise.
(reload_vsx_from_gpr<mode>): Likewise.
(reload_vsx_from_gprsf): Likewise.
(p8_mfvsrd_3_<mode>): LIkewise.
(reload_gpr_from_vsx<mode>): Likewise.
(reload_gpr_from_vsxsf): Likewise.
(p8_mfvsrd_4_disf): Likewise.
(multi-word GPR splits): Do not split direct moves or quad memory
operations.
[gcc/testsuite]
2013-06-10 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
libgomp/
* testsuite/libgomp.c/icv-2.c: Extend current handling of
Linux-based x86 systems to cover all GNU systems.
* testsuite/libgomp.c/lock-3.c: Likewise.
* testsuite/libgomp.c/pr48591.c: Likewise.
Jonathan Wakely [Sun, 9 Jun 2013 23:54:07 +0000 (23:54 +0000)]
mutex (call_once): Remove parentheses to fix error in c++1y and gnu++1y mode.
* include/std/mutex (call_once): Remove parentheses to fix error in
c++1y and gnu++1y mode.
* testsuite/30_threads/mutex/try_lock/2.cc: Call try_lock() in new
thread to avoid undefined behaviour.
re PR rtl-optimization/57559 (S/390: ICE with lra)
2013-06-08 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/57559
* lra-constraints.c (process_alt_operands): Don't discourage
memory with known offset for offsetable memory constraint.
* lra.c (lra_emit_add): Exchange y and z for 2-op add insn.
2013-06-08 Vladimir Makarov <vmakarov@redhat.com>
PR rtl-optimization/57559
* gcc.target/s390/pr57559.c : New test.
Walter Lee [Sat, 8 Jun 2013 16:26:32 +0000 (16:26 +0000)]
atomic.h: Don't include stdint.h or features.h.
* config/tilepro/atomic.h: Don't include stdint.h or features.h.
Replace int64_t with long long. Add __extension__ where
appropriate.
* config/tilepro/atomic.c: Include config.h.
Balaji V. Iyer [Fri, 7 Jun 2013 17:41:52 +0000 (17:41 +0000)]
Moved array notation helper functions from c/ to c-family/ files.
2013-06-07 Balaji V. Iyer <balaji.v.iyer@intel.com>
* c-array-notation.c (length_mismatch_in_expr_p): Moved this
function to c-family/array-notation-common.c.
(is_cilkplus_reduce_builtin): Likewise.
(find_rank): Likewise.
(extract_array_notation_exprs): Likewise.
(replace_array_notations): Likewise.
(find_inv_trees): Likewise.
(replace_inv_trees): Likewise.
(contains_array_notation_expr): Likewise.
(find_correct_array_notation_type): Likewise.
(replace_invariant_exprs): Initialized additional_tcodes to NULL.
(struct inv_list): Moved this to c-family/array-notation-common.c.
* c-tree.h (is_cilkplus_builtin_reduce): Remove prototype.
2013-06-07 Balaji V. Iyer <balaji.v.iyer@intel.com>
* array-notation-common.c (length_mismatch_in_expr_p): Moved this
function from c/c-array-notation.c.
(is_cilkplus_reduce_builtin): Likewise.
(find_rank): Likewise.
(extract_array_notation_exprs): Likewise.
(replace_array_notations): Likewise.
(find_inv_trees): Likewise.
(replace_inv_trees): Likewise.
(contains_array_notation_expr): Likewise.
(find_correct_array_notation_type): Likewise.
* c-common.h (struct inv_list): Moved this struct from the file
c/c-array-notation.c and added a new field called additional tcodes.
(length_mismatch_in_expr_p): New prototype.
(is_cilkplus_reduce_builtin): Likewise.
(find_rank): Likewise.
(extract_array_notation_exprs): Likewise.
(replace_array_notation): Likewise.
(find_inv_trees): Likewise.
(replace_inv_trees): Likewise.
Andreas Krebbel [Fri, 7 Jun 2013 14:50:56 +0000 (14:50 +0000)]
s390.md (cpu_facility): Add cpu_zarch.
2013-06-07 Andreas Krebbel <Andreas.Krebbel@de.ibm.com>
* config/s390/s390.md (cpu_facility): Add cpu_zarch.
("*movmem_short", "*clrmem_short", "*cmpmem_short): Use cpu_zarch
for last alternative in the cpu_facility attribute.
* config/arm/constraints.md (Df): New constraint.
* config/arm/arm.md (iordi3_insn): Use Df constraint instead of De.
Correct length attribute for last two alternatives.
Alan Modra [Fri, 7 Jun 2013 04:56:46 +0000 (14:26 +0930)]
rs6000.c (rs6000_option_override_internal): Don't override user -mfp-in-toc.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Don't
override user -mfp-in-toc.
(offsettable_ok_by_alignment): Consider just the current access
rather than the whole object, unless BLKmode. Handle
CONSTANT_POOL_ADDRESS_P constants that lack a decl too.
(use_toc_relative_ref): Allow CONSTANT_POOL_ADDRESS_P constants
for -mcmodel=medium.
* config/rs6000/linux64.h (SUBSUBTARGET_OVERRIDE_OPTIONS): Don't
override user -mfp-in-toc or -msum-in-toc. Default to
-mno-fp-in-toc for -mcmodel=medium.
extend.texi (PowerPC AltiVec/VSX Built-in Functions): Document new power8 builtins.
[gcc]
2013-06-06 Michael Meissner <meissner@linux.vnet.ibm.com>
Pat Haugen <pthaugen@us.ibm.com>
Peter Bergner <bergner@vnet.ibm.com>
* doc/extend.texi (PowerPC AltiVec/VSX Built-in Functions):
Document new power8 builtins.
* config/rs6000/vector.md (and<mode>3): Add a clobber/scratch of a
condition code register, to allow 128-bit logical operations to be
done in the VSX or GPR registers.
(nor<mode>3): Use the canonical form for nor.
(eqv<mode>3): Add expanders for power8 xxleqv, xxlnand, xxlorc,
vclz*, and vpopcnt* vector instructions.
(nand<mode>3): Likewise.
(orc<mode>3): Likewise.
(clz<mode>2): LIkewise.
(popcount<mode>2): Likewise.
* config/rs6000/predicates.md (int_reg_operand): Rework tests so
that only the GPRs are recognized.
* config/rs6000/rs6000-c.c (altivec_overloaded_builtins): Add
support for new power8 builtins.
* config/rs6000/rs6000.c (rs6000_option_override_internal): Only
allow power8 quad mode in 64-bit.
(rs6000_builtin_vectorized_function): Add support to vectorize
ISA 2.07 count leading zeros, population count builtins.
(rs6000_expand_vector_init): On ISA 2.07 use xscvdpspn to form
V4SF vectors instead of xscvdpsp to avoid IEEE related traps.
(builtin_function_type): Add vgbbd builtin function which takes an
unsigned argument.
(altivec_expand_vec_perm_const): Add support for new power8 merge
instructions.
* config/rs6000/vsx.md (VSX_L2): New iterator for 128-bit types,
that does not include TImdoe for use with 32-bit.
(UNSPEC_VSX_CVSPDPN): Support for power8 xscvdpspn and xscvspdpn
instructions.
(UNSPEC_VSX_CVDPSPN): Likewise.
(vsx_xscvdpspn): Likewise.
(vsx_xscvspdpn): Likewise.
(vsx_xscvdpspn_scalar): Likewise.
(vsx_xscvspdpn_directmove): Likewise.
(vsx_and<mode>3): Split logical operations into 32-bit and
64-bit. Add support to do logical operations on TImode as well as
VSX vector types. Allow logical operations to be done in either
VSX registers or in general purpose registers in 64-bit mode. Add
splitters if GPRs were used. For AND, add clobber of CCmode to
allow use of ANDI on GPRs. Rewrite nor to use the canonical RTL
encoding.
(vsx_and<mode>3_32bit): Likewise.
(vsx_and<mode>3_64bit): Likewise.
(vsx_ior<mode>3): Likewise.
(vsx_ior<mode>3_32bit): Likewise.
(vsx_ior<mode>3_64bit): Likewise.
(vsx_xor<mode>3): Likewise.
(vsx_xor<mode>3_32bit): Likewise.
(vsx_xor<mode>3_64bit): Likewise.
(vsx_one_cmpl<mode>2): Likewise.
(vsx_one_cmpl<mode>2_32bit): Likewise.
(vsx_one_cmpl<mode>2_64bit): Likewise.
(vsx_nor<mode>3): Likewise.
(vsx_nor<mode>3_32bit): Likewise.
(vsx_nor<mode>3_64bit): Likewise.
(vsx_andc<mode>3): Likewise.
(vsx_andc<mode>3_32bit): Likewise.
(vsx_andc<mode>3_64bit): Likewise.
(vsx_eqv<mode>3_32bit): Add support for power8 xxleqv, xxlnand,
and xxlorc instructions.
(vsx_eqv<mode>3_64bit): Likewise.
(vsx_nand<mode>3_32bit): Likewise.
(vsx_nand<mode>3_64bit): Likewise.
(vsx_orc<mode>3_32bit): Likewise.
(vsx_orc<mode>3_64bit): Likewise.
* config/rs6000/altivec.md (UNSPEC_VGBBD): Add power8 vgbbd
instruction.
(p8_vmrgew): Add power8 vmrgew and vmrgow instructions.
(p8_vmrgow): Likewise.
(altivec_and<mode>3): Add clobber of CCmode to allow AND using
GPRs to be split under VSX.
(p8v_clz<mode>2): Add power8 count leading zero support.
(p8v_popcount<mode>2): Add power8 population count support.
(p8v_vgbbd): Add power8 gather bits by bytes by doubleword
support.
* config/rs6000/rs6000.md (eqv<mode>3): Add support for powerp eqv
instruction.
projects / thirdparty / gcc.git / log
