BALATON Zoltan [Thu, 23 Oct 2025 00:06:09 +0000 (02:06 +0200)]
hw/ppc/pegasos2: Change device tree generation
We generate a flattened device tree programmatically for VOF. Change
this to load the static parts from a device tree blob and only
generate the parts that depend on run time conditions such as CPU
type, memory size and PCI devices. Moving the static parts in a dts
makes the board code simpler and more generic.
BALATON Zoltan [Thu, 23 Oct 2025 00:06:07 +0000 (02:06 +0200)]
ppc/vof: Make nextprop behave more like Open Firmware
The FDT does not normally store name properties but reconstructs it
from path but Open Firmware specification says each node should at
least have this property. This is correctly handled in getprop but
nextprop should also return it even if not present as a property.
Explicit name properties are still allowed because they are needed
e.g. on the root node that guests expect to have specific names as
seen on real machines instead of being empty so sometimes the node
name may need to be overriden. For example on pegasos MorphOS checks
the name of "/" and expects to find bplan,Pegasos2 which is how it
identifies the machine.
The SpaprMachineClass::phb_placement callback was only used by
the pseries-4.0 machine, which got removed. Remove it as now
unused, directly calling spapr_phb_placement().
Move spapr_phb_placement() definition to avoid forward declaration.
pseries-4.0 had been deprecated and due for removal now as per policy.
Also remove pre-4.1 migration hacks which were introduced for backward
compatibility.
Suggested-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Cédric Le Goater <clg@redhat.com>
[PMD: Remove SpaprMachineClass::pre_4_1_migration field] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Link: https://lore.kernel.org/qemu-devel/20251021084346.73671-9-philmd@linaro.org Signed-off-by: Harsh Prateek Bora <harshpb@linux.ibm.com>
pseries-3.1 had been deprecated and due for removal now as per policy.
Also remove backward compatibility flags and related code introduced for
pre pseries-4.0 machines.
Merge tag 'pull-vfio-20251022' of https://github.com/legoater/qemu into staging
vfio queue:
* Fix CPR transfer
* Add support for VFIO_DMA_UNMAP_FLAG_ALL
* Fix vfio-user documentation
* Update Alex Williamson's email address
* Fix for vfio-region cache for the vGPU use case
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# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [full]
* tag 'pull-vfio-20251022' of https://github.com/legoater/qemu:
vfio: only check region info cache for initial regions
vfio: rename field to "num_initial_regions"
MAINTAINERS: Update Alex Williamson's email address
docs/system/devices/vfio-user: fix formatting
vfio/listener: Add an assertion for unmap_all
vfio/iommufd: Support unmap all in one ioctl()
vfio/container: Support unmap all in one ioctl()
accel/kvm: Fix an erroneous check on coalesced_mmio_ring
vfio/iommufd: Restore vbasedev's reference to hwpt after CPR transfer
vfio/iommufd: Set cpr.ioas_id on source side for CPR transfer
vfio/cpr-legacy: drop an erroneous assert
vfio/container: Remap only populated parts in a section
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'pull-aspeed-20251022' of https://github.com/legoater/qemu into staging
aspeed queue:
* Improve AST2700 co-processor models
* Add vbootrom support to the ast2700fc multi-soc machine
* Bump SDK version to v09.08 for the ast2700fc machine
* Add 32 bits property for Aspeed GPIOs
* Change ast2600-evb machine flash model to w25q512jv
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# gpg: Good signature from "Cédric Le Goater <clg@redhat.com>" [full]
# gpg: aka "Cédric Le Goater <clg@kaod.org>" [full]
* tag 'pull-aspeed-20251022' of https://github.com/legoater/qemu:
hw/arm/aspeed: Remove ast2700fc self-aliasing
hw/arm/aspeed: ast2600-evb: Use w25q512jv flash model
tests/qtest: Add qtest for for ASPEED GPIO gpio-set property
hw/gpio: Add property for ASPEED GPIO in 32 bits basis
tests/functional/aarch64/ast2700fc: Add vbootrom test
tests/functional/aarch64/ast2700fc: Move coprocessor image loading to common function
tests/functional/aarch64/ast2700fc: Add eth2 network interface check in PCIe test
tests/functional/aarch64/ast2700fc: Update test ASPEED SDK v09.08
hw/arm/aspeed_ast27x0-fc: Add VBOOTROM support
hw/arm/aspeed_ast27x0-fc: Map FMC0 flash contents into CA35 boot ROM
hw/arm/ast27x0: Share single UART set across PSP, SSP, and TSP
hw/arm/ast27x0: Share single SCU instance across PSP, SSP, and TSP
hw/arm/ast27x0: Add SRAM link and alias mapping for TSP coprocessor
hw/arm/ast27x0: Add SRAM link and alias mapping for SSP coprocessor
hw/arm/aspeed_ast27x0-tsp: Add SDRAM region and fix naming and size to 512MB
hw/arm/aspeed_ast27x0-ssp: Add SDRAM region and fix naming and size to 512MB
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Merge tag 'hw-misc-20251021' of https://github.com/philmd/qemu into staging
Misc HW patches
- Replace compile-time checks by runtime ones to build virtio-mem.c once
- Cleanups in Raven PCI host bridge, audio and PC devices
- Allow machine dynamic registration of valid CPU types
- Introduce DEFINE_MACHINE_WITH_INTERFACE[_ARRAY]() macros
- Set DDR2 minimum write recovery time in EEPROM SPD
- Have PPCe500 machines abort gracefully when using invalid CPU
- Prevent buffer overflow in openrisc_sim_init()
- Pass PCI domain to Xen xc_physdev_map_pirq_msi()
- Fix register API leaks
- Simplify Xilinx CANFD model
- Unconditionally create System I/O on PReP machine
- Update documentation around '-soundhw' command line option
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# gpg: Signature made Wed 22 Oct 2025 03:19:00 AM CDT
# gpg: using RSA key FAABE75E12917221DCFD6BB2E3E32C2CDEADC0DE
# gpg: Good signature from "Philippe Mathieu-Daudé (F4BUG) <f4bug@amsat.org>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: FAAB E75E 1291 7221 DCFD 6BB2 E3E3 2C2C DEAD C0DE
* tag 'hw-misc-20251021' of https://github.com/philmd/qemu: (45 commits)
docs: Update mentions of removed '-soundhw' command line option
docs: update -soundhw -> -device list
MAINTAINERS: Add missing machine name in the Alpha section
qemu/target-info: Include missing 'qapi-types-common.h' header
hw/ppc/spapr: Rename resize_hpt_err to errp
hw/audio: replace AUD_log() usage
hw/pcspk: check the "pit" is set
hw/pcspk: make 'pit' a class property
hw/pcspk: use explicitly the required PIT types
hw/audio: remove global pcspk
hw/audio: rename model list function
hw/audio: improve error reports
tests/qtest/ds1338: Reuse from_bcd()
hw/intc/apic: Pass APICCommonState to apic_register_{read,write}
hw/i386/apic: Ensure own APIC use in apic_msr_{read,write}
hw/i386/apic: Prefer APICCommonState over DeviceState
hw/ide/ide-internal: Move dma_buf_commit() into ide "namespace"
hw/rtc/mc146818rtc: Assert correct usage of mc146818rtc_set_cmos_data()
hw/rtc/mc146818rtc: Use ARRAY_SIZE macro
hw/rtc/mc146818rtc: Convert CMOS_DPRINTF() into trace events
...
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
Gerd Hoffmann [Fri, 17 Oct 2025 11:50:05 +0000 (13:50 +0200)]
hw/uefi/ovmf-log: add maxsize parameter
Allow limiting the amount of log output sent. Allow up to 1 MiB.
In case the guest log buffer is larger than 1 MiB limit the output
instead of throwing an error.
Acked-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-ID: <20251017115006.2696991-4-kraxel@redhat.com>
Gerd Hoffmann [Fri, 17 Oct 2025 11:50:03 +0000 (13:50 +0200)]
hw/uefi: add query-firmware-log monitor command
Starting with the edk2-stable202508 tag OVMF (and ArmVirt too) have
optional support for logging to a memory buffer. There is guest side
support -- for example in linux kernels v6.17+ -- to read that buffer.
But that might not helpful if your guest stops booting early enough that
guest tooling can not be used yet. So host side support to read that
log buffer is a useful thing to have.
This patch implements the query-firmware-log qmp monitor command to
read the firmware log.
Reviewed-by: Markus Armbruster <armbru@redhat.com> Signed-off-by: Gerd Hoffmann <kraxel@redhat.com>
Message-ID: <20251017115006.2696991-2-kraxel@redhat.com>
docs: Update mentions of removed '-soundhw' command line option
The `-soundhw` CLI was removed in commit 039a68373c4 ("introduce
-audio as a replacement for -soundhw"). Remove outdated comments
and update the document mentioning the old usage.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Marc-André Lureau <marcandre.lureau@redhat.com>
Message-Id: <20251021131825.99390-2-philmd@linaro.org>
Thomas Huth [Mon, 20 Oct 2025 14:04:24 +0000 (16:04 +0200)]
MAINTAINERS: Add missing machine name in the Alpha section
Without a machine name here, get_maintainers.pl uses the "-----..."
separator for describing what the maintainer is taking care of:
$ scripts/get_maintainer.pl -f hw/alpha/dp264.c
Richard Henderson <richard.henderson@linaro.org> (maintainer:--------------)
qemu-devel@nongnu.org (open list:All patches CC here)
Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251020140425.45003-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
qemu/target-info: Include missing 'qapi-types-common.h' header
When adding the TargetInfo::@endianness field in commit a37aec2e7d8,
we neglected to include the "qapi-types-common.h" header to get the
EndianMode enum definition. Fix that.
We don't let the user create a "isa-pcspk" via -device yet (in theory,
we could, and fallback on a lookup PIT), but we can add some safety
checks that the property was correctly set nonetheless.
Signed-off-by: Marc-André Lureau <marcandre.lureau@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251021090317.425409-7-marcandre.lureau@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Cédric Le Goater [Thu, 16 Oct 2025 21:24:37 +0000 (23:24 +0200)]
hw/arm/aspeed: ast2600-evb: Use w25q512jv flash model
The ast2600-evb machine model is using the "mx66u51235f" flash model,
which has issues with recent Linux kernels (6.15+) when reading SFDP
data.
Change the flash model to "w25q512jv", which is the model present on
some ast2600a3 EVB board and is known to work correctly with recent
kernels. Adjust the corresponding qtest to reflect the new JEDEC ID of
the w25q512jv flash.
Felix Wu [Wed, 15 Oct 2025 01:18:25 +0000 (01:18 +0000)]
hw/gpio: Add property for ASPEED GPIO in 32 bits basis
Added 32 bits property for ASPEED GPIO. Previously it can only be
access in bitwise manner.
The changes to qobject is to index gpios with array indices on top of
accessing with registers. This allows for easier gpio access,
especially in tests with complex behaviors that requires large number
of gpios at a time, like fault injection and networking behaviors.
Indexing multiple gpios at once allows qmp/side band client to no
longer hardcode and populate register names and manipulate them
faster.
Jamin Lin [Wed, 15 Oct 2025 06:22:05 +0000 (14:22 +0800)]
tests/functional/aarch64/ast2700fc: Add eth2 network interface check in PCIe test
Enhance the AST2700 functional PCIe test to verify the network interface
configuration for eth2. This adds an additional command to check the IP
address assignment on eth2 to ensure network functionality is correctly
initialized in the test environment.
Jamin Lin [Wed, 15 Oct 2025 06:22:02 +0000 (14:22 +0800)]
hw/arm/aspeed_ast27x0-fc: Map FMC0 flash contents into CA35 boot ROM
This patch introduces a dedicated ca35_boot_rom memory region and
copies the FMC0 flash data into it.
The motivation is to support the upcoming vbootrom. The vbootrom
replaces the existing BOOTMCU (RISC-V 32 SPL) flow, which currently reads
the "image-bmc" from FMC_CS0 and loads the following components
into DRAM:
- Trusted Firmware-A
- OP-TEE OS
- u-boot-nodtb.bin
- u-boot.dtb
After loading, BOOTMCU releases the CA35 reset so that CA35 can start
executing Trusted Firmware-A.
The vbootrom follows the same sequence: CA35 fetches "image-bmc" from FMC0
flash at the SPI boot ROM base address (0x100000000), parses the FIT image,
loads each component into its designated DRAM location, and then jumps to
Trusted Firmware-A.
Jamin Lin [Wed, 15 Oct 2025 06:22:01 +0000 (14:22 +0800)]
hw/arm/ast27x0: Share single UART set across PSP, SSP, and TSP
In the original model, each subsystem (PSP, SSP, and TSP) created its own
set of 13 UART devices, resulting in a total of 39 UART instances. However,
on real AST2700 hardware, there is only one set of 13 UARTs shared among
all processors.
This commit reworks the UART handling to correctly model the shared
hardware design. The PSP now creates the full set of 13 UART instances,
while the SSP and TSP link to the corresponding shared UART device
through object properties.
Changes include:
- Add "DEFINE_PROP_LINK("uart", ...)" and "DEFINE_PROP_INT32("uart-dev", ...)"
to allow each coprocessor to reference a specific shared UART instance.
- Modify SSP to link to PSP’s UART4, and TSP to link to PSP’s UART7.
- Introduce "uart_alias" to remap the UART’s MMIO region into the coprocessor’s
memory space.
- Redirect the UART interrupt to the coprocessor’s NVIC, replacing the
default routing to the PSP’s GIC.
With this change, only one set of 13 UART devices is instantiated by the PSP,
while the SSP and TSP reuse them via aliasing and shared interrupt routing,
matching the real AST2700 hardware behavior.
Jamin Lin [Wed, 15 Oct 2025 06:22:00 +0000 (14:22 +0800)]
hw/arm/ast27x0: Share single SCU instance across PSP, SSP, and TSP
AST2700 has a single SCU hardware block, memory-mapped at
0x12C02000–0x12C03FFF from the perspective of the main CA35 processor (PSP).
The SSP and TSP coprocessors access this same SCU block at different
addresses: 0x72C02000–0x72C03FFF.
Previously, each subsystem (PSP, SSP, and TSP) instantiated its own SCU
device, resulting in three independent SCU instances in the QEMU model.
In real hardware, however, only a single SCU exists and is shared among
all processors.
This commit reworks the SCU model to correctly reflect the hardware
behavior by allowing SSP and TSP to reference the PSP’s SCU instance.
The following changes are introduced:
- Add a scu property to AspeedCoprocessorState for linking the
coprocessor to the PSP’s SCU instance.
- Replace per-coprocessor SCU instantiation with a shared SCU link.
- Add "MemoryRegion scu_alias" to model address remapping for SSP and TSP.
- Create SCU alias regions in both SSP and TSP coprocessors and map
them at 0x72C02000 to mirror the PSP’s SCU registers.
- Ensure the SCU device in PSP is realized before SSP/TSP alias setup.
With this change, PSP, SSP, and TSP now share a consistent SCU state,
matching the single-SCU hardware design of AST2700.
Jamin Lin [Wed, 15 Oct 2025 06:21:59 +0000 (14:21 +0800)]
hw/arm/ast27x0: Add SRAM link and alias mapping for TSP coprocessor
AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for
the PSP (CA35) processor. The TSP coprocessor shares this same SRAM but
accesses it through a different address window at 0x70000000–0x7001FFFF.
To model this shared-memory behavior in QEMU, this commit introduces a
linked SRAM property and alias mapping between the PSP and TSP subsystems.
Changes include:
- Add the SRAM alias mapping at 0x70000000 in aspeed_ast27x0-tsp.c.
- In aspeed_ast27x0-fc.c, connect the TSP coprocessor’s "sram" link to
the PSP’s SRAM region.
- Ensure the alias region is initialized during TSP SoC realization so
the TSP can correctly access shared SRAM through its own address space.
This ensures that the TSP and PSP share the same physical SRAM backing.
Jamin Lin [Wed, 15 Oct 2025 06:21:58 +0000 (14:21 +0800)]
hw/arm/ast27x0: Add SRAM link and alias mapping for SSP coprocessor
AST2700 has a 128KB SRAM, physically mapped at 0x10000000–0x1001FFFF for
the PSP (CA35) processor. The SSP coprocessor shares this same SRAM but
accesses it through a different address window at 0x70000000–0x7001FFFF.
To model this shared-memory behavior in QEMU, this commit introduces a
linked SRAM property and alias mapping between the PSP and SSP subsystems.
Changes include:
- Add a "MemoryRegion *sram" link and "MemoryRegion sram_alias" to
AspeedCoprocessorState.
- Register the new "sram" property in aspeed_coprocessor_common.c.
- In aspeed_ast27x0-fc.c, connect the SSP coprocessor’s "sram" link to
the PSP’s SRAM region.
- In aspeed_ast27x0-ssp.c, create an alias mapping for SRAM at
0x70000000 – 0x7001FFFF in the SSP’s memory map.
This ensures that the SSP can correctly access the shared SRAM contents
through its own address space while maintaining a consistent physical
backing region. It also guarantees that the SRAM is realized before the
SSP device, ensuring successful alias setup.
Jamin Lin [Wed, 15 Oct 2025 06:21:57 +0000 (14:21 +0800)]
hw/arm/aspeed_ast27x0-tsp: Add SDRAM region and fix naming and size to 512MB
Previously, the TSP memory was incorrectly modeled as "SRAM" with
a 32 MB size. Rename from SRAM to SDRAM and correct size from 32MB
to 512MB to match hardware.
Jamin Lin [Wed, 15 Oct 2025 06:21:56 +0000 (14:21 +0800)]
hw/arm/aspeed_ast27x0-ssp: Add SDRAM region and fix naming and size to 512MB
Previously, the SSP memory was incorrectly modeled as "SRAM" with
a 32 MB size. This change introduces a new sdram field in
AspeedCoprocessorState and updates the realization logic accordingly.
Rename from SRAM to SDRAM and correct size from 32MB to 512MB to match
hardware.
John Levon [Tue, 14 Oct 2025 15:12:27 +0000 (17:12 +0200)]
vfio: only check region info cache for initial regions
It is semantically valid for a VFIO device to increase the number of
regions after initialization. In this case, we'd attempt to check for
cached region info past the size of the ->reginfo array. Check for the
region index and skip the cache in these cases.
This also works around some VGPU use cases which appear to be a bug,
where VFIO_DEVICE_QUERY_GFX_PLANE returns a region index beyond the
reported ->num_regions.
Fixes: 95cdb024 ("vfio: add region info cache") Signed-off-by: John Levon <john.levon@nutanix.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Alex Williamson <alex@shazbot.org> Link: https://lore.kernel.org/qemu-devel/20251014151227.2298892-3-john.levon@nutanix.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
John Levon [Tue, 14 Oct 2025 15:12:26 +0000 (17:12 +0200)]
vfio: rename field to "num_initial_regions"
We set VFIODevice::num_regions at initialization time, and do not
otherwise refresh it. As it is valid in theory for a VFIO device to
later increase the number of supported regions, rename the field to
"num_initial_regions" to better reflect its semantics.
Zhenzhong Duan [Thu, 9 Oct 2025 04:01:34 +0000 (00:01 -0400)]
vfio/listener: Add an assertion for unmap_all
Currently the maximum of iommu address space is 64bit. So when a maximum
iommu memory section is deleted, it's in scope [0, 2^64). Add a
assertion for that.
Zhenzhong Duan [Thu, 9 Oct 2025 04:01:33 +0000 (00:01 -0400)]
vfio/iommufd: Support unmap all in one ioctl()
IOMMUFD kernel uAPI supports unmapping whole address space in one call with
[iova, size] set to [0, UINT64_MAX], this can simplify iommufd_cdev_unmap()
a bit. See iommufd_ioas_unmap() in kernel for details.
Zhenzhong Duan [Thu, 9 Oct 2025 04:01:32 +0000 (00:01 -0400)]
vfio/container: Support unmap all in one ioctl()
VFIO type1 kernel uAPI supports unmapping whole address space in one call
since commit c19650995374 ("vfio/type1: implement unmap all"). Use the
unmap_all variant whenever it's supported in kernel.
Opportunistically pass VFIOLegacyContainer pointer in low level function
vfio_legacy_dma_unmap_one().
Co-developed-by: John Levon <levon@movementarian.org> Signed-off-by: John Levon <levon@movementarian.org> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Link: https://lore.kernel.org/qemu-devel/20251009040134.334251-2-zhenzhong.duan@intel.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
accel/kvm: Fix an erroneous check on coalesced_mmio_ring
According to KVM uAPI, coalesced mmio page is KVM_COALESCED_MMIO_PAGE_OFFSET
offset from kvm_run pages. For x86 it's 2 pages offset, for arm it's 1 page
offset currently. We shouldn't presume it's hardcoded 1 page or else
coalesced_mmio_ring will not be cleared in do_kvm_destroy_vcpu() in x86.
Fixes: 7ed0919119b0 ("migration: close kvm after cpr") Cc: Markus Armbruster <armbru@redhat.com> Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Steve Sistare <steven.sistare@oracle.com> Link: https://lore.kernel.org/qemu-devel/20250928085432.40107-6-zhenzhong.duan@intel.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
vfio/iommufd: Restore vbasedev's reference to hwpt after CPR transfer
After CPR transfer, if there are more than one VFIO devices, device is
not added to hwpt->device_list and its reference to hwpt isn't restored
on destination. We still need to call iommufd_cdev_attach_container() to
restore it after a matching container is found, or else SIGSEV triggers.
vfio/iommufd: Set cpr.ioas_id on source side for CPR transfer
On source side, if there are more than one VFIO devices and they
attach to same container, only the first device sets cpr.ioas_id,
the others are bypassed. We should set it for each device, or
else only first device works.
vfio_legacy_cpr_dma_map() is not only used in post_load on destination
but also error recovery path on source side. Assert it for destination
is wrong.
vfio/container: Remap only populated parts in a section
If there are multiple containers and unmap-all fails for some of them, we
need to remap vaddr for the other containers for which unmap-all succeeded.
When ram discard is enabled, we should only remap populated parts in a
section instead of the whole section.
Fixes: eba1f657cbb1 ("vfio/container: recover from unmap-all-vaddr failure") Signed-off-by: Zhenzhong Duan <zhenzhong.duan@intel.com> Reviewed-by: Steven Sistare <steven.sistare@oracle.com> Reviewed-by: David Hildenbrand <david@redhat.com> Link: https://lore.kernel.org/qemu-devel/20250928085432.40107-2-zhenzhong.duan@intel.com Signed-off-by: Cédric Le Goater <clg@redhat.com>
Bernhard Beschow [Sun, 19 Oct 2025 21:03:02 +0000 (23:03 +0200)]
hw/intc/apic: Pass APICCommonState to apic_register_{read,write}
As per the previous patch, the APIC instance is already available in
apic_msr_{read,write}, so it can be passed along. It turns out that
the call to cpu_get_current_apic() is only required in
apic_mem_{read,write}, so it has been moved there. Longer term,
cpu_get_current_apic() could be removed entirely if
apic_mem_{read,write} is tied to a CPU's local address space.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-10-shentey@gmail.com>
[PMD: Move return after apic_send_msi() in apic_mem_write()] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sun, 19 Oct 2025 21:03:01 +0000 (23:03 +0200)]
hw/i386/apic: Ensure own APIC use in apic_msr_{read,write}
Avoids the `current_cpu` global and seems more robust by not "forgetting" the
own APIC and then re-determining it by cpu_get_current_apic() which uses the
global.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-9-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sun, 19 Oct 2025 21:03:00 +0000 (23:03 +0200)]
hw/i386/apic: Prefer APICCommonState over DeviceState
Makes the APIC API more type-safe by resolving quite a few APIC_COMMON
downcasts.
Like PICCommonState, the APICCommonState is now a public typedef while staying
an abstract datatype.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-8-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sun, 19 Oct 2025 21:02:59 +0000 (23:02 +0200)]
hw/ide/ide-internal: Move dma_buf_commit() into ide "namespace"
The identifier suggests that it is a generic DMA function while it is tied
to IDE. Fix this by adding an "ide_" prefix.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-7-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sun, 19 Oct 2025 21:02:58 +0000 (23:02 +0200)]
hw/rtc/mc146818rtc: Assert correct usage of mc146818rtc_set_cmos_data()
The offset is never controlled by the guest, so any misuse constitutes a
programming error and shouldn't be silently ignored. Fix this by using assert().
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-6-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sun, 19 Oct 2025 21:02:57 +0000 (23:02 +0200)]
hw/rtc/mc146818rtc: Use ARRAY_SIZE macro
Avoids the error-prone repetition of the array size.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-5-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sun, 19 Oct 2025 21:02:56 +0000 (23:02 +0200)]
hw/rtc/mc146818rtc: Convert CMOS_DPRINTF() into trace events
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-4-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sun, 19 Oct 2025 21:02:55 +0000 (23:02 +0200)]
hw/audio/pcspk: Add I/O trace events
Allows to see how the guest interacts with the device.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-3-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Bernhard Beschow [Sun, 19 Oct 2025 21:02:54 +0000 (23:02 +0200)]
hw/timer/i8254: Add I/O trace events
Allows to see how the guest interacts with the device.
Signed-off-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20251019210303.104718-2-shentey@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
BALATON Zoltan [Sat, 18 Oct 2025 14:04:59 +0000 (16:04 +0200)]
hw/ppc/prep: Always create prep-systemio
The prep-systemio device models the system control ports of the 40p
machine which is not an optional pluggable device but part of the
system so it should not be disabled by -nodefaults but always created.
Additionally remove some line breaks to make lines related to one
device appear in one block for logical separation from other devices.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <b5b0150b6c579b10682f6482e7832cf381ffb759.1760795082.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Luc Michel [Fri, 17 Oct 2025 16:18:05 +0000 (18:18 +0200)]
hw/net/can/xlnx-versal-canfd: remove register API usage for banked regs
Now that we have a simple decoding logic for all the banked registers,
remove the register API usage for them. This restricts the register API
usage to only the base registers (from 0x0 to 0xec).
This also removes all the custom code that was creating register
descriptors for the register API and was leading to memory leaks when
the device was finalized.
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Luc Michel <luc.michel@amd.com>
Message-ID: <20251017161809.235740-7-luc.michel@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Luc Michel [Fri, 17 Oct 2025 16:18:04 +0000 (18:18 +0200)]
hw/net/can/xlnx-versal-canfd: refactor the banked registers logic
The CANFD device has several groups of registers:
- the main control registers from 0x0 to 0xec
- several banks of multiple registers. The number of banks is either
hardcoded, or configurable using QOM properties:
- Tx registers
- Filter registers
- Tx events registers
- Rx0 registers
- Rx1 registers
As of now, all the registers are handled using the register API. The
banked register logic results in a convoluted code to correctly allocate
the register descriptors for the register API. This code bypasses the
standard register API creation function (register_init_block). The
resulting code leaks memory when the device is finalized.
This commit introduces decoding logic for the banked registers. Those
registers are quite simple in practice. Accessing them triggers no
side-effect (only the filter registers need a check to catch guest
invalid behaviour). Starting from the Tx events registers, they are all
read-only.
The main device memory region is changed to an I/O one, calling the
new decoding logic when accessed. The register API memory region still
overlaps all of it so for now the introduced code has no effect. The
next commit will remove the register API usage for banked registers.
Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Luc Michel <luc.michel@amd.com>
Message-ID: <20251017161809.235740-6-luc.michel@amd.com>
[PMD: Have canfd_decode_reg_bank() take optional @idx, types fixups] Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Luc Michel [Fri, 17 Oct 2025 16:18:03 +0000 (18:18 +0200)]
hw/core/register: remove the `register_finalize_block' function
This function is now unused. Drop it.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Luc Michel <luc.michel@amd.com>
Message-ID: <20251017161809.235740-5-luc.michel@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Luc Michel [Fri, 17 Oct 2025 16:18:02 +0000 (18:18 +0200)]
hw/core/register: remove the calls to `register_finalize_block'
This function is now a no-op. The register array is parented to the
device and get finalized when the device is.
Drop all the calls to `register_finalize_block'. Drop the
RegisterInfoArray reference when it is not used elsewhere in the device.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Luc Michel <luc.michel@amd.com>
Message-ID: <20251017161809.235740-4-luc.michel@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Luc Michel [Fri, 17 Oct 2025 16:18:01 +0000 (18:18 +0200)]
hw/core/register: add the REGISTER_ARRAY type
Introduce the REGISTER_ARRAY QOM type. This type reuses the existing
RegisterInfoArray struct. When `register_init_block' is called, it creates
a REGISTER_ARRAY object and parents it to the calling device. This way
it gets finalized when the device is. The memory region is parented to
the REGISTER_ARRAY object to ensure correct finalizing order.
The finalize function of the REGISTER_ARRAY type performs the necessary
cleaning that used to be done by `register_finalize_block'. The latter
is left empty and will be removed when all the register API users have
been refactored.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Luc Michel <luc.michel@amd.com>
Message-ID: <20251017161809.235740-3-luc.michel@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Luc Michel [Fri, 17 Oct 2025 16:18:00 +0000 (18:18 +0200)]
hw/core/register: remove the REGISTER device type
The REGISTER class (RegisterInfo struct) is currently a QOM type
inheriting from DEVICE. This class has no real purpose:
- the qdev API is not used,
- according to the comment preceding it, the object_initialize call
is here to zero-initialize the struct. However all the effective
struct attributes are then initialized explicitly.
- the object is never parented.
This commits drops the REGISTER QOM type completely, leaving the
RegisterInfo struct as a bare C struct.
The register_register_types function is left empty here because it is
reused in the next commit.
Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Reviewed-by: Francisco Iglesias <francisco.iglesias@amd.com> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com> Signed-off-by: Luc Michel <luc.michel@amd.com>
Message-ID: <20251017161809.235740-2-luc.michel@amd.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Roger Pau Monne [Fri, 17 Oct 2025 15:51:36 +0000 (17:51 +0200)]
hw/xen: pass PCI domain to xc_physdev_map_pirq_msi()
It's currently impossible for passthrough devices on segment different
than 0 to work correctly, as the PCI domain is not provided to
xc_physdev_map_pirq_msi(), and hence it's unconditionally assumed that
all devices are on segment 0.
Adjust the call to xc_physdev_map_pirq_msi() to pass the PCI domain in
the high 16bits of the bus parameter. On versions of Xen where this
is not supported the passed segment will be ignored and assume to be 0,
no worse than the current state.
Signed-off-by: Roger Pau Monné <roger.pau@citrix.com> Reviewed-by: Frediano Ziglio <freddy77@gmail.com> Reviewed-by: Anthony PERARD <anthony.perard@vates.tech> Reviewed-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Message-ID: <20251017155136.16540-1-roger.pau@citrix.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Resolves this build breakage (which is actually a false-positive)
../hw/openrisc/openrisc_sim.c: In function ‘openrisc_sim_init’:
../hw/openrisc/openrisc_sim.c:284:45: error: ‘__builtin___snprintf_chk’ output may be truncated before the last format character [-Werror=format-truncation=]
snprintf(alias, sizeof(alias), "serial%d", uart_idx);
^
In file included from /usr/include/stdio.h:964:0,
from /data/qemu/include/qemu/osdep.h:114,
from ../hw/openrisc/openrisc_sim.c:21:
/usr/include/bits/stdio2.h:54:10: note: ‘__builtin___snprintf_chk’ output between 8 and 9 bytes into a destination of size 8
return __builtin___snprintf_chk (__s, __n, __USE_FORTIFY_LEVEL - 1,
^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
__glibc_objsize (__s), __fmt,
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
__va_arg_pack ());
~~~~~~~~~~~~~~~~~
by using a modern, more robust allocation pattern.
Suggested-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Message-ID: <298bd904-1ee9-439e-8220-7a24e0952861@siemens.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Thomas Huth [Wed, 15 Oct 2025 11:12:43 +0000 (13:12 +0200)]
hw/ppc/e500: Check for compatible CPU type instead of aborting ungracefully
When using the ppce500 machine with an embedded CPU type that has
the right MMU model, but is not part of the e500 CPU family, QEMU
currently aborts ungracefully:
The ppce500 machine expects a CPU with certain GPIO interrupt pins,
so let's replace the coarse check for the MMU_BOOKE206 model with
a more precise check that only allows CPUs from the e500 family.
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3162 Signed-off-by: Thomas Huth <thuth@redhat.com> Acked-by: Bernhard Beschow <shentey@gmail.com> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20251015111243.1585018-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
BALATON Zoltan [Thu, 1 May 2025 23:20:33 +0000 (01:20 +0200)]
hw/boards: Extend DEFINE_MACHINE macro to cover more use cases
Add a more general DEFINE_MACHINE_EXTENDED macro and define simpler
versions with less parameters based on that. This is inspired by how
the OBJECT_DEFINE macros do this in a similar way to allow using the
shortened definition in more complex cases too.
hw/core/machine: Allow dynamic registration of valid CPU types
Add MachineClass::get_valid_cpu_types(), a helper that
returns a dynamic list of CPU types. Since the helper
takes a MachineState argument, we know the machine is
created by the time we call it.
hw/core: Filter machine list available for a particular target binary
Binaries can register a QOM type to filter their machines
by filling their TargetInfo::machine_typename field.
Commit 28502121be7 ("system/vl: Filter machine list available
for a particular target binary") added the filter to
machine_help_func() but missed the other places where the machine
list must be filtered, such QMP 'query-machines' command used by
QTests, and select_machine(). Fix that.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
Message-Id: <20251020220941.65269-2-philmd@linaro.org>
hw/pci-host/raven: Use correct parameter in direct access ops
Instead of passing unneeded enclosing objects to the config direct
access ops that only need the bus we can pass that directly thus
simplifying the functions.
Signed-off-by: BALATON Zoltan <balaton@eik.bme.hu> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <226e0756661e72a03ba363887730112a58acde85.1760795082.git.balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Remove unused "system/ram_addr.h" header. This file doesn't
use any target specific definitions anymore, compile it once
by moving it to system_virtio_ss[].
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: David Hildenbrand <david@redhat.com> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20250502214551.80401-6-philmd@linaro.org>
hw/virtio/virtio-mem: Convert VIRTIO_MEM_HAS_LEGACY_GUESTS to runtime
Check legacy guests support at runtime: instead of evaluating
the VIRTIO_MEM_HAS_LEGACY_GUESTS definition at compile time,
call target_arch() to detect which target is being run at runtime.
Register virtio_mem_legacy_guests_properties[] at runtime.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20250502214551.80401-5-philmd@linaro.org>
hw/virtio/virtio-mem: Convert VIRTIO_MEM_USABLE_EXTENT to runtime
Use target_arch() to check at runtime which target architecture
is being run.
Note, since TARGET_ARM is defined for TARGET_AARCH64, we
check for both ARM & AARCH64 enum values.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org> Acked-by: David Hildenbrand <david@redhat.com> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20250502214551.80401-4-philmd@linaro.org>
Merge tag 'pull-request-2025-10-21' of https://gitlab.com/thuth/qemu into staging
- Add a missing QAPI event + functional test for the CPI feature on s390x
- Remove the obsolete s390-ccw-virtio-4.2 machine type
- 2nd try to fix the slow cache up/download in the MSYS2 CI job
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# 5rkFTIUEkNIWhS92XNyy165tvXw2cz66J3ud/A006p0OzO3Kow3863TNAQI/wFNR
# xDGFNjzNp/8YpXMfsgQZ3oB7iEpK5zliosd61sxqGUcd33w8kMHaKeWwly2Mroy2
# eS1dHAHdSrg=
# =pnHC
# -----END PGP SIGNATURE-----
# gpg: Signature made Tue 21 Oct 2025 08:54:17 AM CDT
# gpg: using RSA key 27B88847EEE0250118F3EAB92ED9D774FE702DB5
# gpg: issuer "thuth@redhat.com"
# gpg: Good signature from "Thomas Huth <th.huth@gmx.de>" [unknown]
# gpg: aka "Thomas Huth <thuth@redhat.com>" [unknown]
# gpg: aka "Thomas Huth <th.huth@posteo.de>" [unknown]
# gpg: aka "Thomas Huth <huth@tuxfamily.org>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 27B8 8847 EEE0 2501 18F3 EAB9 2ED9 D774 FE70 2DB5
* tag 'pull-request-2025-10-21' of https://gitlab.com/thuth/qemu:
gitlab-ci: Decrease the size of the compiler cache
hw/core/machine: Remove MachineClass::fixup_ram_size callback
hw/s390x/ccw: Remove SCLPDevice::increment_size field
hw/s390x/ccw: Remove deprecated s390-ccw-virtio-4.2 machine
tests/functional: add tests for SCLP event CPI
qapi/machine-s390x: add QAPI event SCLP_CPI_INFO_AVAILABLE
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
projects / thirdparty / qemu.git / log
