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7 weeks agoclk: qcom: Constify qcom_cc_driver_data
Krzysztof Kozlowski [Tue, 31 Mar 2026 09:17:22 +0000 (11:17 +0200)] 
clk: qcom: Constify qcom_cc_driver_data

The static 'struct qcom_cc_driver_data' contains probe match-like data
and is not modified: neither by the driver defining it nor by common.c
code using it.

Make it const for code safety and code readability.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331091721.61613-3-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
7 weeks agoclk: qcom: videocc-glymur: Constify qcom_cc_desc
Krzysztof Kozlowski [Tue, 31 Mar 2026 08:55:22 +0000 (10:55 +0200)] 
clk: qcom: videocc-glymur: Constify qcom_cc_desc

Static 'struct qcom_cc_desc' is not modified by drivers and can be made
const for code safety.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260331085521.37337-2-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: Add a driver for SM8750 GPU clocks
Konrad Dybcio [Thu, 5 Mar 2026 10:40:09 +0000 (16:10 +0530)] 
clk: qcom: Add a driver for SM8750 GPU clocks

Support the graphics clock controller for SM8750 for Graphics SW
driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a
block dedicated to managing clocks for the GPU subsystem on GX power
domain. The GX clock controller driver manages only the GX GDSC and the
rest of the resources of the controller are managed by the firmware.

Update the compatible for Graphics GX Clock Controller for SM8750 as the
GX clock controller is a reuse of the Kaanapali driver.

Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-2-78292b40b053@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: clock: qcom: Add SM8750 GPU clocks
Konrad Dybcio [Thu, 5 Mar 2026 10:40:08 +0000 (16:10 +0530)] 
dt-bindings: clock: qcom: Add SM8750 GPU clocks

The SM8750 features a "traditional" GPU_CC block, much of which is
controlled through the GMU microcontroller. GPU_CC block requires the MX
and CX rail control and thus add the corresponding power-domains and
require-opps. Additionally, there's an separate GX_CC block, where
the GX GDSC is moved.

Update the bindings to accommodate for SM8750 SoC.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260305-gpucc_sm8750_v2-v5-1-78292b40b053@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support
John Crispin [Wed, 11 Mar 2026 18:39:41 +0000 (19:39 +0100)] 
clk: qcom: ipq-cmn-pll: Add IPQ8074 SoC support

The CMN PLL in IPQ8074 SoC supplies fixed clocks to the networking
subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at
416.5 MHz.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20260311183942.10134-5-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: clock: qcom: Add CMN PLL support for IPQ8074
John Crispin [Wed, 11 Mar 2026 18:39:40 +0000 (19:39 +0100)] 
dt-bindings: clock: qcom: Add CMN PLL support for IPQ8074

The CMN PLL block in the IPQ8074 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.

Add the related compatible for IPQ8074 to the ipq9574-cmn-pll
generic schema.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-4-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support
John Crispin [Wed, 11 Mar 2026 18:39:39 +0000 (19:39 +0100)] 
clk: qcom: ipq-cmn-pll: Add IPQ6018 SoC support

The CMN PLL in IPQ6018 SoC supplies fixed clocks to the networking
subsystem: bias_pll_cc_clk at 300 MHz and bias_pll_nss_noc_clk at
416.5 MHz.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Link: https://lore.kernel.org/r/20260311183942.10134-3-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: clock: qcom: Add CMN PLL support for IPQ6018
John Crispin [Wed, 11 Mar 2026 18:39:38 +0000 (19:39 +0100)] 
dt-bindings: clock: qcom: Add CMN PLL support for IPQ6018

The CMN PLL block in the IPQ6018 SoC takes 48 MHz as the reference
input clock. Its output clocks are the bias_pll_cc_clk (300 MHz) and
bias_pll_nss_noc_clk (416.5 MHz) clocks used by the networking
subsystem.

Add the related compatible for IPQ6018 to the ipq9574-cmn-pll
generic schema.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311183942.10134-2-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agoclk: qcom: gdsc: Fix error path on registration of multiple pm subdomains
Vladimir Zapolskiy [Sat, 28 Mar 2026 01:26:19 +0000 (03:26 +0200)] 
clk: qcom: gdsc: Fix error path on registration of multiple pm subdomains

Some pm subdomains may be left in added to a parent domain state, if
gdsc_add_subdomain_list() function fails in the middle and bails from
a GDSC power domain controller registration out.

Fixes: b489235b4dc0 ("clk: qcom: Support attaching GDSCs to multiple parents")
Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Bryan O'Donoghue <bod@kernel.org>
Link: https://lore.kernel.org/r/20260328012619.832770-1-vladimir.zapolskiy@linaro.org
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
8 weeks agodt-bindings: clock: qcom: Add missing power-domains property
Abel Vesa [Fri, 27 Mar 2026 12:13:40 +0000 (14:13 +0200)] 
dt-bindings: clock: qcom: Add missing power-domains property

In order for the GCC votes on the GDSCs it provides to be propagated
to CX, CX needs to be declared as power domain of the GCC.

Document the missing power-domains property to that purpose.

Fixes: 95ba6820a665 ("dt-bindings: clock: qcom: document the Milos Global Clock Controller")
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260327-dt-fix-milos-eliza-gcc-power-domains-v1-1-f14a22c73fe9@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock
Abel Vesa [Mon, 23 Mar 2026 18:57:12 +0000 (20:57 +0200)] 
clk: qcom: gcc-eliza: Enable FORCE_MEM_CORE_ON for UFS AXI PHY clock

According to internal documentation, the UFS AXI PHY clock requires
FORCE_MEM_CORE_ON to be enabled for UFS MCQ mode to work. Without this,
the UFS controller fails when operating in MCQ mode, which is already
enabled in the device tree.

The UFS PHY ICE core clock already has this bit set, so apply the same
configuration to the UFS PHY AXI clock.

Fixes: 3d356ab4a1ec ("clk: qcom: Add support for Global clock controller on Eliza")
Reported-by: Nitin Rawat <nitin.rawat@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260323-eliza-gcc-set-ufs-axi-phyforce-mem-core-on-v1-1-b6b7a6f3f8c5@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-sc7180: Add missing MDSS resets
Konrad Dybcio [Tue, 20 Jan 2026 11:19:26 +0000 (12:19 +0100)] 
clk: qcom: dispcc-sc7180: Add missing MDSS resets

The MDSS resets have so far been left undescribed. Fix that.

Fixes: dd3d06622138 ("clk: qcom: Add display clock controller driver for SC7180")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Tested-by: Val Packett <val@packett.cool> # sc7180-ecs-liva-qc710
Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-2-0b1b442156c3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoMerge branch '20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com'...
Bjorn Andersson [Tue, 24 Mar 2026 03:16:44 +0000 (22:16 -0500)] 
Merge branch '20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com' into clk-for-7.1

Merge the addition of reset constants to the SC7180 display clock
controller through a topic branch, in order to make them available to
the DeviceTree branch as well.

2 months agodt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets
Konrad Dybcio [Tue, 20 Jan 2026 11:19:25 +0000 (12:19 +0100)] 
dt-bindings: clock: qcom,dispcc-sc7180: Define MDSS resets

The MDSS resets have so far been left undescribed. Fix that.

Fixes: 75616da71291 ("dt-bindings: clock: Introduce QCOM sc7180 display clock bindings")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Tested-by: Val Packett <val@packett.cool> # sc7180-ecs-liva-qc710
Link: https://lore.kernel.org/r/20260120-topic-7180_dispcc_bcr-v1-1-0b1b442156c3@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: rcg2: expand frac table for mdss_pixel_clk_src
Pengyu Luo [Sat, 21 Mar 2026 09:50:28 +0000 (17:50 +0800)] 
clk: qcom: rcg2: expand frac table for mdss_pixel_clk_src

Recently, when testing 10-bit dsi C-PHY panel, clks are different
from the usual. (dsi0_phy_pll_out_dsiclk's parent is dsi0_pll_bit_clk
now (dsiclk_sel = 0)) And we failed to set dsiclk's children.

dsi_link_clk_set_rate_6g: Set clk rates: pclk=172992000, byteclk=108120000

byteclk was set first to 108120000, so the vco rate was set to
108120000 * 7 * 1 * 1 = 756840000. When we was trying to set
172992000 on mdss_pixel_clk_src later.

Since there was no matched ratio, we failed to set it. And dsiclk
divider ratio was set to 15:1 (wrong cached register value 0xf and
didn't update), we finally got 50455997, apparently wrong.

  dsi0vco_clk                1       1        0        756839941
     dsi0_pll_out_div_clk    1       1        0        756839941
        dsi0_pll_post_out_div_clk 0       0        0        216239983
        dsi0_pll_bit_clk     2       2        0        756839941
           dsi0_phy_pll_out_dsiclk 2       2        0        50455997
              disp_cc_mdss_pclk1_clk_src 1       1        0        50455997
           dsi0_pll_by_2_bit_clk 0       0        0        378419970
           dsi0_phy_pll_out_byteclk 2       2        0        108119991
              disp_cc_mdss_byte1_clk_src 2       2        0        108119991

Downstream clk_summary shows the mdss_pixel_clk_src support the
ratio(35:16)

 dsi0_phy_pll_out_dsiclk             2       2        0        378420000
     disp_cc_mdss_pclk1_clk_src       1       1        0        172992000
 dsi0_phy_pll_out_byteclk            2       2        0        108120000
     disp_cc_mdss_byte1_clk_src       2       2        0        108120000

After checking downstream source, 15:4 also seems to be supported,
add them two.

Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260321095029.2259489-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-eliza: Add Eliza display clock controller support
Krzysztof Kozlowski [Thu, 19 Mar 2026 11:49:43 +0000 (12:49 +0100)] 
clk: qcom: dispcc-eliza: Add Eliza display clock controller support

Add a driver for the display clock controller on Qualcomm Eliza SoC,
which is copied from SM8750 driver plus changes:

1. Additional DT_HDMI_PHY_PLL_CLK clock input,
2. Eight new HDMI clocks,
3. Different PLLs (lucid and pongo).

Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260319-clk-qcom-dispcc-eliza-v3-2-d1f2b19a6e6b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoMerge branch '20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com'...
Bjorn Andersson [Mon, 23 Mar 2026 16:29:06 +0000 (11:29 -0500)] 
Merge branch '20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com' into clk-for-7.1

Merge the Eliza display clock controller binding through a topic branch,
to allow the constants to be shared with the DeviceTree branch.

2 months agodt-bindings: clock: qcom,eliza-dispcc: Add Eliza SoC display CC
Krzysztof Kozlowski [Thu, 19 Mar 2026 11:49:42 +0000 (12:49 +0100)] 
dt-bindings: clock: qcom,eliza-dispcc: Add Eliza SoC display CC

Add bindings for Qualcomm Eliza SoC display clock controller (dispcc),
which is very similar to one in SM8750, except new HDMI-related clocks
and additional clock input from HDMI PHY PLL.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260319-clk-qcom-dispcc-eliza-v3-1-d1f2b19a6e6b@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: videocc-sm8350: use depend on instead of select
Pengyu Luo [Fri, 13 Mar 2026 11:10:18 +0000 (19:10 +0800)] 
clk: qcom: videocc-sm8350: use depend on instead of select

Both sm8350 and sc8280xp use this, on sc8280xp, this would select
gcc-sm8350, we don't neet it on sc8280xp. use depend on to fix it.

Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260313111018.130068-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: gcc-ipq6018: mark gcc_xo_clk_src as critical
John Crispin [Wed, 11 Mar 2026 18:21:42 +0000 (19:21 +0100)] 
clk: qcom: gcc-ipq6018: mark gcc_xo_clk_src as critical

The XO clock source is always-on in hardware and cannot be gated.
Without CLK_IS_CRITICAL, runtime PM of downstream consumers (such as
the CMN PLL driver) cascades a disable up to gcc_xo_clk_src, causing
a branch status timeout warning.

The IPQ8074 GCC driver already marks this clock as CLK_IS_CRITICAL.
Apply the same fix to IPQ6018.

Signed-off-by: John Crispin <john@phrozen.org>
Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311182147.30266-1-ansuelsmth@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: camcc-sc8180x: Refactor to use qcom_cc_driver_data
Val Packett [Thu, 12 Mar 2026 11:12:16 +0000 (08:12 -0300)] 
clk: qcom: camcc-sc8180x: Refactor to use qcom_cc_driver_data

Use a qcom_cc_driver_data struct instead of a long custom probe
callback to align with modern qcom/gcc-*.c style.

No functional change intended.

Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-12-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-sm8250: Enable parents for pixel clocks
Val Packett [Thu, 12 Mar 2026 11:12:13 +0000 (08:12 -0300)] 
clk: qcom: dispcc-sm8250: Enable parents for pixel clocks

Add CLK_OPS_PARENT_ENABLE to MDSS pixel clock sources to ensure parent
clocks are enabled during clock operations, preventing potential
stability issues during display configuration.

Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250")
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-9-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-sm8250: Use shared ops on the mdss vsync clk
Val Packett [Thu, 12 Mar 2026 11:12:12 +0000 (08:12 -0300)] 
clk: qcom: dispcc-sm8250: Use shared ops on the mdss vsync clk

mdss_gdsc can get stuck on boot due to RCGs being left on from last boot.
As a fix, commit 01a0a6cc8cfd ("clk: qcom: Park shared RCGs upon
registration") introduced a callback to ensure the RCG is off upon init.
However, the fix depends on all shared RCGs being marked as such in code.

For SM8150/SC8180X/SM8250 the MDSS vsync clock was using regular ops,
unlike the same clock in the SC7180 code. This was causing display to
frequently fail to initialize after rebooting on the Surface Pro X.
Fix by using shared ops for this clock.

Fixes: 80a18f4a8567 ("clk: qcom: Add display clock controller driver for SM8150 and SM8250")
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-8-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: gcc-sc8180x: Refactor to use qcom_cc_driver_data
Val Packett [Thu, 12 Mar 2026 11:12:11 +0000 (08:12 -0300)] 
clk: qcom: gcc-sc8180x: Refactor to use qcom_cc_driver_data

Use a qcom_cc_driver_data struct instead of a long custom probe
callback to align with modern qcom/gcc-*.c style.

No functional change intended.

Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-7-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: gcc-sc8180x: Enable runtime PM support
Val Packett [Thu, 12 Mar 2026 11:12:10 +0000 (08:12 -0300)] 
clk: qcom: gcc-sc8180x: Enable runtime PM support

The GCC block on SC8180X is powered by the CX rail. We need to ensure
that it's enabled to prevent unwanted power collapse.

Enable runtime PM to keep the power flowing only when necessary.

Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-6-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: gcc-sc8180x: Use retention for PCIe power domains
Val Packett [Thu, 12 Mar 2026 11:12:09 +0000 (08:12 -0300)] 
clk: qcom: gcc-sc8180x: Use retention for PCIe power domains

As the PCIe host controller driver does not yet support dealing with the
loss of state during suspend, use retention for relevant GDSCs.

This fixes the link not surviving upon resume:

    nvme 0002:01:00.0: Unable to change power state from D3cold to D0, device inaccessible
    nvme nvme0: controller is down; will reset: CSTS=0xffffffff, PCI_STATUS read failed (134)
    nvme 0002:01:00.0: Unable to change power state from D3cold to D0, device inaccessible
    nvme nvme0: Disabling device after reset failure: -19

Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Manivannan Sadhasivam <mani@kernel.org>
Link: https://lore.kernel.org/r/20260312112321.370983-5-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: gcc-sc8180x: Use retention for USB power domains
Val Packett [Thu, 12 Mar 2026 11:12:08 +0000 (08:12 -0300)] 
clk: qcom: gcc-sc8180x: Use retention for USB power domains

The USB subsystem does not expect to lose its state on suspend:

    xhci-hcd xhci-hcd.0.auto: xHC error in resume, USBSTS 0x401, Reinit
    usb usb1: root hub lost power or was reset

(The reinitialization usually succeeds, but it does slow down resume.)

To maintain state during suspend, the relevant GDSCs need to stay in
retention mode, like they do on other similar SoCs. Change the mode to
PWRSTS_RET_ON to fix.

Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260312112321.370983-4-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: gcc-sc8180x: Add missing GDSCs
Val Packett [Thu, 12 Mar 2026 11:12:07 +0000 (08:12 -0300)] 
clk: qcom: gcc-sc8180x: Add missing GDSCs

There are 5 more GDSCs that we were ignoring and not putting to sleep,
which are listed in downstream DTS. Add them.

Fixes: 4433594bbe5d ("clk: qcom: gcc: Add global clock controller driver for SC8180x")
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260312112321.370983-3-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agodt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs
Val Packett [Thu, 12 Mar 2026 11:12:06 +0000 (08:12 -0300)] 
dt-bindings: clock: qcom,gcc-sc8180x: Add missing GDSCs

There are 5 more GDSCs that we were ignoring and not putting to sleep,
which are listed in downstream DTS. Add them.

Signed-off-by: Val Packett <val@packett.cool>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260312112321.370983-2-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC
Kathiravan Thirumoorthy [Wed, 18 Mar 2026 08:39:44 +0000 (14:09 +0530)] 
clk: qcom: add Global Clock controller (GCC) driver for IPQ5210 SoC

Add support for the global clock controller found on IPQ5210 SoC.

Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-ipq5210_boot_to_shell-v2-2-a87e27c37070@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoMerge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com'...
Bjorn Andersson [Thu, 19 Mar 2026 01:53:02 +0000 (20:53 -0500)] 
Merge branch '20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com' into clk-for-7.1

Merge the IPQ5210 Global clock controller binding through a topic
branch, to allow the constants to also be merged into the DeviceTree
branch.

2 months agodt-bindings: clock: add Qualcomm IPQ5210 GCC
Kathiravan Thirumoorthy [Wed, 18 Mar 2026 08:39:43 +0000 (14:09 +0530)] 
dt-bindings: clock: add Qualcomm IPQ5210 GCC

Add binding for the Qualcomm IPQ5210 Global Clock Controller.

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Kathiravan Thirumoorthy <kathiravan.thirumoorthy@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-ipq5210_boot_to_shell-v2-1-a87e27c37070@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: eliza: Cleanup redundant header includes
Krzysztof Kozlowski [Wed, 18 Mar 2026 11:08:44 +0000 (12:08 +0100)] 
clk: qcom: eliza: Cleanup redundant header includes

Remove unused header includes - drivers do not use any OF API.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-5-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: milos: Cleanup redundant header includes
Krzysztof Kozlowski [Wed, 18 Mar 2026 11:08:43 +0000 (12:08 +0100)] 
clk: qcom: milos: Cleanup redundant header includes

Remove unused header includes - drivers do not use any clk, OF or
PTR_ERR API, but they need declaration of of_device_id table.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-4-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: sm8750: Cleanup redundant header includes
Krzysztof Kozlowski [Wed, 18 Mar 2026 11:08:42 +0000 (12:08 +0100)] 
clk: qcom: sm8750: Cleanup redundant header includes

Remove unused header includes - drivers do not use any OF or runtime PM
API, but they need declaration of of_device_id table.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-3-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: glymur: Cleanup redundant header includes
Krzysztof Kozlowski [Wed, 18 Mar 2026 11:08:41 +0000 (12:08 +0100)] 
clk: qcom: glymur: Cleanup redundant header includes

Remove unused header includes - drivers do not use any OF or runtime PM
API.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-2-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: kaanapali: Cleanup redundant header includes
Krzysztof Kozlowski [Wed, 18 Mar 2026 11:08:40 +0000 (12:08 +0100)] 
clk: qcom: kaanapali: Cleanup redundant header includes

Remove unused header includes - drivers do not use any OF or runtime PM
API.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260318-clk-qcom-headers-v1-1-d5c6a3b11b67@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-sm6125: Add missing MDSS resets
Val Packett [Tue, 3 Mar 2026 03:41:23 +0000 (00:41 -0300)] 
clk: qcom: dispcc-sm6125: Add missing MDSS resets

The MDSS resets were left undescribed. Add them to allow resetting the
display subsystem, which is necessary to avoid issues caused by state
left over from the bootloader on various platforms.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260303034847.13870-5-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-sm6115: Add missing MDSS resets
Val Packett [Tue, 3 Mar 2026 03:41:22 +0000 (00:41 -0300)] 
clk: qcom: dispcc-sm6115: Add missing MDSS resets

The MDSS resets were left undescribed. Add them to allow resetting the
display subsystem, which is necessary to avoid issues caused by state
left over from the bootloader on various platforms.

Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260303034847.13870-4-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoMerge branch '20260303034847.13870-2-val@packett.cool' into clk-for-7.1
Bjorn Andersson [Wed, 11 Mar 2026 20:44:31 +0000 (15:44 -0500)] 
Merge branch '20260303034847.13870-2-val@packett.cool' into clk-for-7.1

Merge the definition of MDSS resets for SM6115 and SM6125 to allow them
to be made available in the DeviceTree branch.

2 months agodt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets
Val Packett [Tue, 3 Mar 2026 03:41:21 +0000 (00:41 -0300)] 
dt-bindings: clock: qcom,dispcc-sm6125: Define MDSS resets

Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260303034847.13870-3-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agodt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets
Val Packett [Tue, 3 Mar 2026 03:41:20 +0000 (00:41 -0300)] 
dt-bindings: clock: qcom,sm6115-dispcc: Define MDSS resets

Add the missing defines for MDSS resets, which are necessary to reset
the display subsystem in order to avoid issues caused by state left over
from the bootloader.

While here, align comment style with other SoCs.

Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Val Packett <val@packett.cool>
Link: https://lore.kernel.org/r/20260303034847.13870-2-val@packett.cool
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: Add TCSR clock driver for Eliza
Abel Vesa [Wed, 11 Mar 2026 14:46:36 +0000 (16:46 +0200)] 
clk: qcom: Add TCSR clock driver for Eliza

Add the TCSR clock controller that provides the refclks on Eliza
platform for PCIe, USB and UFS subsystems.

Co-developed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-6-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: Add support for Global clock controller on Eliza
Taniya Das [Wed, 11 Mar 2026 14:46:35 +0000 (16:46 +0200)] 
clk: qcom: Add support for Global clock controller on Eliza

Add support for Global clock controller for Eliza Qualcomm SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-5-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: rpmh: Add support for Eliza rpmh clocks
Taniya Das [Wed, 11 Mar 2026 14:46:34 +0000 (16:46 +0200)] 
clk: qcom: rpmh: Add support for Eliza rpmh clocks

Add the RPMH clocks present in Eliza SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-4-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoMerge branch '20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com' into clk...
Bjorn Andersson [Wed, 11 Mar 2026 20:31:22 +0000 (15:31 -0500)] 
Merge branch '20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com' into clk-for-7.1

Merge DeviceTree bindings for Eliza global, rpmh, and tcsr clock
controllers through a topic branch, in case we need them in the
DeviceTree branch as well.

2 months agodt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Eliza
Taniya Das [Wed, 11 Mar 2026 14:46:33 +0000 (16:46 +0200)] 
dt-bindings: clock: qcom-rpmhcc: Add RPMHCC for Eliza

Update the documentation for RPMH clock controller for Eliza SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-3-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agodt-bindings: clock: qcom: Document the Eliza TCSR Clock Controller
Taniya Das [Wed, 11 Mar 2026 14:46:32 +0000 (16:46 +0200)] 
dt-bindings: clock: qcom: Document the Eliza TCSR Clock Controller

Add bindings documentation for TCSR Clock Controller for Eliza SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-2-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agodt-bindings: clock: qcom: document the Eliza Global Clock Controller
Taniya Das [Wed, 11 Mar 2026 14:46:31 +0000 (16:46 +0200)] 
dt-bindings: clock: qcom: document the Eliza Global Clock Controller

Add bindings documentation for the Global Clock Controller on Qualcomm
Eliza SoC. Reuse the Milos bindings schema since the controller resources
are exactly the same, even though the controllers are incompatible between
them.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Signed-off-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260311-eliza-clocks-v6-1-453c4cf657a2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting
Konrad Dybcio [Wed, 4 Mar 2026 13:48:31 +0000 (14:48 +0100)] 
clk: qcom: dispcc[01]-sa8775p: Fix DSI byte clock rate setting

The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: e700bfd2f976 ("clk: qcom: Add support for Display clock Controllers on SA8775P")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-5-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-sm4450: Fix DSI byte clock rate setting
Konrad Dybcio [Wed, 4 Mar 2026 13:48:30 +0000 (14:48 +0100)] 
clk: qcom: dispcc-sm4450: Fix DSI byte clock rate setting

The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: 76f05f1ec766 ("clk: qcom: Add DISPCC driver support for SM4450")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-4-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-milos: Fix DSI byte clock rate setting
Konrad Dybcio [Wed, 4 Mar 2026 13:48:29 +0000 (14:48 +0100)] 
clk: qcom: dispcc-milos: Fix DSI byte clock rate setting

The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: f40b5217dce1 ("clk: qcom: Add Display Clock controller (DISPCC) driver for Milos")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-3-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-kaanapali: Fix DSI byte clock rate setting
Konrad Dybcio [Wed, 4 Mar 2026 13:48:28 +0000 (14:48 +0100)] 
clk: qcom: dispcc-kaanapali: Fix DSI byte clock rate setting

The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: 6c6750b7061c ("clk: qcom: dispcc: Add support for display clock controller Kaanapali")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-2-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-glymur: Fix DSI byte clock rate setting
Konrad Dybcio [Wed, 4 Mar 2026 13:48:27 +0000 (14:48 +0100)] 
clk: qcom: dispcc-glymur: Fix DSI byte clock rate setting

The clock tree for byte_clk_src is as follows:

   ┌──────byte0_clk_src─────┐
   │                        │
byte0_clk            byte0_div_clk_src
                            │
                     byte0_intf_clk

If both of its direct children have CLK_SET_RATE_PARENT with different
requests, byte0_clk_src (and its parent) will be reconfigured. In this
case, byte0_intf should strictly follow the rate of byte0_clk (with
some adjustments based on PHY mode).

Remove CLK_SET_RATE_PARENT from byte0_div_clk_src to avoid this issue.

Fixes: b4d15211c408 ("clk: qcom: dispcc-glymur: Add support for Display Clock Controller")
Signed-off-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260304-topic-dsi_byte_fixup-v1-1-b79b29f83176@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
2 months agoclk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers
White Lewis [Tue, 3 Mar 2026 11:55:50 +0000 (19:55 +0800)] 
clk: qcom: dispcc-sc8280xp: remove CLK_SET_RATE_PARENT from byte_div_clk_src dividers

The four byte_div_clk_src dividers (disp{0,1}_cc_mdss_byte{0,1}_div_clk_src)
had CLK_SET_RATE_PARENT set. When the DSI driver calls clk_set_rate() on
byte_intf_clk, the rate-change propagates through the divider up to the
parent PLL (byte_clk_src), halving the byte clock rate.

A simiar issue had been also encountered on SM8750.
b8501febdc51 ("clk: qcom: dispcc-sm8750: Drop incorrect CLK_SET_RATE_PARENT on byte intf parent").

Likewise, remove CLK_SET_RATE_PARENT from all four byte divider clocks
so that clk_set_rate() on the divider adjusts only the divider ratio,
leaving the parent PLL untouched.

Fixes: 4a66e76fdb6d ("clk: qcom: Add SC8280XP display clock controller")
Signed-off-by: White Lewis <liu224806@gmail.com>
[pengyu: reword]
Signed-off-by: Pengyu Luo <mitltlatltl@gmail.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260303115550.9279-1-mitltlatltl@gmail.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoclk: qcom: dispcc-glymur: use RCG2 ops for DPTX1 AUX clock source
Dmitry Baryshkov [Mon, 12 Jan 2026 02:12:22 +0000 (04:12 +0200)] 
clk: qcom: dispcc-glymur: use RCG2 ops for DPTX1 AUX clock source

The clk_dp_ops are supposed to be used for DP-related clocks with a
proper MND divier. Use shared RCG2 ops for dptx1_aux_clk_src, the same
as all other DPTX AUX clocks in this driver.

Fixes: b4d15211c408 ("clk: qcom: dispcc-glymur: Add support for Display Clock Controller")
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260112-dp-aux-clks-v1-1-456b0c11b069@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoclk: qcom: videocc-glymur: Add video clock controller driver for Glymur
Taniya Das [Mon, 2 Feb 2026 10:56:53 +0000 (16:26 +0530)] 
clk: qcom: videocc-glymur: Add video clock controller driver for Glymur

Add support for the video clock controller for video clients to be able
to request for videocc clocks on Glymur platform.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-4-8f7d8b4d8edd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoclk: qcom: gcc-glymur: Add video axi clock resets for glymur
Taniya Das [Mon, 2 Feb 2026 10:56:52 +0000 (16:26 +0530)] 
clk: qcom: gcc-glymur: Add video axi clock resets for glymur

The global clock controller video axi reset clocks are required by
the video SW driver to assert and deassert the clock resets during
their power down sequence. Hence add these clock resets.

Fixes: efe504300a17 ("clk: qcom: gcc: Add support for Global Clock Controller")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-3-8f7d8b4d8edd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agodt-bindings: clock: qcom: Add video clock controller on Glymur SoC
Taniya Das [Mon, 2 Feb 2026 10:56:51 +0000 (16:26 +0530)] 
dt-bindings: clock: qcom: Add video clock controller on Glymur SoC

Add compatible string for Glymur video clock controller and the bindings
for Glymur Qualcomm SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-2-8f7d8b4d8edd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agodt-bindings: clock: qcom: Add GCC video axi reset clock for Glymur
Taniya Das [Mon, 2 Feb 2026 10:56:50 +0000 (16:26 +0530)] 
dt-bindings: clock: qcom: Add GCC video axi reset clock for Glymur

The global clock controller video axi reset clocks are required by
the video SW driver to assert and deassert the clock resets.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260202-glymur_videocc-v2-1-8f7d8b4d8edd@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoclk: qcom: Add support for GPUCC and GXCLK for Glymur
Taniya Das [Tue, 27 Jan 2026 07:15:50 +0000 (12:45 +0530)] 
clk: qcom: Add support for GPUCC and GXCLK for Glymur

Support the graphics clock controller for Glymur for Graphics SW
driver to use the clocks. GXCLKCTL (Graphics GX Clock Controller) is a
block dedicated to managing clocks for the GPU subsystem on GX power
domain. The GX clock controller driver manages only the GX GDSC and the
rest of the resources of the controller are managed by the firmware.

Update the compatible for Graphics GX Clock Controller for Glymur as the
GX clock controller is a reuse of the Kaanapali driver.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-By: Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260127-glymur_gpucc-v1-2-547334c81ba2@oss.qualcomm.com
[bjorn: Fixed copyright and de-acronymized MODULE_DESCRIPTION]
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agodt-bindings: clock: qcom: document the Glymur GPU Clock Controller
Taniya Das [Tue, 27 Jan 2026 07:15:49 +0000 (12:45 +0530)] 
dt-bindings: clock: qcom: document the Glymur GPU Clock Controller

Glymur SoC has Qualcomm GX(graphics) clock controller and also the
Graphics clock controller. The GX graphics clock controller helps in the
recovery of the Graphics subsystem.

Add bindings documentation for the Glymur Graphics Clock and Graphics
power domain Controller for Glymur SoC.

Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Acked-by: Rob Herring (Arm) <robh@kernel.org>
Link: https://lore.kernel.org/r/20260127-glymur_gpucc-v1-1-547334c81ba2@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoclk: qcom: De-acronymize Glymur SoC name
Krzysztof Kozlowski [Tue, 17 Feb 2026 13:00:49 +0000 (14:00 +0100)] 
clk: qcom: De-acronymize Glymur SoC name

Glymur is a codename of Qualcomm SoC, not an acronym.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260217130047.281813-4-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agodt-bindings: clock: qcom,glymur-dispcc: De-acronymize SoC name
Krzysztof Kozlowski [Tue, 17 Feb 2026 13:00:48 +0000 (14:00 +0100)] 
dt-bindings: clock: qcom,glymur-dispcc: De-acronymize SoC name

Glymur is a codename of Qualcomm SoC, not an acronym.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Reviewed-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Link: https://lore.kernel.org/r/20260217130047.281813-3-krzysztof.kozlowski@oss.qualcomm.com
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
3 months agoLinux 7.0-rc1 v7.0-rc1
Linus Torvalds [Sun, 22 Feb 2026 21:18:59 +0000 (13:18 -0800)] 
Linux 7.0-rc1

3 months agoMerge tag 'fsverity-for-linus' of git://git.kernel.org/pub/scm/fs/fsverity/linux
Linus Torvalds [Sun, 22 Feb 2026 21:12:04 +0000 (13:12 -0800)] 
Merge tag 'fsverity-for-linus' of git://git.kernel.org/pub/scm/fs/fsverity/linux

Pull fsverity fixes from Eric Biggers:

 - Fix a build error on parisc

 - Remove the non-large-folio-aware function fsverity_verify_page()

* tag 'fsverity-for-linus' of git://git.kernel.org/pub/scm/fs/fsverity/linux:
  fsverity: fix build error by adding fsverity_readahead() stub
  fsverity: remove fsverity_verify_page()
  f2fs: make f2fs_verify_cluster() partially large-folio-aware
  f2fs: remove unnecessary ClearPageUptodate in f2fs_verify_cluster()

3 months agoMerge tag 'libcrypto-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git...
Linus Torvalds [Sun, 22 Feb 2026 21:09:33 +0000 (13:09 -0800)] 
Merge tag 'libcrypto-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux

Pull crypto library fix from Eric Biggers:
 "Fix a big endian specific issue in the PPC64-optimized AES code"

* tag 'libcrypto-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/ebiggers/linux:
  lib/crypto: powerpc/aes: Fix rndkey_from_vsx() on big endian CPUs

3 months agoCREDITS: Add -next to Stephen Rothwell's entry
Mark Brown [Tue, 17 Feb 2026 13:10:46 +0000 (13:10 +0000)] 
CREDITS: Add -next to Stephen Rothwell's entry

Stephen retired and stepped back from -next maintainership, update his
entry in CREDITS to recognise his 18 years of hard work making it what
it is today and all the impact it's had on our development process.

Also update to his current GnuPG key while we're here.

Acked-by: Stephen Rothwell <sfr@canb.auug.org.au>
Acked-by: SeongJae Park <sj@kernel.org>
Reviewed-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agox509: select CONFIG_CRYPTO_LIB_SHA256
Arnd Bergmann [Tue, 17 Feb 2026 08:26:49 +0000 (08:26 +0000)] 
x509: select CONFIG_CRYPTO_LIB_SHA256

The x509 public key code gained a dependency on the sha256 hash
implementation, causing a rare link time failure in randconfig
builds:

  arm-linux-gnueabi-ld: crypto/asymmetric_keys/x509_public_key.o: in function `x509_get_sig_params':
  x509_public_key.c:(.text.x509_get_sig_params+0x12): undefined reference to `sha256'
  arm-linux-gnueabi-ld: (sha256): Unknown destination type (ARM/Thumb) in crypto/asymmetric_keys/x509_public_key.o
  x509_public_key.c:(.text.x509_get_sig_params+0x12): dangerous relocation: unsupported relocation

Select the necessary library code from Kconfig.

Fixes: 2c62068ac86b ("x509: Separately calculate sha256 for blacklist")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: David Howells <dhowells@redhat.com>
Reviewed-by: Eric Biggers <ebiggers@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoxz: fix arm fdt compile error for kmalloc replacement
Haiyue Wang [Sun, 22 Feb 2026 12:11:00 +0000 (20:11 +0800)] 
xz: fix arm fdt compile error for kmalloc replacement

Align to the commit bf4afc53b77a ("Convert 'alloc_obj' family to use the
new default GFP_KERNEL argument") update the 'kmalloc_obj' declaration
for userspace to fix below compile error:

  In file included from arch/arm/boot/compressed/../../../../lib/decompress_unxz.c:241,
                   from arch/arm/boot/compressed/decompress.c:56:
  arch/arm/boot/compressed/../../../../lib/xz/xz_dec_stream.c: In function 'xz_dec_init':
  arch/arm/boot/compressed/../../../../lib/xz/xz_dec_stream.c:787:28: error: implicit declaration of function 'kmalloc_obj'; did you mean 'kmalloc'? [-Wimplicit-function-declaration]
     787 |         struct xz_dec *s = kmalloc_obj(*s);
         |                            ^~~~~~~~~~~
         |                            kmalloc

Signed-off-by: Haiyue Wang <haiyuewa@163.com>
Fixes: 69050f8d6d07 ("treewide: Replace kmalloc with kmalloc_obj for non-scalar types")
Fixes: bf4afc53b77a ("Convert 'alloc_obj' family to use the new default GFP_KERNEL argument")
Reviewed-by: Kees Cook <kees@kernel.org>
Acked-by: Lasse Collin <lasse.collin@tukaani.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoMerge tag 'rtc-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux
Linus Torvalds [Sun, 22 Feb 2026 17:43:11 +0000 (09:43 -0800)] 
Merge tag 'rtc-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux

Pull RTC updates from Alexandre Belloni:

 - loongson: Loongson-2K0300 support

 - s35390a: nvmem support

 - zynqmp: rework calibration

* tag 'rtc-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/abelloni/linux:
  rtc: ds1390: fix number of bytes read from RTC
  rtc: class: Remove duplicate check for alarm
  rtc: optee: simplify OP-TEE context match
  rtc: interface: Alarm race handling should not discard preceding error
  rtc: s35390a: implement nvmem support
  rtc: loongson: Add Loongson-2K0300 support
  dt-bindings: rtc: loongson: Document Loongson-2K0300 compatible
  dt-bindings: rtc: loongson: Correct Loongson-1C interrupts property
  dt-bindings: rtc: renesas,rz-rtca3: Add RZ/V2N support
  dt-bindings: rtc: cpcap: convert to schema
  rtc: zynqmp: use dynamic max and min offset ranges
  rtc: zynqmp: rework set_offset
  rtc: zynqmp: rework read_offset
  rtc: zynqmp: check calibration max value
  rtc: zynqmp: correct frequency value
  rtc: amlogic-a4: Remove IRQF_ONESHOT
  rtc: pcf8563: use correct of_node for output clock
  rtc: max31335: use correct CONFIG symbol in IS_REACHABLE()
  rtc: nvvrs: Add ARCH_TEGRA to the NV VRS RTC driver

3 months agoMerge tag 'rust-fixes-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/ojeda...
Linus Torvalds [Sun, 22 Feb 2026 16:43:31 +0000 (08:43 -0800)] 
Merge tag 'rust-fixes-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/ojeda/linux

Pull rust fixes from Miguel Ojeda:
 "Toolchain and infrastructure:

   - Pass '-Zunstable-options' flag required by the future Rust 1.95.0

   - Fix 'objtool' warning for Rust 1.84.0

  'kernel' crate:

   - 'irq' module: add missing bound detected by the future Rust 1.95.0

   - 'list' module: add missing 'unsafe' blocks and placeholder safety
     comments to macros (an issue for future callers within the crate)

  'pin-init' crate:

   - Clean Clippy warning that changed behavior in the future Rust
     1.95.0"

* tag 'rust-fixes-7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/ojeda/linux:
  rust: list: Add unsafe blocks for container_of and safety comments
  rust: pin-init: replace clippy `expect` with `allow`
  rust: irq: add `'static` bounds to irq callbacks
  objtool/rust: add one more `noreturn` Rust function
  rust: kbuild: pass `-Zunstable-options` for Rust 1.95.0

3 months agoMerge tag 'trace-rv-7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace...
Linus Torvalds [Sun, 22 Feb 2026 16:40:13 +0000 (08:40 -0800)] 
Merge tag 'trace-rv-7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace

Pull runtime verifier fix from Steven Rostedt:

 - Fix multiple definition of __pcpu_unique_da_mon_this

   After refactoring monitors, we used static per-cpu variables with the
   same names across different per-cpu monitors. This is explicitly
   disallowed for modules on some architectures (alpha) or if
   CONFIG_DEBUG_FORCE_WEAK_PER_CPU is enabled (e.g. Fedora's debug
   kernel). Make sure all those variables have different names to avoid
   compilation issues.

* tag 'trace-rv-7.0-2' of git://git.kernel.org/pub/scm/linux/kernel/git/trace/linux-trace:
  rv: Fix multiple definition of __pcpu_unique_da_mon_this

3 months agoConvert remaining multi-line kmalloc_obj/flex GFP_KERNEL uses
Kees Cook [Sun, 22 Feb 2026 07:46:04 +0000 (23:46 -0800)] 
Convert remaining multi-line kmalloc_obj/flex GFP_KERNEL uses

Conversion performed via this Coccinelle script:

  // SPDX-License-Identifier: GPL-2.0-only
  // Options: --include-headers-for-types --all-includes --include-headers --keep-comments
  virtual patch

  @gfp depends on patch && !(file in "tools") && !(file in "samples")@
  identifier ALLOC = {kmalloc_obj,kmalloc_objs,kmalloc_flex,
      kzalloc_obj,kzalloc_objs,kzalloc_flex,
    kvmalloc_obj,kvmalloc_objs,kvmalloc_flex,
    kvzalloc_obj,kvzalloc_objs,kvzalloc_flex};
  @@

   ALLOC(...
  - , GFP_KERNEL
   )

  $ make coccicheck MODE=patch COCCI=gfp.cocci

Build and boot tested x86_64 with Fedora 42's GCC and Clang:

Linux version 6.19.0+ (user@host) (gcc (GCC) 15.2.1 20260123 (Red Hat 15.2.1-7), GNU ld version 2.44-12.fc42) #1 SMP PREEMPT_DYNAMIC 1970-01-01
Linux version 6.19.0+ (user@host) (clang version 20.1.8 (Fedora 20.1.8-4.fc42), LLD 20.1.8) #1 SMP PREEMPT_DYNAMIC 1970-01-01

Signed-off-by: Kees Cook <kees@kernel.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoConvert more 'alloc_obj' cases to default GFP_KERNEL arguments
Linus Torvalds [Sun, 22 Feb 2026 04:03:00 +0000 (20:03 -0800)] 
Convert more 'alloc_obj' cases to default GFP_KERNEL arguments

This converts some of the visually simpler cases that have been split
over multiple lines.  I only did the ones that are easy to verify the
resulting diff by having just that final GFP_KERNEL argument on the next
line.

Somebody should probably do a proper coccinelle script for this, but for
me the trivial script actually resulted in an assertion failure in the
middle of the script.  I probably had made it a bit _too_ trivial.

So after fighting that far a while I decided to just do some of the
syntactically simpler cases with variations of the previous 'sed'
scripts.

The more syntactically complex multi-line cases would mostly really want
whitespace cleanup anyway.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoConvert 'alloc_flex' family to use the new default GFP_KERNEL argument
Linus Torvalds [Sun, 22 Feb 2026 01:06:51 +0000 (17:06 -0800)] 
Convert 'alloc_flex' family to use the new default GFP_KERNEL argument

This is the exact same thing as the 'alloc_obj()' version, only much
smaller because there are a lot fewer users of the *alloc_flex()
interface.

As with alloc_obj() version, this was done entirely with mindless brute
force, using the same script, except using 'flex' in the pattern rather
than 'objs*'.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoConvert 'alloc_obj' family to use the new default GFP_KERNEL argument
Linus Torvalds [Sun, 22 Feb 2026 00:37:42 +0000 (16:37 -0800)] 
Convert 'alloc_obj' family to use the new default GFP_KERNEL argument

This was done entirely with mindless brute force, using

    git grep -l '\<k[vmz]*alloc_objs*(.*, GFP_KERNEL)' |
        xargs sed -i 's/\(alloc_objs*(.*\), GFP_KERNEL)/\1)/'

to convert the new alloc_obj() users that had a simple GFP_KERNEL
argument to just drop that argument.

Note that due to the extreme simplicity of the scripting, any slightly
more complex cases spread over multiple lines would not be triggered:
they definitely exist, but this covers the vast bulk of the cases, and
the resulting diff is also then easier to check automatically.

For the same reason the 'flex' versions will be done as a separate
conversion.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoadd default_gfp() helper macro and use it in the new *alloc_obj() helpers
Linus Torvalds [Sun, 22 Feb 2026 00:14:11 +0000 (16:14 -0800)] 
add default_gfp() helper macro and use it in the new *alloc_obj() helpers

Most simple allocations use GFP_KERNEL, and with the new allocation
helpers being introduced, let's just take advantage of that to simplify
that default case.

It's a numbers game:

    git grep 'alloc_obj(' |
sed 's/.*\(GFP_[_A-Z]*\).*/\1/' |
sort | uniq -c | sort -n | tail

shows that about 90% of all those new allocator instances just use that
standard GFP_KERNEL.

Those helpers are already macros, and we can easily just make it be the
default case when the gfp argument is missing.

And yes, we could do that for all the legacy interfaces too, but let's
keep it to just the new ones at least for now, since those all got
converted recently anyway, so this is not any "extra" noise outside of
that limited conversion.

And, in fact, I want to do this before doing the -rc1 release, exactly
so that we don't get extra merge conflicts.

Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoslab.h: disable completely broken overflow handling in flex allocations
Linus Torvalds [Sat, 21 Feb 2026 23:12:09 +0000 (15:12 -0800)] 
slab.h: disable completely broken overflow handling in flex allocations

Commit 69050f8d6d07 ("treewide: Replace kmalloc with kmalloc_obj for
non-scalar types") started using the new allocation helpers, and in the
process showed that they were completely non-working.

The overflow logic in overflows_flex_counter_type() is completely the
wrong way around, and that broke __alloc_flex() completely.  By chance,
the resulting code was then such a mess that clang generated
sufficiently garbage code that objtool warned about it all.  Which made
it somewhat quicker to narrow things down.

While fixing overflows_flex_counter_type() would presumably fix this
all, I'm excising the whole broken overflow logic from __alloc_flex(),
because we don't want that kind of code in basic allocation functions
anyway.

That (no longer) broken overflows_flex_counter_type() thing needs to be
inserted into the actual __set_flex_counter() logic in the unlikely case
that we ever want this at all.  And made conditional.

Fixes: 81cee9166a90 ("compiler_types: Introduce __flex_counter() and family")
Fixes: 69050f8d6d07 ("treewide: Replace kmalloc with kmalloc_obj for non-scalar types")
Cc: Kees Cook <kees@kernel.org>
Link: https://lore.kernel.org/all/CAHk-=whEd020BYzGTzYrENjD9Z5_82xx6h8HsQvH5xDSnv0=Hw@mail.gmail.com/
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
3 months agoMerge tag 'kmalloc_obj-treewide-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kerne...
Linus Torvalds [Sat, 21 Feb 2026 19:02:58 +0000 (11:02 -0800)] 
Merge tag 'kmalloc_obj-treewide-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux

Pull kmalloc_obj conversion from Kees Cook:
 "This does the tree-wide conversion to kmalloc_obj() and friends using
  coccinelle, with a subsequent small manual cleanup of whitespace
  alignment that coccinelle does not handle.

  This uncovered a clang bug in __builtin_counted_by_ref(), so the
  conversion is preceded by disabling that for current versions of
  clang.  The imminent clang 22.1 release has the fix.

  I've done allmodconfig build tests for x86_64, arm64, i386, and arm. I
  did defconfig builds for alpha, m68k, mips, parisc, powerpc, riscv,
  s390, sparc, sh, arc, csky, xtensa, hexagon, and openrisc"

* tag 'kmalloc_obj-treewide-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/kees/linux:
  kmalloc_obj: Clean up after treewide replacements
  treewide: Replace kmalloc with kmalloc_obj for non-scalar types
  compiler_types: Disable __builtin_counted_by_ref for Clang

3 months agoMerge tag 'perf-tools-for-v7.0-1-2026-02-21' of git://git.kernel.org/pub/scm/linux...
Linus Torvalds [Sat, 21 Feb 2026 18:51:08 +0000 (10:51 -0800)] 
Merge tag 'perf-tools-for-v7.0-1-2026-02-21' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools

Pull perf tools updates from Arnaldo Carvalho de Melo:

 - Introduce 'perf sched stats' tool with record/report/diff workflows
   using schedstat counters

 - Add a faster libdw based addr2line implementation and allow selecting
   it or its alternatives via 'perf config addr2line.style='

 - Data-type profiling fixes and improvements including the ability to
   select fields using 'perf report''s -F/-fields, e.g.:

     'perf report --fields overhead,type'

 - Add 'perf test' regression tests for Data-type profiling with C and
   Rust workloads

 - Fix srcline printing with inlines in callchains, make sure this has
   coverage in 'perf test'

 - Fix printing of leaf IP in LBR callchains

 - Fix display of metrics without sufficient permission in 'perf stat'

 - Print all machines in 'perf kvm report -vvv', not just the host

 - Switch from SHA-1 to BLAKE2s for build ID generation, remove SHA-1
   code

 - Fix 'perf report's histogram entry collapsing with '-F' option

 - Use system's cacheline size instead of a hardcoded value in 'perf
   report'

 - Allow filtering conversion by time range in 'perf data'

 - Cover conversion to CTF using 'perf data' in 'perf test'

 - Address newer glibc const-correctness (-Werror=discarded-qualifiers)
   issues

 - Fixes and improvements for ARM's CoreSight support, simplify ARM SPE
   event config in 'perf mem', update docs for 'perf c2c' including the
   ARM events it can be used with

 - Build support for generating metrics from arch specific python
   script, add extra AMD, Intel, ARM64 metrics using it

 - Add AMD Zen 6 events and metrics

 - Add JSON file with OpenHW Risc-V CVA6 hardware counters

 - Add 'perf kvm' stats live testing

 - Add more 'perf stat' tests to 'perf test'

 - Fix segfault in `perf lock contention -b/--use-bpf`

 - Fix various 'perf test' cases for s390

 - Build system cleanups, bump minimum shellcheck version to 0.7.2

 - Support building the capstone based annotation routines as a plugin

 - Allow passing extra Clang flags via EXTRA_BPF_FLAGS

* tag 'perf-tools-for-v7.0-1-2026-02-21' of git://git.kernel.org/pub/scm/linux/kernel/git/perf/perf-tools: (255 commits)
  perf test script: Add python script testing support
  perf test script: Add perl script testing support
  perf script: Allow the generated script to be a path
  perf test: perf data --to-ctf testing
  perf test: Test pipe mode with data conversion --to-json
  perf json: Pipe mode --to-ctf support
  perf json: Pipe mode --to-json support
  perf check: Add libbabeltrace to the listed features
  perf build: Allow passing extra Clang flags via EXTRA_BPF_FLAGS
  perf test data_type_profiling.sh: Skip just the Rust tests if code_with_type workload is missing
  tools build: Fix feature test for rust compiler
  perf libunwind: Fix calls to thread__e_machine()
  perf stat: Add no-affinity flag
  perf evlist: Reduce affinity use and move into iterator, fix no affinity
  perf evlist: Missing TPEBS close in evlist__close()
  perf evlist: Special map propagation for tool events that read on 1 CPU
  perf stat-shadow: In prepare_metric fix guard on reading NULL perf_stat_evsel
  Revert "perf tool_pmu: More accurately set the cpus for tool events"
  tools build: Emit dependencies file for test-rust.bin
  tools build: Make test-rust.bin be removed by the 'clean' target
  ...

3 months agoMerge tag 'cocci-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jlawall...
Linus Torvalds [Sat, 21 Feb 2026 18:25:42 +0000 (10:25 -0800)] 
Merge tag 'cocci-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jlawall/linux

Pull coccinelle updates from Julia Lawall:
 "This simplifies and clarifies the handling of output generated by
  Coccinelle that is sent to standard error.

  By default, this goes to /dev/null. Remind the user of that and
  encourage them to provide another file name (Benjamin Philip)"

* tag 'cocci-7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/jlawall/linux:
  Documentation: Coccinelle: document debug log handling
  scripts: coccicheck: warn on unset debug file
  scripts: coccicheck: simplify debug file handling

3 months agoMerge tag 'ntb-7.0' of https://github.com/jonmason/ntb
Linus Torvalds [Sat, 21 Feb 2026 18:20:32 +0000 (10:20 -0800)] 
Merge tag 'ntb-7.0' of https://github.com/jonmason/ntb

Pull NTB (PCIe non-transparent bridge) updates from Jon Mason:
 "NTB updates include debugfs improvements, correctness fixes, cleanups,
  and new hardware support:

  ntb_transport QP stats are converted to seq_file, a tx_memcpy_offload
  module parameter is introduced with associated ordering fixes, and a
  debugfs queue name truncation bug is corrected.

  Additional fixes address format specifier mismatches in ntb_tool and
  boundary conditions in the Switchtec driver, while unused MSI helpers
  are removed and the codebase migrates to dma_map_phys().

  Intel Gen6 (Diamond Rapids) NTB support is also added"

* tag 'ntb-7.0' of https://github.com/jonmason/ntb:
  NTB: ntb_transport: Use seq_file for QP stats debugfs
  NTB: ntb_transport: Fix too small buffer for debugfs_name
  ntb/ntb_tool: correct sscanf format for u64 and size_t in tool_peer_mw_trans_write
  ntb: intel: Add Intel Gen6 NTB support for DiamondRapids
  NTB/msi: Remove unused functions
  ntb: ntb_hw_switchtec: Increase MAX_MWS limit to 256
  ntb: ntb_hw_switchtec: Fix array-index-out-of-bounds access
  ntb: ntb_hw_switchtec: Fix shift-out-of-bounds for 0 mw lut
  NTB: epf: allow built-in build
  ntb: migrate to dma_map_phys instead of map_page
  NTB: ntb_transport: Add 'tx_memcpy_offload' module option
  NTB: ntb_transport: Remove unused 'retries' field from ntb_queue_entry

3 months agoMerge tag 'io_uring-20260221' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe...
Linus Torvalds [Sat, 21 Feb 2026 18:05:49 +0000 (10:05 -0800)] 
Merge tag 'io_uring-20260221' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux

Pull io_uring fixes from Jens Axboe:

 - A fix for a missing URING_CMD128 opcode check, fixing an issue with
   the SQE mixed mode support introduced in 6.19. Merged late due to
   having multiple dependencies

 - Add sqe->cmd size checking for big SQEs, similar to what we have for
   normal sized SQEs

 - Fix a race condition in zcrx, that leads to a double free

* tag 'io_uring-20260221' of git://git.kernel.org/pub/scm/linux/kernel/git/axboe/linux:
  io_uring: Add size check for sqe->cmd
  io_uring: add IORING_OP_URING_CMD128 to opcode checks
  io_uring/zcrx: fix user_ref race between scrub and refill paths

3 months agoMerge tag 'fixes-2026-02-21' of git://git.kernel.org/pub/scm/linux/kernel/git/rppt...
Linus Torvalds [Sat, 21 Feb 2026 17:58:22 +0000 (09:58 -0800)] 
Merge tag 'fixes-2026-02-21' of git://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock

Pull memblock fix from Mike Rapoport:
 "Fix detection of NUMA node for CXL windows

  phys_to_target_node() may assign a CXL Fixed Memory Window to the
  wrong NUMA node when a CXL node resides in the gap of discontinuous
  System RAM node.

  Fix this by checking both numa_meminfo and numa_reserved_meminfo,
  preferring the reserved NID when the address appears in both"

* tag 'fixes-2026-02-21' of git://git.kernel.org/pub/scm/linux/kernel/git/rppt/memblock:
  mm: numa_memblks: Identify the accurate NUMA ID of CFMW

3 months agoMerge tag 'sched_ext-for-7.0-fixes' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sat, 21 Feb 2026 17:38:59 +0000 (09:38 -0800)] 
Merge tag 'sched_ext-for-7.0-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/sched_ext

Pull sched_ext fixes from Tejun Heo:

 - Various bug fixes for the example schedulers and selftests

* tag 'sched_ext-for-7.0-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/tj/sched_ext:
  tools/sched_ext: fix getopt not re-parsed on restart
  tools/sched_ext: scx_userland: fix data races on shared counters
  tools/sched_ext: scx_pair: fix stride == 0 crash on single-CPU systems
  tools/sched_ext: scx_central: fix CPU_SET and skeleton leak on early exit
  tools/sched_ext: scx_userland: fix stale data on restart
  tools/sched_ext: scx_flatcg: fix potential stack overflow from VLA in fcg_read_stats
  selftests/sched_ext: Fix rt_stall flaky failure
  tools/sched_ext: scx_userland: fix restart and stats thread lifecycle bugs
  tools/sched_ext: scx_central: fix sched_setaffinity() call with the set size
  tools/sched_ext: scx_flatcg: zero-initialize stats counter array

3 months agoMerge tag 'v7.0-rc-part2-ksmbd-server-fixes' of git://git.samba.org/ksmbd
Linus Torvalds [Sat, 21 Feb 2026 17:11:32 +0000 (09:11 -0800)] 
Merge tag 'v7.0-rc-part2-ksmbd-server-fixes' of git://git.samba.org/ksmbd

Pull smb server fixes from Steve French:
 "Two small fixes:

   - fix potential deadlock

   - minor cleanup"

* tag 'v7.0-rc-part2-ksmbd-server-fixes' of git://git.samba.org/ksmbd:
  ksmbd: call ksmbd_vfs_kern_path_end_removing() on some error paths
  smb: server: Remove duplicate include of misc.h

3 months agoDocumentation: Coccinelle: document debug log handling
Benjamin Philip [Tue, 6 Jan 2026 19:08:36 +0000 (00:38 +0530)] 
Documentation: Coccinelle: document debug log handling

The current debug documentation does not mention that logs are printed
to stdout unless DEBUG_FILE is set. It also doesn't mention that
Coccinelle cannot overwrite debug files.

Document this behaviour in the examples and reference it in the
debugging section.

Signed-off-by: Benjamin Philip <benjamin.philip495@gmail.com>
Signed-off-by: Julia Lawall <julia.lawall@inria.fr>
3 months agoscripts: coccicheck: warn on unset debug file
Benjamin Philip [Tue, 6 Jan 2026 19:08:35 +0000 (00:38 +0530)] 
scripts: coccicheck: warn on unset debug file

coccicheck prints debug logs to stdout unless a debug file has been set.
This makes it hard to read coccinelle's suggested changes, especially
for someone new to coccicheck.

From this commit, we warn about this behaviour from within the script on
an unset debug file. Explicitly setting the debug file to /dev/null
suppresses the warning while keeping the default.

Signed-off-by: Benjamin Philip <benjamin.philip495@gmail.com>
Signed-off-by: Julia Lawall <julia.lawall@inria.fr>
3 months agoscripts: coccicheck: simplify debug file handling
Benjamin Philip [Tue, 6 Jan 2026 19:08:34 +0000 (00:38 +0530)] 
scripts: coccicheck: simplify debug file handling

This commit separates handling unset files and pre-existing files. It
also eliminates a duplicated check for unset files in run_cmd_parmap().

Signed-off-by: Benjamin Philip <benjamin.philip495@gmail.com>
Signed-off-by: Julia Lawall <julia.lawall@inria.fr>
3 months agokmalloc_obj: Clean up after treewide replacements
Kees Cook [Sat, 21 Feb 2026 08:12:19 +0000 (00:12 -0800)] 
kmalloc_obj: Clean up after treewide replacements

Coccinelle doesn't handle re-indenting line escapes. Fix the 2 places
where these got misaligned.

Remove 2 now-redundant type casts, found with:
$ git grep -P 'struct (\S+).*\)\s*k\S+alloc_(objs?|flex)\(struct \1'

Signed-off-by: Kees Cook <kees@kernel.org>
3 months agotreewide: Replace kmalloc with kmalloc_obj for non-scalar types
Kees Cook [Sat, 21 Feb 2026 07:49:23 +0000 (23:49 -0800)] 
treewide: Replace kmalloc with kmalloc_obj for non-scalar types

This is the result of running the Coccinelle script from
scripts/coccinelle/api/kmalloc_objs.cocci. The script is designed to
avoid scalar types (which need careful case-by-case checking), and
instead replace kmalloc-family calls that allocate struct or union
object instances:

Single allocations: kmalloc(sizeof(TYPE), ...)
are replaced with: kmalloc_obj(TYPE, ...)

Array allocations: kmalloc_array(COUNT, sizeof(TYPE), ...)
are replaced with: kmalloc_objs(TYPE, COUNT, ...)

Flex array allocations: kmalloc(struct_size(PTR, FAM, COUNT), ...)
are replaced with: kmalloc_flex(*PTR, FAM, COUNT, ...)

(where TYPE may also be *VAR)

The resulting allocations no longer return "void *", instead returning
"TYPE *".

Signed-off-by: Kees Cook <kees@kernel.org>
3 months agocompiler_types: Disable __builtin_counted_by_ref for Clang
Kees Cook [Fri, 20 Feb 2026 21:15:58 +0000 (13:15 -0800)] 
compiler_types: Disable __builtin_counted_by_ref for Clang

Unfortunately, there is a corner case of __builtin_counted_by_ref()
usage that crashes[1] Clang since support was introduced in Clang 19.
Disable it prior to Clang 22. Found while tested kmalloc_obj treewide
refactoring (via kmalloc_flex() usage).

Link: https://github.com/llvm/llvm-project/issues/182575
Signed-off-by: Kees Cook <kees@kernel.org>
3 months agotools/sched_ext: fix getopt not re-parsed on restart
David Carlier [Wed, 18 Feb 2026 19:22:35 +0000 (19:22 +0000)] 
tools/sched_ext: fix getopt not re-parsed on restart

After goto restart, optind retains its advanced position from the
previous getopt loop, causing getopt() to immediately return -1.
This silently drops all command-line options on the restarted skeleton.

Reset optind to 1 at the restart label so options are re-parsed.

Affected schedulers: scx_simple, scx_central, scx_flatcg, scx_pair,
scx_sdt, scx_cpu0.

Signed-off-by: David Carlier <devnexen@gmail.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
3 months agotools/sched_ext: scx_userland: fix data races on shared counters
David Carlier [Wed, 18 Feb 2026 19:22:23 +0000 (19:22 +0000)] 
tools/sched_ext: scx_userland: fix data races on shared counters

The stats thread reads nr_vruntime_enqueues, nr_vruntime_dispatches,
nr_vruntime_failed, and nr_curr_enqueued concurrently with the main
thread writing them, with no synchronization.

Use __atomic builtins with relaxed ordering for all accesses to these
counters to eliminate the data races.

Only display accuracy is affected, not scheduling correctness.

Signed-off-by: David Carlier <devnexen@gmail.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
3 months agoMerge tag 'spi-fix-v7.0-merge-window' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sat, 21 Feb 2026 01:14:36 +0000 (17:14 -0800)] 
Merge tag 'spi-fix-v7.0-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi

Pull spi fixes from Mark Brown:
 "There's a relatively large but ultimately simple fix for spidev here
  which addresses some ABBA races by simplifying down to just using a
  single lock, it's not clear to me that there was ever any benefit in
  having the two separate locks in the first place.

  We also have simple missing error check fix in in the wpcm-fiu driver"

* tag 'spi-fix-v7.0-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi:
  spi: spidev: fix lock inversion between spi_lock and buf_lock
  spi: wpcm-fiu: Fix potential NULL pointer dereference in wpcm_fiu_probe()

3 months agoMerge tag 'regulator-fix-v7.0-merge-window' of git://git.kernel.org/pub/scm/linux...
Linus Torvalds [Sat, 21 Feb 2026 01:11:55 +0000 (17:11 -0800)] 
Merge tag 'regulator-fix-v7.0-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator

Pull regulator fixes from Mark Brown:
 "A few driver specific fixes, plus a patch from Bjorn which removes a
  fixed limit on regulator names that was breaking some Qualcomm
  systems"

* tag 'regulator-fix-v7.0-merge-window' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/regulator:
  regulator: s2mps11: fix pctrlsel macro usage in s2mpg10_of_parse_cb()
  regulator: s2mps11: drop redundant sanity checks in s2mpg10_of_parse_cb()
  regulator: core: Remove regulator supply_name length limit
  regulator: mt6363: Fix interrmittent timeout

3 months agoMerge tag 'pci-v7.0-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci
Linus Torvalds [Sat, 21 Feb 2026 01:05:52 +0000 (17:05 -0800)] 
Merge tag 'pci-v7.0-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci

Pull pci fixes from Bjorn Helgaas:

 - Fix bridge window selection bug that prevented resource assignment
   (Kai-Heng Feng)

 - Fix bridge window sizing, which failed to assign resources for
   windows containing only optional resources (ROMs, SR-IOV BARs, etc)
   (Ilpo Järvinen)

 - Select CONFIGFS_FS when PCI_EPF_TEST is enabled to avoid a link error
   (Arnd Bergmann)

 - Fix recently merged Endpoint inbound submapping feature (Koichiro
   Den)

* tag 'pci-v7.0-fixes-1' of git://git.kernel.org/pub/scm/linux/kernel/git/pci/pci:
  PCI: dwc: ep: Always clear IB maps on BAR update
  PCI: dwc: ep: Return after clearing BAR-match inbound mapping
  PCI: endpoint: pci-epf-test: Select configfs
  PCI: Account fully optional bridge windows correctly
  PCI: Validate window resource type in pbus_select_window_for_type()

3 months agoMerge tag 'dmi-for-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare...
Linus Torvalds [Sat, 21 Feb 2026 00:18:48 +0000 (16:18 -0800)] 
Merge tag 'dmi-for-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging

Pull dmi update from Jean Delvare:

 - include product_family info in dmi-id modalias

* tag 'dmi-for-v7.0' of git://git.kernel.org/pub/scm/linux/kernel/git/jdelvare/staging:
  firmware/dmi: Include product_family info to modalias

3 months agoMerge tag 'gpio-fixes-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel...
Linus Torvalds [Sat, 21 Feb 2026 00:10:54 +0000 (16:10 -0800)] 
Merge tag 'gpio-fixes-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux

Pull gpio fixes from Bartosz Golaszewski:

 - add a missing IS_ERR() check in gpio-nomadik

 - fix a NULL-pointer dereference in GPIO character device code

 - restore label matching in swnode-lookup due to reported regressions
   in existing users (this will get removed again once we audit and
   update all drivers)

 - fix remove path in GPIO sysfs code

 - normalize the return value of gpio_chip::get() in gpio-amd-fch

* tag 'gpio-fixes-for-v7.0-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/brgl/linux:
  gpio: amd-fch: ionly return allowed values from amd_fch_gpio_get()
  gpio: sysfs: fix chip removal with GPIOs exported over sysfs
  gpio: swnode: restore the swnode-name-against-chip-label matching
  gpio: cdev: Avoid NULL dereference in linehandle_create()
  gpio: nomadik: Add missing IS_ERR() check