David Barbion [Wed, 10 Sep 2025 21:18:55 +0000 (23:18 +0200)]
board: rockchip: Fix RG353M model renaming
Anbernic RG353M is hardware compatible with RG353P. Only the form-factor
differs. So only one DTS is created for both machines with
"Anbernic RG353P" as default model. If a RG353M is detected, the model
should be overwritten with the correct name.
Actually, it's overwritten with "Anbernic" only making the process of
machine detection a little harder.
However, to determine the size of the string "Anbernic RG353M", it is
sizeof() which is used resulting in obtaining the size of the pointer
(which is 8 bytes on ARM64) not the size of the pointed string.
strlen() should be used instead.
Signed-off-by: David Barbion <davidb@230ruedubac.fr> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 29 Oct 2025 11:34:25 +0000 (12:34 +0100)]
rockchip: imply most symbols for ARCH_ROCKCHIP
Forcing all those symbols on means we cannot make the binary smaller or
with unnecessary features or drivers disabled. This is especially useful
for security, auditing and certification where less code built means
less to look at (and less surface attack) and less to patch, but also
for making binary images smaller which typically means faster boot.
It is possible to have boards without MMC, NAND or SPI flashes, without
anything on SPI or I2C buses, nothing to control over PWM or GPIO or for
which we have no interest in regulator control or serial output so make
it possible to remove all that if desired.
No intended change in default selected symbols.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 65e2c14d5a5a ("binman: btool: mkimage: use Bintool.version")
removed the version argument from the run method but forgot to remove it
from the method docstring, so let's fix this oversight.
Fixes: 65e2c14d5a5a ("binman: btool: mkimage: use Bintool.version") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 28 Oct 2025 16:57:37 +0000 (17:57 +0100)]
rockchip: spl_common: fix TIMER_FMODE constant
The free running mode is 0 at bit offset 1. User mode is 1 at bit offset
1. Currently, free running mode is 1 at offset 0, which is already the
case thanks to TIME_EN.
So, this essentially does not change the actual value written to the
register as it is TIME_EN | TIMER_FMODE which currently is 0x1 | BIT(0)
= 0b1, and will become 0x1 | (0 << 1) = 0b1.
I checked PX30, RK3128, RK3188, RK3228, RK3288, RK3308, RK3328, RK3368
RK3506, RK3562 and RK3568 TRMs.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 28 Oct 2025 16:57:36 +0000 (17:57 +0100)]
rockchip: rk3399: fix TIMER_FMODE constant
The free running mode is 0 at bit offset 1. User mode is 1 at bit offset
1. Currently, free running mode is 1 at offset 0, which is already the
case thanks to TIME_EN.
So, this essentially does not change the actual value written to the
register as it is TIME_EN | TIMER_FMODE which currently is 0x1 | BIT(0)
= 0b1, and will become 0x1 | (0 << 1) = 0b1.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 28 Oct 2025 16:57:35 +0000 (17:57 +0100)]
rockchip: rk3036: use rockchip_stimer_init from spl_common.o
The only difference with the implementation in spl_common.c is that we
check whether the timer has already been enabled. Considering this is
running in SPL, the first stage on RK3036, I feel like it's guaranteed
to not be enabled by default. No public TRM though and I don't have
access to an RK3036 device so take this as a guess.
Size of SPL binary increases by 8B for evb-rk3036.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 28 Oct 2025 16:57:34 +0000 (17:57 +0100)]
rockchip: px30: use rockchip_stimer_init from spl_common.o for TPL
Instead of redefining what is essentially the same code in
secure_timer_init, let's simply use rockchip_stimer_init from
spl_common.o instead.
This increases the size of the TPL by 16B, due to the added check of
STIMER already being enabled. Experimentally, STIMER is not already
enabled when in TPL.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 3ba04aa78ba71faab4a339f5ab15bc81a3e0a51b) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d272bc0c747a5af49cf98140ebd25a702f84ab52) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Oct 2025 16:50:50 +0000 (16:50 +0000)]
board: rockchip: Add Luckfox Omni3576
Luckfox Omni3576 Carrier Board with Core3576 Module, powered by the
Rockchip RK3576 SoC with four Cortex-A72 cores, four Cortex-A53 cores,
and a Mali-G52 MC3 GPU.
Features tested with a Core3576 Rev1.1 on a Omni3576 carrier board:
- SD-card boot
- eMMC boot
- LED
- PCIe/NVMe
- USB2.0 HOST
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Oct 2025 15:47:19 +0000 (15:47 +0000)]
board: rockchip: Add Radxa ROCK 4D
The Radxa ROCK 4D is a compact single-board computer (SBC) featuring
numerous top-tier functions, features, and expansion options.
Equipped with the Rockchip RK3576 or RK3576J SoC, the ROCK 4D boasts an
octa-core CPU (4x Cortex-A72 + 4x Cortex-A53), Mali-G52 GPU, and a
powerful 6 TOPS NPU, making it ideal for AI and multimedia tasks.
Features tested on a Radxa ROCK 4D v1.112:
- SPI Flash boot
- Ethernet
- PCIe/NVMe
- USB host
ROCK 4D boards with SPI Flash is configured to boot from FSPI0->UFS->USB,
or directly from USB when the MASKROM button is pressed, booting
directly from SD-card is not possible on these boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Oct 2025 15:47:18 +0000 (15:47 +0000)]
rockchip: rk3576: Add SPI Flash boot support
The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB
differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81.
Add a RK3576 specific read_brom_bootsource_id() function to help decode
the new bootsource id values and the required boot_devices mapping of
sfc0 and sfc1 to help support booting from SPI flash on RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Oct 2025 15:47:16 +0000 (15:47 +0000)]
rockchip: spl: Add a read_brom_bootsource_id() helper
The bootsource ids reported by BootROM of RK3528 and RK3576 for e.g.
SPI NOR and USB differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81 on RK3528 and RK3576.
Add a helper function to read the bootsource id. This helper function
will be used to translate the new values to the common BROM_BOOTSOURCE
enum values on RK3528 and RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 31 Aug 2025 16:49:35 +0000 (16:49 +0000)]
arm: dts: rockchip: Include OTP in U-Boot pre-reloc phase for RK3326
Update rk3326-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
Jonas Karlman [Sun, 31 Aug 2025 16:49:30 +0000 (16:49 +0000)]
rockchip: odroid-go2: Use env from same storage FIT was loaded from
Change to dynamically select what storage media to use for the U-Boot
environment depending on from what storage media the FIT images was
loaded from, fall back to use env from nowhere.
U-Boot SPL 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Trying to boot from MMC1
...
Loading Environment from MMC... Reading from MMC(0)...
or
U-Boot SPL 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Trying to boot from SPI
...
Loading Environment from SPIFlash...
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 31 Aug 2025 16:49:27 +0000 (16:49 +0000)]
rockchip: odroid-go2: Use power off at power plug-in event
Include the RK817 PMIC in SPL and enable Kconfig options to power off
the handheld gaming device when it was powered on due to a power cable
plug-in event:
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
out
Power Off due to plug-in event
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- riscv: dts: starfive: cherry-pick jh7110 updates from v6.18-rc1-dts
- riscv: Add upstream boards Milk-V Mars CM and Mars CM Lite
- timer: sifive_clint: Add GHRTv2 compaible string
Tom Rini [Fri, 11 Jul 2025 15:16:01 +0000 (09:16 -0600)]
mtd: nvmxip: Make use of LBAF for printing lbaint_t
When printing the contents of an lbaint_t variable we need to use LBAF
to print it in order to get the correct format type depending on 32 or
64bit-ness.
Tom Rini [Fri, 11 Jul 2025 15:15:57 +0000 (09:15 -0600)]
mtd: spi: sf_dataflash.c: Make use of 'z' for printing size_t
When printing the contents of an size_t variable we need to use z prefix
to the format character in order to get the correct format type
depending on 32 or 64bit-ness.
Tom Rini [Fri, 4 Jul 2025 21:45:56 +0000 (15:45 -0600)]
mtd: Correct dependency on SYS_FLASH_CHECKSUM
This feature requires that CFG_SYS_FLASH_BASE is defined and this in
turn is only done in the case of FLASH_CFI_DRIVER && !CFI_FLASH or in
other words, when DM_MTD is not enabled.
Tom Rini [Wed, 2 Jul 2025 01:06:09 +0000 (19:06 -0600)]
mtd: Add function prototype for mtd_read_oob_bf(...)
The function mtd_read_oob_bf is called by cmd/nand.c but does not have a
prototype in any header. Add this to include/linux/mtd/mtd.h as that is
the most logical place currently.
Fixes: 1fac57720719 ("nand: Add a watch command") Signed-off-by: Tom Rini <trini@konsulko.com>
Andrew Goodbody [Tue, 1 Jul 2025 16:12:44 +0000 (17:12 +0100)]
mtd: nand: Prevent dereference of NULL pointer
In nand_wait_ready there is a loop that includes a NULL check for
chip->dev_ready before it is dereferenced. Use a NULL check once the
loop is exited as well to cover the case where it exits due to a timeout
and it is therefore not known if chip->dev_ready is NULL or not.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Michael Trimarchi <michael@amarulasolutions.com>
Andrew Goodbody [Thu, 26 Jun 2025 10:49:32 +0000 (11:49 +0100)]
cmd: mtd: Prevent use of uninitialised variable
ret maybe used uninitialised in some cases so instead
initialise it first to prevent this.
This issue was found by Smatch.
Fixes: 9671243e8d10 (cmd: mtd: Use the subcmd infrastructure to declare mtd sub-commands) Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Tom Rini [Sat, 15 Mar 2025 01:29:11 +0000 (19:29 -0600)]
ARM: renesas: Drop 'imply MULTI_DTB_FIT_USER_DEFINED_AREA' lines
As the code is today, we get a warning about "select" statements on
"choice" options not doing anything. This is why for all of the boards
which had an 'imply MULTI_DTB_FIT_USER_DEFINED_AREA' they then also had
to set the option in the defconfig. Drop the imply lines here.
Tuyen Dang [Tue, 28 Oct 2025 14:22:27 +0000 (15:22 +0100)]
ufs: Add UFS driver for Renesas R-Car X5H
Add UFS driver for UFS controller present on Renesas R-Car X5H R8A78000.
The controller uses different initialization code compared to previous
generation UFS controller present in Renesas R-Car S4 R8A779F0, and the
majority of the driver is the initialization, hence a new driver.
[Marek: Clean driver up, add SCMI reset handling, use read_poll_timeout(),
pass error values out of ufs_renesas_pre_init(), change the
compatible string to "renesas,r8a78000-ufs" to align with
previous generation "renesas,r8a779f0-ufs"]
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com> Signed-off-by: Tuyen Dang <tuyen.dang.xa@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251028142335.18125-7-marek.vasut+renesas@mailbox.org Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Marek Vasut [Tue, 28 Oct 2025 14:22:26 +0000 (15:22 +0100)]
ufs: renesas: Update Kconfig entry help text
The current Renesas UFS driver contains initialization code
that is specific to R-Car S4 R8A779F0. The upcoming R-Car X5H
initialization code is different and contained in a separate
driver. Update the Kconfig entry help text for the current
driver to help discern it from the X5H driver. No functional
change.
Marek Vasut [Tue, 28 Oct 2025 14:22:25 +0000 (15:22 +0100)]
ufs: Call ufs_scsi_bind() from uclass .post_bind
Instead of duplicating the ufs_scsi_bind() call in every driver,
call it from UFS uclass .post_bind callback for every driver in
one place. While doing so, inline ufs_scsi_bind() directly into
ufs_post_bind() as trivial device_bind_driver() call.
Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Link: https://patch.msgid.link/20251028142335.18125-5-marek.vasut+renesas@mailbox.org
[narmstrong: also updated the rockchip and mediatek drivers] Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Andrew Goodbody [Mon, 6 Oct 2025 15:09:25 +0000 (16:09 +0100)]
spi: spi-uclass: Use unwind goto
In _spi_get_bus_and_cs the check for stacked parallel support needing
multiple chip select support does a direct return on error. Instead it
should set the error code in ret and then use the unwind goto.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 12 Aug 2025 16:42:59 +0000 (17:42 +0100)]
spi: fspi: Logical or used instead of logical and
In erratum_err050568 the test for apllicability uses logical or to check
multiple chip IDs but this means the test will always evaluate to true
as at least 1 term will always be true. Logical and should have been
used so that the expression evaluates to true if all terms are true
which would mean that no chip ID of interest was in use.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 12 Aug 2025 13:31:16 +0000 (14:31 +0100)]
spi: ich: Do not use uninitialised value
In ich_spi_exec_op_swseq the variable with_address is only assigned a
value in the case of op->addr.nbytes being non-zero.
Initialise with_address to zero. so that it is always valid.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Thu, 3 Jul 2025 14:40:46 +0000 (15:40 +0100)]
clk: Return value calculated by ERR_PTR
In clk_set_default_get_by_id ret is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.
This issue found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Acked-by: Quentin Schulz <quentin.schulz@cherry.de>
Tom Rini [Tue, 28 Oct 2025 15:59:55 +0000 (09:59 -0600)]
Merge patch series "clk: versaclock: Fix two issues found by Smatch"
Andrew Goodbody <andrew.goodbody@linaro.org> says:
Should return value calculated by ERR_PTR as calling code attempts to
check for it.
Also do not dereference a pointer that could be an error pointer before
checking it with IS_ERR.
Andrew Goodbody [Thu, 31 Jul 2025 11:11:47 +0000 (12:11 +0100)]
mmc: owl_mmc: Do not dereference data before NULL check
In owl_mmc_prepare_data there is a NULL check for the pointer data but
it happens after data has already been dereferenced. Refactor the code
so that the NULL check happens before any code dereferences data.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Fri, 25 Jul 2025 12:04:26 +0000 (13:04 +0100)]
gpio: intel_gpio: Initialise or0 and or1
In intel_gpio_set_flags the two variables or0 and or1 may be used
uninitialised. Correct this by setting initial values in the
declaration.
Also there is no need to use '|=' when the initial value is 0 and there
is only one assignment performed to each variable so just use '='
instead.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Marek Vasut [Tue, 28 Oct 2025 14:22:23 +0000 (15:22 +0100)]
ufs: core: Rename ufs.c to ufs-uclass.c
Previous commit folded existing ufs-uclass.c into ufs.c ,
which produced a nice and reviewable change , but also broke
the UCLASS should be in *-uclass.c pattern. Fix it. Keep the
change separate from the previous one to make this reviewable.
Andrew Goodbody [Tue, 12 Aug 2025 11:34:39 +0000 (12:34 +0100)]
spi: cadence_qspi: Do not return unset error code
In spi_calibration if the low range fails to calibrate then the code
attempted to return the variable err but this has not been set in this
case. Instead just return -EIO.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 12 Aug 2025 11:34:38 +0000 (12:34 +0100)]
spi: cadence_qspi: Off by 1 in test for timeout
In cadence_qspi_apb_exec_flash_cmd the test for a timeout uses a
post-decrement on the variable retry which will result in a value of -1
after the loop exit, or it would if the variable were signed.
To fix this make retry a signed variable and test its value for being
equal to -1.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Igor Belwon [Sat, 11 Oct 2025 19:10:06 +0000 (21:10 +0200)]
ufs: Add MediaTek UFS driver
Add the UFS driver for MediaTek platforms.
Loosely based on the Linux driver, this UFS driver can successfully get a
link and R/W access to the UFS chip on the MediaTek MT6878 mobile SoC,
when U-Boot is running as lk, or as the kernel (Secure world access is
not tested)
Jared McArthur [Fri, 10 Oct 2025 19:55:56 +0000 (14:55 -0500)]
ufs: Add bRefClkFreq attribute setting
A UFS device needs its bRefClkFreq attribute set to the correct value
before switching to high speed. If bRefClkFreq is set to the wrong
value, all transactions after the power mode change will fail.
The bRefClkFreq depends on the host controller and the device.
Query the device's current bRefClkFreq and compare with the ref_clk
specified in the device-tree. If the two differ, set the bRefClkFreq
to the device-tree's ref_clk frequency.
Taken from Linux kernel v6.17 (drivers/ufs/core/ufshcd.c and
include/ufs/ufs.h) and ported to U-Boot.
Signed-off-by: Jared McArthur <j-mcarthur@ti.com> Reviewed-by: Bryan Brattlof <bb@ti.com> Reviewed-by: Udit Kumar <u-kumar1@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Link: https://patch.msgid.link/20251010195556.1772611-3-j-mcarthur@ti.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
However, the U-Boot code still uses these values directly without shifting,
and resulting in wrong bitfield placement in the Transfer Request
Descriptor.
This fixes the issue by applying the necessary shift to align the value.
Fixes: d232d7fdbf6f ("ufs: core: sync ufshci.h with Linux v6.12") Signed-off-by: Kunihiko Hayashi <hayashi.kunihiko@socionext.com> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://patch.msgid.link/20251010024557.673787-1-hayashi.kunihiko@socionext.com Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org>
Andrew Goodbody [Tue, 7 Oct 2025 11:42:12 +0000 (12:42 +0100)]
ufs: ti-j721e: Correct error detection
In ti_j721e_ufs_probe there is a call to clk_get_rate but the code after
that attempts to detect an error from that call incorrectly uses
IS_ERR_VALUE. Instead the test should just be for regular error codes.
The call returns an unsigned long so that needs to be cast to a signed type
first of all.
Andrew Goodbody [Wed, 23 Jul 2025 15:54:07 +0000 (16:54 +0100)]
clk: versaclock: return value calculated by ERR_PTR
In versaclock_get_name -ENOMEM is passed to ERR_PTR but nothing is
done with the value that this calculates which is obviously not the
intention of the code. This is confirmed by the code around where this
function is called.
Instead return the value from ERR_PTR.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 30 Sep 2025 15:52:24 +0000 (16:52 +0100)]
usb: musb-new: Cannot test unsigned member to be negative
You cannot test an unsigned member of a struct for being negative, the
test will always fail. Instead assign the return value of
fdtdec_get_int, which returns an int, to a temporary variable declared
as an int, so that it can be tested for being negative before being
assigned to the unsigned struct member.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 30 Sep 2025 15:52:23 +0000 (16:52 +0100)]
usb: musb-new: Limit check array index before use
epnum is used as an index into an array. The limit check for this index
should be performed before using it to access an element in the array to
prevent possible bounds overrun.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Andrew Goodbody [Tue, 30 Sep 2025 15:52:22 +0000 (16:52 +0100)]
usb: musb-new: Null check before dereference
A null check for the variable 'data' was introduced before dereferencing
it for set_phy_power but other uses were not so protected. Add the null
check for other dereferences of 'data'.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 30 Sep 2025 10:34:44 +0000 (11:34 +0100)]
usb: xhci: exynos: variable node should be signed
The variable node is assigned to the return value of a function that
returns an int. It is tested for being negative and then passed as an
argument to a function that takes an int. So 'node' should not be
declared as unsigned. Correct it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 30 Sep 2025 16:06:44 +0000 (17:06 +0100)]
usb: ulpi: Incorrect operator used
Combining two bits into a mask to be used so that the same write code
can be used to set or reset bits in a register clearly needs to use the
binary 'or' operator, not the binary 'and'. Fix it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Tue, 30 Sep 2025 09:56:02 +0000 (10:56 +0100)]
usb: ohci-hcd: Null check lurb_priv before dereference
When a variable needs a null check before it is dreferenced ensure that
this is done even in the case of assignment on declaration. This was not
happening for lurb_priv so correct it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Thu, 25 Sep 2025 11:56:44 +0000 (12:56 +0100)]
usb: fsl-dt-fixup: Return an error code on error
fsl_fdt_fixup_usb_erratum uses strcmp to detect an error but then
returns 'err' without it being set to an error. Calling code may not
detect that an error occurred leading to a silent failure. Instead just
return -EINVAL.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org>
Andrew Goodbody [Mon, 29 Sep 2025 16:53:11 +0000 (17:53 +0100)]
usb: ehci: exynos: variable node should be signed
THe variable node is assigned to the return value of a function that
returns an int. It is tested for being negative and then passed as an
argument to a function that takes an int. So 'node' should not be
declared as unsigned. Correct it.
This issue was found by Smatch.
Signed-off-by: Andrew Goodbody <andrew.goodbody@linaro.org> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
E Shattow [Tue, 21 Oct 2025 23:09:59 +0000 (16:09 -0700)]
configs: starfive: Add Milk-V Mars CM and Mars CM Lite to visionfive2
Add Milk-V Mars CM and Mars CM Lite to visionfive2.
These boards were previously supported and then removed in the transition
to OF_UPSTREAM. The dts have landed in the for-next queue so let's add the
boards again.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Hal Feng <hal.feng@starfivetech.com>
E Shattow [Wed, 15 Oct 2025 10:22:53 +0000 (03:22 -0700)]
riscv: dts: starfive: add Milk-V Mars CM Lite system-on-module
Milk-V Mars CM Lite is a System-on-Module based on the Milk-V Mars CM
without the onboard eMMC storage component populated and configured
instead for SD3.0 Card Slot on that interface via 100-pin connector.
Link to Milk-V Mars CM Lite schematics: https://github.com/milkv-mars/mars-files/tree/main/Mars-CM_Hardware_Schematices
Link to StarFive JH7110 Technical Reference Manual: https://doc-en.rvspace.org/JH7110/TRM/index.html
Link to Raspberry Pi CM4IO datasheet: https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf
Add the devicetree file to make use of StarFive JH7110 common supported
features PMIC, EEPROM, UART, I2C, GPIO, PCIe, QSPI Flash, PWM, and
Ethernet. Also configure the eMMC interface mmc0 for SD Card use and
configure the common SD Card interface mmc1 for onboard SDIO BT+WiFi.
E Shattow [Wed, 15 Oct 2025 10:22:51 +0000 (03:22 -0700)]
riscv: dts: starfive: add Milk-V Mars CM system-on-module
Milk-V Mars CM is a System-on-Module based on the StarFive VisionFive 2
board and Radxa CM3 System-on-Module compatible with the Raspberry Pi
CM4IO Classic IO Board.
Mars CM SoM features:
- StarFive JH7110 System on Chip with RV64GC up to 1.5GHz
- AXP15060 Power Management Unit
- LPDDR4 2GB / 4GB / 8GB DRAM memory
- BL24C04F 4K bits (512 x 8) EEPROM
- GigaDevice 25LQ128EWIG QSPI NOR Flash 16M or SoC ROM UART loader for
boot (selectable by GPIO)
- eMMC5.0 8GB / 16GB / 32GB flash storage onboard
- AP6256 via SDIO 2.0 onboard wireless connectivity WiFi 5 + Bluetooth
5.2 (optional, present in models with WiFi feature)
- 1x Motorcomm YT8531C Gigabit Ethernet PHY
- IMG BXE-4-32 Integrated GPU with 3D Acceleration:
- H.264 & H.265 4K@60fps Decoding
- H.265 1080p@30fps Encoding
- JPEG encoder / decoder
Additional features available via 2x 100-pin connectors for CM4IO Board:
- 1x HDMI 2.0
- 1x MIPI DSI (4-lanes)
- 1x 2CH Audio out (via GPIO)
- 1x MIPI CSI (2x2-lanes or 1x4-lanes)
- 1x USB 2.0
- 1x PCIe 1-lane Host, Gen 2 (5Gbps)
- Up to 28x GPIO, supporting 3.3V
- UART x6
- PWM x8
- I2C x7
- SPI
- I2S
Link to Milk-V Mars CM schematics: https://github.com/milkv-mars/mars-files/tree/main/Mars-CM_Hardware_Schematices
Link to StarFive JH7110 Technical Reference Manual: https://doc-en.rvspace.org/JH7110/TRM/index.html
Link to Raspberry Pi CM4IO datasheet: https://datasheets.raspberrypi.com/cm4io/cm4io-datasheet.pdf
Add the devicetree file to make use of StarFive JH7110 common supported
features PMIC, EEPROM, UART, I2C, GPIO, eMMC, PCIe, QSPI Flash, PWM, and
Ethernet. Also configure the common SD Card interface mmc1 for onboard
SDIO BT+WiFi.
projects / thirdparty / u-boot.git / log
