Michal Simek [Wed, 15 Feb 2017 09:13:22 +0000 (10:13 +0100)]
arm64: zynqmp: Fix psu_init* external functions
In older vivado version some psu_init* files didn't contain prog_reg
function that's why it was added to xil_io.h.
The same with mask*() which were missing.
From some pre v2017.1 these issues were fixed that's why
some functions were commented in origin psu_init* files.
This patch adds prog_reg() and mask*() to psu_init* files
where it is missing and remove comment from files which have
prog_reg() already.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 10 Feb 2017 07:13:56 +0000 (08:13 +0100)]
arm64: zynqmp: Add i2c node selection to Kconfig
zcu100 revA is using different i2c then revB that's why add this quick
workaround by selecting i2c via defconfig. This should go away when i2c
cadence DM based driver is used.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Extract from Linux mainline patch:
The ARM architected timer specification mandates that the interrupt
associated with each timer is level triggered (which corresponds to
the "counter >= comparator" condition).
A number of DTs are being remarkably creative, declaring the interrupt
to be edge triggered. A quick look at the TRM for the corresponding ARM
CPUs clearly shows that this is wrong, and I've corrected those.
For non-ARM designs (and in the absence of a publicly available TRM),
I've made them active low as well, which can't be completely wrong
as the GIC cannot disinguish between level low and level high.
The respective maintainers are of course welcome to prove me wrong.
While I was at it, I took the liberty to fix a couple of related issue,
such as some spurious affinity bits on ThunderX, and their complete
absence on ls1043a (both of which seem to be related to copy-pasting
from other DTs).
Acked-by: Duc Dang <dhdang@apm.com> Acked-by: Carlo Caione <carlo@endlessm.com> Acked-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Krzysztof Kozlowski <k.kozlowski@samsung.com> Acked-by: Dinh Nguyen <dinguyen@opensource.altera.com> Acked-by: Masahiro Yamada <yamada.masahiro@socionext.com> Signed-off-by: Marc Zyngier <marc.zyngier@arm.com> Signed-off-by: Arnd Bergmann <arnd@arndb.de> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
ARM64: zynqmp: PM: Specify power domains for DP related nodes
Currently DP power domain (pd_dp) is not attached to any of the DP nodes which is
causing genpd to trigger a power down request for DP domain, making all DP related
peripherals unusable. So assign power domains for all DP related nodes to enable
proper accounting of DP power domain usage.
Signed-off-by: Jyotheeswar Reddy <jyothee@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Wed, 18 Jan 2017 12:04:48 +0000 (17:34 +0530)]
arch: arm64: dts: add USB OTG interrupts support in ZynqMP device tree
This patch adds OTG interrupt support in device tree. It will add
an extra interrupt line number dedicated to OTG events. This will
enable OTG interrupts to serve in DWC3 OTG driver.
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 17 Jan 2017 13:36:54 +0000 (14:36 +0100)]
phy: zynqmp: Remove tx_termination_fix detection on silicon v1
Only silicon v1 requires this termination fix. With new nvmem soc
revision nvmem detection driver this can be autodetected at run time and
this flag is not needed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Moritz Fischer [Thu, 22 Dec 2016 17:19:25 +0000 (09:19 -0800)]
ARM64: zynqmp: Fix i2c node's compatible string
The Zynq Ultrascale MP uses version 1.4 of the Cadence IP core
which fixes some silicon bugs that needed software workarounds
in Version 1.0 that was used on Zynq systems.
Signed-off-by: Moritz Fischer <mdf@kernel.org> Cc: Michal Simek <michal.simek@xilinx.com> Cc: Sören Brinkmann <soren.brinkmann@xilinx.com> Cc: Rob Herring <robh+dt@kernel.org> Acked-by: Sören Brinkmann <soren.brinkmann@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 7 Feb 2017 13:32:26 +0000 (14:32 +0100)]
arm64: zynqmp: Check pmufw version
If PMUFW version is not v0.3 then panic.
ZynqMP switch to CCF based clock driver which requires
PMUFW to be present at certain version.
This patch ensure that you use correct and tested PMUFW
binary.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for CCF, this CCF reads the ref clocks
from dt and checks all the required clock control
registers for its source , divisors and calculates
the clock from them. This supports clock and set
functions.
Panic when read/write fails.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The AMS includes an ADC as well as on-chip sensors that can be used to
sample external voltages and monitor on-die operating conditions, such as
temperature and supply voltage levels.
Signed-off-by: Rajnikant Bhojani <rajnikant.bhojani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 6 Feb 2017 13:43:01 +0000 (14:43 +0100)]
arm64: zynqmp: Do not call SMC from SPL
SPL is running before ATF in EL3 that's why SMCs can't be called because
there is nothing to call. zynqmp_mmio*() are doing direct read/write
accesses and this patch does the same.
PMUFW is up and running at this time and there is a way to talk to pmufw
via IPI but there is no reason to implement IPI stuff in SPL if we need
just simple read for getting clock driver to work.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 6 Feb 2017 13:34:01 +0000 (14:34 +0100)]
arm64: zynqmp: Do not perform reset in case of panic
Do not perform reset when panic happens because in the next reset
panic happens again and logs are overflood by the same errors.
This can be enabled by default and reset can be performed via watchdog.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 6 Feb 2017 14:35:38 +0000 (15:35 +0100)]
arm64: zynqmp: Fix SPI layout for SPL
The patch:
"spi_flash: zynqmp: Dont use 4K sector erase by default"
(sha1: 246880b5ef7616c766a195d100b75f2443f9b02f)
breaks SPL code because increased erase sector size which were used
for writing SPL code to QSPI.
Fix u-boot.img position.
mmcinfo
sf probe
load mmc 0 10000000 boot.bin
sf erase 0 +$filesize
sf write 10000000 0 $filesize
load mmc 0 10000000 atf-spi.ub
sf erase 0x80000 +$filesize
sf write 10000000 0x80000 $filesize
load mmc 0 10000000 u-boot.bin
sf erase 0xa0000 +$filesize
sf write 10000000 0xa0000 $filesize
#Fixed location from 0x140000 to 0x170000
load mmc 0 10000000 u-boot.img
sf erase 0x170000 +$filesize
sf write 10000000 0x170000 $filesize
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mmc: Change frequency while accessing to boot partition
Boot partition is not supported in HS200 mode, hence change
clock to high speed while accessing boot partition and
revert back when partition is switching to other than boot
partition
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Deine private structure arasan_sdhci_priv instead of sdhci_host
as private. This allows us in adding more private data as required
for usage in driver.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Make sdhci_ops of host modifiable as ops may contain
platform specific funtion pointers which may need
to be defined for some platforms(example: platform specific
tuning and delays)
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mmc: sdhci: Add support for platform specific delay
Add support for any platform/board specific delays
requirement while setting clocks. Some boards needs
to program tapdelay for setting certain high frequencies
and this patch adds hook for supporting the same.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mmc: sdhci: Add support for platform/board specific tuning
Add support to execute platform/board specific tuning needed
for SDR104 and SDR50 UHS modes.This patch adds hook routine
to support specific tuning requirements.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Add support for all UHS modes of SD3.0.
This patch defines the routines to switch
volatge, setting uhs modes and execute tuning
as these are needed for SD3.0 support
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The SD3.0 needs voltage switching to 1.8V
based on host and cards capabilities and also
needs to switch to one of the uhs modes based
on cards capability. This supports frequencies
till 200MHz. This patch define hooks to perform
the same at sdhci driver level.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch fixes the below warning by typecasting it properly
fs/ubifs/ubifs.c: In function 'ubifs_load':
fs/ubifs/ubifs.c:942:29: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
err = ubifs_read(filename, (void *)addr, 0, size, &actread);
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Fixed the below warnings by typecasting it properly
w+../common/spl/spl_spi.c: In function 'spi_load_image_os':
w+../common/spl/spl_spi.c:41:27: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
w+../common/spl/spl_spi.c: In function 'spl_spi_load_image':
w+../common/spl/spl_spi.c:121:11: warning: cast to pointer from integer
of different size [-Wint-to-pointer-cast]
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: zynq_gem: Dont enable SGMII and PCS selection
Dont enable SGMII and PCS selection if internal PCS/PMA
is not used, by getting the info about internal/external
PCS/PMA usage from dt property "is-internal-phy".
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynqmp_qspi: Add support x1 and x2 qspi modes
This patch adds support for x1 and x2 qspi modes which
means to support rx and tx on 2 lines and single line
respectively by reading tx and rx bus widths from
device tree. Read is-dual for determining dual
parallel/single mode.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support for x1 and x2 qspi modes which
means to support rx and tx on 2 lines and single line
respectively by reading tx and rx bus widths from
device tree. Read is-dual for determining dual
parallel/single mode.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: spi_flash: Add support for read if offset is odd
Add support ot read from flash if offset received is odd
incase of dual parallel. This fixes the issue of spi flash
read failures if received offset is odd
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi_flash: zynqmp: Dont use 4K sector erase by default
Dont use 4K sector erase by default, Disabling this
would use 64K sector erase and decreases erase time.
Also disabled by the fact that UBIFS and JFFS2 won't work
with 4K sector erase.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Rename command ls to fsls as its conflicting with
generic file systesm command ls and this is causing
compilation failure as below, if both are enabled
and this patch fixes it.
cmd/jffs2.o:(.u_boot_list_2_cmd_2_ls+0x0):
multiple definition of `_u_boot_list_2_cmd_2_ls'
cmd/fs.o:(.u_boot_list_2_cmd_2_ls+0x0):first defined here
scripts/Makefile.build:359: recipe for target 'cmd/built-in.o'
failed
make[1]: *** [cmd/built-in.o] Error 1
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynqmp_qspi: Use default baudrate value instead of max value
Use default baudrate value instead of max baudrate value as
using max baudrate value causing the issues on some QSPI parts
(Spansion, Macronix etc) as frequency goes down below 1MHz.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Alison Wang [Tue, 17 Jan 2017 01:39:17 +0000 (09:39 +0800)]
armv8: aarch64: Fix the warning about x1-x3 nonzero issue
For 64-bit kernel, there is a warning about x1-x3 nonzero in violation
of boot protocol. To fix this issue, input argument 4 is added for
armv8_switch_to_el2 and armv8_switch_to_el1. The input argument 4 will
be set to the right value, such as zero.
Signed-off-by: Alison Wang <alison.wang@nxp.com> Reviewed-by: Alexander Graf <agraf@suse.de> Tested-by: Ryan Harkin <ryan.harkin@linaro.org> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 16 Jan 2017 11:57:19 +0000 (12:57 +0100)]
spl: Add missing line ending to SPL print
One print requires line ending to be aligned with SW running
after it. Prints look weird without it.
For example:
U-Boot SPL 2017.01-01801-g1fb1292c7b9d (Jan 16 2017 - 12:50:53)
EL Level: EL3
Trying to boot from SPINOTICE: ATF running on XCZU15EG/silicon
v2/RTL5.1 at 0xfffe5000, with PMU firmware
NOTICE: BL31: Secure code at 0x0
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 2 Jan 2017 08:40:09 +0000 (09:40 +0100)]
scsi: dm: Unbind all scsi based block devices before new scan
New scan should unbind all block devices not to be listed again.
Without this patch if scsi reset or scan is called new block devices are
created which point to the same id and lun.
For example:
ZynqMP> scsi scan
scsi_scan: if_type=2, devnum=0: sdhci@ff170000.blk, 6, 0
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 0
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 1
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 2
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 3
scsi_scan: if_type=2, devnum=0: ahci@fd0c0000.id1lun0, 2, 4
scanning bus for devices...
Device 0: (1:0) Vendor: ATA Prod.: KINGSTON SVP200S Rev: 501A
Type: Hard Disk
Capacity: 57241.8 MB = 55.9 GB (117231408 x 512)
Reported-by: Ken Ma <make@marvell.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com> Acked-by: Simon Glass <sjg@chromium.org>
Michal Simek [Mon, 9 Jan 2017 09:05:16 +0000 (10:05 +0100)]
ARM64: zynqmp: Generate handoff structure for ATF
Xilinx ATF extending options for passing images from BL2(FSBL)
to BL31. U-Boot SPL is FSBL replacement that's why it should generate
handoff structure the same. Support only one entry which is U-Boot in
EL2 itself. When FIT image is adopted structure generate should be data
driven.
Currently ATF is placing this structure at the beggining of OCM which is
rewriting early parts of ATF which should be unused at that time.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Kamensky Ivan [Tue, 27 Dec 2016 16:12:23 +0000 (19:12 +0300)]
xilinx_phy: Pass correct pointer to fdtdec_get_int()
This patch fixes incorrect pointer on offset device in device tree blob.
When using with the component "Ethernet 1G/2.5G BASE-X PCS/PMA or SGMII"
it does not understand what type is XAE_PHY_TYPE_1000BASE_X and trying
to change frequency.
Signed-off-by: Kamensky Ivan <kamensky.ivan@mail.ru> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: xilinx_axi_emac: Add support for non processor mode
Add support for non processor mode, this mode doesnt have
access to some of the registers and hence this patch
bypasses it and also length has to be calculated from
status instead of app4 in this mode.
Michal Simek [Tue, 20 Dec 2016 15:26:25 +0000 (16:26 +0100)]
usb: storage: Show number of storage devices detected for DM_USB
By enabling DM_USB information about number of storage devices
was lost.
Get this information back simply by printing number of devices detected
via BLK uclass.
For example:
scanning bus 0 for devices... 7 USB Device(s) found
scanning usb for storage devices... 3 Storage Device(s) found
scanning usb for ethernet devices... 0 Ethernet Device(s) found
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 31 Mar 2016 11:53:58 +0000 (13:53 +0200)]
drivers: usb: Add DWC3 Xilinx ZynqMP glue logic
By enabling BLK by default this is the next driver which needs to get
support for DM_USB. Adding generic DWC3 glue logic which only
parse nodes and read device mode. Based on it probe proper
host/peripheral DWC3 drivers for it.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 21 Dec 2016 12:18:40 +0000 (13:18 +0100)]
drivers: usb: dwc3: add ti dwc3 peripheral driver with driver model support
Add a TI DWC3 peripheral driver with driver model support and the
driver will be bound by the DWC3 wrapper driver based on the
dr_mode device tree entry.
projects / thirdparty / u-boot.git / log
