Simona Vetter [Fri, 31 Oct 2025 17:47:16 +0000 (18:47 +0100)]
Merge tag 'drm-misc-next-2025-10-28' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v6.19-rc1:
UAPI Changes:
Cross-subsystem Changes:
- Update DT bindings for renesas and powervr-rogue.
- Update MAINTAINERS email and add spsc_queue.
Core Changes:
- Allow ttm page protection flags on risc-v.
- Move freeing of drm client memory to driver.
Driver Changes:
- Assorted small fixes and updates to qaic, ivpu, st7571-i2c, gud,
amdxdna.
- Allow configuration of vkms' display through configfs.
- Add Arm Ethos-U65/U85 accel driver.
Simona Vetter [Fri, 31 Oct 2025 17:40:53 +0000 (18:40 +0100)]
Merge tag 'drm-xe-next-2025-10-28' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next
Driver Changes:
More xe3p support (Harish, Brian, Balasubramani, Matt Roper)
Make panic support work on VRAM for display (Maarten)
Fix stolen size check (Shuicheng)
xe_pci_test update (Gustavo)
VF migration updates (Tomasz)
A couple of fixes around allocation and PM references (Matt Brost)
Migration update for the MEM_COPY instruction (Matt Auld)
Initial CRI support (Balasubramani, Matt Roper)
Use SVM range helpers in PT layer (Matt Brost)
Drop MAX_GT_TYPE_CHARS constant (Matt Roper)
Fix spelling and typos (Sanjay)
Fix VF FLR synchronization between all GTs (Michal)
Add a Workaround (Nitin)
Access VF's register using dedicated MMIO view (Michal)
Icenowy Zheng [Mon, 20 Oct 2025 05:35:23 +0000 (13:35 +0800)]
drm/ttm: add pgprot handling for RISC-V
The RISC-V Svpbmt privileged extension provides support for overriding
page memory coherency attributes, and, along with vendor extensions like
Xtheadmae, supports pgprot_{writecombine,noncached} on RISC-V.
Adapt the codepath that maps ttm_write_combined to pgprot_writecombine
and ttm_noncached to pgprot_noncached to RISC-V, to allow proper page
access attributes.
Signed-off-by: Icenowy Zheng <uwu@icenowy.me> Tested-by: Han Gao <rabenda.cn@gmail.com> Acked-by: Christian König <christian.koenig@amd.com> Signed-off-by: Christian König <christian.koenig@amd.com> Link: https://lore.kernel.org/r/20251020053523.731353-1-uwu@icenowy.me
Troy Hanson [Wed, 22 Oct 2025 14:16:06 +0000 (16:16 +0200)]
accel/qaic: Rename constant for clarity
QAIC_MANAGE_EXT_MSG_LENGTH is ambiguous and has been confused with
QAIC_MANAGE_MAX_MSG_LENGTH. Rename it to clarify it's a wire length.
Signed-off-by: Troy Hanson <thanson@qti.qualcomm.com> Signed-off-by: Youssef Samir <youssef.abdulrahman@oss.qualcomm.com> Reviewed-by: Carl Vanderlip <carl.vanderlip@oss.qualcomm.com> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
[jhugo: capitalize subject] Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://patch.msgid.link/20251022141606.3740470-1-youssef.abdulrahman@oss.qualcomm.com
Aswin Venkatesan [Wed, 22 Oct 2025 12:41:07 +0000 (14:41 +0200)]
accel/qaic: Fix comment
Replace the word "Qranium" with "qaic" in the function parameter
description.
Signed-off-by: Aswin Venkatesan <aswivenk@qti.qualcomm.com> Signed-off-by: Youssef Samir <youssef.abdulrahman@oss.qualcomm.com> Reviewed-by: Carl Vanderlip <carl.vanderlip@oss.qualcomm.com> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com>
[jhugo: adjust word wrapping in commit text] Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://patch.msgid.link/20251022124107.3712466-1-youssef.abdulrahman@oss.qualcomm.com
Youssef Samir [Fri, 17 Oct 2025 17:34:32 +0000 (19:34 +0200)]
accel/qaic: Update the sahara image table for AIC200
Update the Sahara image table for the AIC200 to add entries for:
- qupv3fw.elf at id 54
- xbl_config.elf at id 38
- tz_qti_config.mbn at id 76
And move pvs.bin to id 78 to avoid firmware conflict.
Co-developed-by: Zack McKevitt <zmckevit@qti.qualcomm.com> Signed-off-by: Zack McKevitt <zmckevit@qti.qualcomm.com> Co-developed-by: Aswin Venkatesan <aswivenk@qti.qualcomm.com> Signed-off-by: Aswin Venkatesan <aswivenk@qti.qualcomm.com> Signed-off-by: Youssef Samir <quic_yabdulra@quicinc.com> Signed-off-by: Youssef Samir <youssef.abdulrahman@oss.qualcomm.com> Reviewed-by: Karol Wachowski <karol.wachowski@linux.intel.com> Reviewed-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Signed-off-by: Jeff Hugo <jeff.hugo@oss.qualcomm.com> Link: https://patch.msgid.link/20251017173432.1207656-1-youssef.abdulrahman@oss.qualcomm.com
Michal Wajdeczko [Fri, 24 Oct 2025 20:58:25 +0000 (22:58 +0200)]
drm/xe/pf: Access VF's register using dedicated MMIO view
Instead of creating ad-hoc new register definitions with altered
register addresses to mimic the VF's access to these registers,
prepare new MMIO instance per required VF, with shifted internal
location of the register map. This will allow to use unmodified
register definitions in all calls to xe_mmio() functions.
Nitin Gote [Mon, 27 Oct 2025 09:26:43 +0000 (14:56 +0530)]
drm/xe/xe3: Add WA_14024681466 for Xe3_LPG
Apply WA_14024681466 to Xe3_LPG graphics IP versions from 30.00 to 30.05.
v2: (Matthew Roper)
- Remove stepping filter as workaround applies to all steppings.
- Add an engine class filter so it only applies to the RENDER engine.
Michal Wajdeczko [Sat, 25 Oct 2025 12:49:05 +0000 (14:49 +0200)]
drm/xe/pf: Fix VF FLR synchronization between all GTs
If subsequent VF FLR request is triggered when previous VF FLR
sequence is still being processed, we ignore it as not needed.
But in case of the multi-GT platforms, one GT may already finish
its VF FLR processing and will start a new sequence, which includes
new cross-GT synchronization point. However, since other GT may
be still busy with post-sync cleanup steps, this will put on hold
this new FLR sequence, which might never finish due to lack of any
future synchronization checkouts.
Add additional cross-GT FLR synchronization point when each GT
ends processing its own FLR sequence. This should also help to
cover the case when one GT fails FLR processing before reaching
the first synchronization point.
Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6287 Fixes: 2a8fcf7cc950 ("drm/xe/pf: Synchronize VF FLR between all GTs") Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Reviewed-by: Piotr Piórkowski <piotr.piorkowski@intel.com> Link: https://patch.msgid.link/20251025124906.5264-1-michal.wajdeczko@intel.com
Sanjay Yadav [Thu, 23 Oct 2025 12:14:54 +0000 (17:44 +0530)]
drm/xe: Fix spelling and typos across Xe driver files
Corrected various spelling mistakes and typos in multiple
files under the Xe directory. These fixes improve clarity
and maintain consistency in documentation.
v2
- Replaced all instances of "XE" with "Xe" where it referred
to the driver name
- of -> for
- Typical -> Typically
v3
- Revert "Xe" to "XE" for macro prefix reference
Philipp Stanner [Fri, 24 Oct 2025 08:15:00 +0000 (10:15 +0200)]
MAINTAINERS: Maintain spsc_queue through drm_sched
Back in the day a specialized lockless queue was designed solely for the
DRM GPU Scheduler: spsc_queue. This queue's only user is drm_sched, and
there is no dedicated maintainer entry for the queue.
Add the spsc_queue header to the DRM GPU Scheduler MAINTAINERS' section.
Matt Roper [Fri, 24 Oct 2025 20:08:35 +0000 (13:08 -0700)]
drm/xe/configfs: Drop MAX_GT_TYPE_CHARS constant
Early revisions of commit 7abd69278bb5 ("drm/xe/configfs: Add attribute
to disable GT types") used MAX_GT_TYPE_CHARS not only to size the
constant name field, but also for some of the string matching logic. By
the time the patch finally landed, the constant was no longer needed for
parsing. Stop using it for the string field definition as well; this
eliminates the risk that we forget to update the constant if we ever add
a GT type name longer than seven characters.
Add a driver for Arm Ethos-U65/U85 NPUs. The Ethos-U NPU has a
relatively simple interface with single command stream to describe
buffers, operation settings, and network operations. It supports up to 8
memory regions (though no h/w bounds on a region). The Ethos NPUs
are designed to use an SRAM for scratch memory. Region 2 is reserved
for SRAM (like the downstream driver stack and compiler). Userspace
doesn't need access to the SRAM.
The h/w has no MMU nor external IOMMU and is a DMA engine which can
read and write anywhere in memory without h/w bounds checks. The user
submitted command streams must be validated against the bounds of the
GEM BOs. This is similar to the VC4 design which validates shaders.
The job submit is based on the rocket driver for the Rockchip NPU
utilizing the GPU scheduler. It is simpler as there's only 1 core rather
than 3.
Tested on i.MX93 platform (U65) and FVP (U85) with Mesa Teflon
support.
Add a binding schema for Arm Ethos-U65/U85 NPU. The Arm Ethos-U NPUs are
designed for edge AI inference applications.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Acked-by: Tomeu Vizoso <tomeu@tomeuvizoso.net> Link: https://patch.msgid.link/20251020-ethos-v6-1-ecebc383c4b7@kernel.org Signed-off-by: Rob Herring (Arm) <robh@kernel.org>
Lizhi Hou [Fri, 24 Oct 2025 16:55:03 +0000 (09:55 -0700)]
accel/amdxdna: Fix uninitialized return value
In aie2_get_hwctx_status() and aie2_query_ctx_status_array(), the
functions could return an uninitialized value in some cases. Update them
to always return 0. The amount of valid results is indicated by the
returned buffer_size, element_size, and num_element fields.
Lizhi Hou [Fri, 24 Oct 2025 16:26:08 +0000 (09:26 -0700)]
accel/amdxdna: Fix incorrect return value in aie2_hwctx_sync_debug_bo()
When the driver issues the SYNC_DEBUG_BO command, it currently returns 0
even if the firmware fails to execute the command. Update the driver to
return -EINVAL in this case to properly indicate the failure.
Reported-by: Dan Carpenter <dan.carpenter@linaro.org> Closes: https://lore.kernel.org/dri-devel/aPsadTBXunUSBByV@stanley.mountain/ Fixes: 7ea046838021 ("accel/amdxdna: Support firmware debug buffer") Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Lizhi Hou <lizhi.hou@amd.com> Link: https://patch.msgid.link/20251024162608.1544842-1-lizhi.hou@amd.com
atomic:
- Clean up and improve state-handling interfaces, update drivers
bridge:
- Improve ref counting
buddy:
- Optimize block management
Driver Changes:
amdxdna:
- Fix runtime power management
- Support firmware debug output
ast:
- Set quirks for each chip model
atmel-hlcdc:
- Set LCDC_ATTRE register in plane disable
- Set correct values for plane scaler
bochs:
- Use vblank timer
bridge:
- synopsis: Support CEC; Init timer with correct frequency
cirrus-qemu:
- Use vblank timer
imx:
- Clean up
ivu:
- Update JSM API to 3.33.0
- Reset engine on more job errors
- Return correct error codes for jobs
komeda:
- Use drm_ logging functions
panel:
- edp: Support AUO B116XAN02.0
panfrost:
- Embed struct drm_driver in Panfrost device
- Improve error handling
- Clean up job handling
panthor:
- Support custom ASN_HASH for mt8196
renesas:
- rz-du: Fix dependencies
rockchip:
- dsi: Add support for RK3368
- Fix LUT size for RK3386
sitronix:
- Fix output position when clearing screens
qaic:
- Support dma-buf exports
- Support new firmware's READ_DATA implementation
- Replace kcalloc with memdup
- Replace snprintf() with sysfs_emit()
- Avoid overflows in arithmetics
- Clean up
- Fixes
Make no assumption on the allocation of the client's memory. For
example, amdgpu stores a client within another data structures,
where it cannot be freed by itself.
The correct place to free the client's memory is the client's free
callback. All existing clients implement this.
Free the client memory in the client free callback. Also move the
debugging output into the free callback: drm_client_release() puts
the reference on the DRM device, so pointers to the device should
be considered dangling afterwards.
drm/log: Do not hold lock across drm_client_release()
When calling drm_client_release(), the client is already quiescent.
Internal locks should therefore be dropped before the caller releases
the client.
In the case of the DRM log, concurrency originates from the console or
from client events. The console has been unregistered in the previous
line. The caller of the unregister callback, drm_log_client_unregister(),
holds clientlist_mutex from struct drm_device to protect against concurrent
client events. It is therefore safe to release the client without holding
locks.
drm/client: Add client free callback to unprepare fb_helper
Add free callback to struct drm_client_funcs. Invoke function to
free the client memory as part of the release process. Implement
free for fbdev emulation.
Fbdev emulation allocates and prepares client memory in
drm_fbdev_client_setup(). The release happens in fb_destroy from
struct fb_ops. Multiple implementations of this callback exist in
the various drivers that provide an fbdev implementation. Each of
them needs to follow the implementation details of the fbdev setup
code.
Adding a free callback for the client puts the unprepare and release
of the fbdev client in a single place.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> # core, msm Acked-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> # omapdrm Acked-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> # gma500 Acked-by: Alex Deucher <alexander.deucher@amd.com> Link: https://lore.kernel.org/r/20251009132006.45834-2-tzimmermann@suse.de
Matt Roper [Tue, 21 Oct 2025 22:45:56 +0000 (15:45 -0700)]
drm/xe/xe3p_xpc: Add MCR steering for NODE and L3BANK ranges
The bspec was originally missing the information related to steering of
L3-related ranges. Now that a late-breaking spec update has added the
necessary information, implement the steering rules in the code. Note
that the sole L3BANK range is the same as the one used on Xe_LPG, so we
can re-use the existing table for that MCR type.
Matt Roper [Tue, 21 Oct 2025 22:45:55 +0000 (15:45 -0700)]
drm/xe/xe3p_xpc: Treat all PSMI MCR ranges as "INSTANCE0"
Early versions of the B-spec originally indicated that Xe3p_XPC had two
ranges of PSMI registers requiring MCR steering (one starting at 0xB500,
one starting at 0xB600), and that reads of registers in these ranges
required different grpid values to ensure that a non-terminated value is
obtained. A late-breaking spec update has simplified this; both ranges
can be safely steered to grpid=0 for reads.
Drop the "PSMI19" replication type and related code, and consolidate
both register ranges into a single entry in the "INSTANCE0" steering
table.
Maciej Falkowski [Wed, 22 Oct 2025 10:53:48 +0000 (12:53 +0200)]
accel/ivpu: Add support for Nova Lake's NPU
Add support for NPU6 generation that will be present on Nova Lake CPUs.
As with previous generations, it maintains compatibility
so no bigger functional changes apart from removing
deprecated call to soc_cpu_drive() function.
Quiescing TOP_MMIO in SOC_CPU_NOC as part of boot procedure is no longer
needed starting from 60XX. Remove soc_cpu_drive() call from NPU6 onward.
The VPU_CPU_NOC_QREQN, VPU_CPU_NOC_QACCEPTN, and VPU_CPU_NOC_QDENY
registers are deprecated and non-functional on 60XX. They will be
removed in future generations.
Add platform definition and PCI IDs for Crescent Island.
Other platforms use INTEL_VGA_DEVICE since they have a
PCI_BASE_CLASS_DISPLAY class. This is not the case for CRI, so just
match on devid, which should be sufficient.
Signed-off-by: Balasubramani Vivekanandan <balasubramani.vivekanandan@intel.com> Reviewed-by: Shekhar Chauhan <shekhar.chauhan@intel.com> Link: https://lore.kernel.org/r/20251021-cri-v1-1-bf11e61d9f49@intel.com Signed-off-by: Lucas De Marchi <lucas.demarchi@intel.com>
Matthew Auld [Wed, 22 Oct 2025 16:38:35 +0000 (17:38 +0100)]
drm/xe/migrate: support MEM_COPY instruction
Make this the default on xe2+ when doing a copy. This has a few
advantages over the exiting copy instruction:
1) It has a special PAGE_COPY mode that claims to be optimised for
page-in/page-out, which is the vast majority of current users.
2) It also has a simple BYTE_COPY mode that supports byte granularity
copying without any restrictions.
With 2) we can now easily skip the bounce buffer flow when copying
buffers with strange sizing/alignment, like for memory_access. But that
is left for the next patch.
v2 (Matt Brost):
- Use device info to check whether device should use the MEM_COPY
path. This should fit better with making this a configfs tunable.
- And with that also keep old path still functional on xe2 for possible
experimentation.
- Add a define for PAGE_COPY page-size.
v3 (Matt Brost):
- Fallback to an actual linear copy for pitch=1.
- Also update NVL.
Matthew Auld [Wed, 22 Oct 2025 16:38:34 +0000 (17:38 +0100)]
drm/xe/migrate: trim batch buffer sizing
We have an extra two dwords, but it looks like we should only need one
for the extra bb_end. Likely this is just leftover from back when the
arb handling was moved into the ring programming.
Matthew Auld [Wed, 22 Oct 2025 16:38:33 +0000 (17:38 +0100)]
drm/xe/migrate: fix batch buffer sizing
In xe_migrate_vram() the copy can straddle page boundaries, so the len
might look like a single page, but actually accounting for the offset
within the page we will need to emit more than one PTE. Otherwise in
some cases the batch buffer will be undersized leading to warnings
later. We already have npages so use that instead.
Matthew Auld [Wed, 22 Oct 2025 16:38:32 +0000 (17:38 +0100)]
drm/xe/migrate: fix chunk handling for 2M page emit
On systems with PAGE_SIZE > 4K the chunk will likely be rounded down to
zero, if say we have single 2M page, so one huge pte, since we also try
to align the chunk to PAGE_SIZE / XE_PAGE_SIZE, which will be 16 on 64K
systems. Make the ALIGN_DOWN conditional for 4K PTEs where we can
encounter gpu_page_size < PAGE_SIZE.
Matthew Auld [Wed, 22 Oct 2025 16:38:31 +0000 (17:38 +0100)]
drm/xe/migrate: rework size restrictions for sram pte emit
We allow the input size to not be aligned to PAGE_SIZE, which leads to
various bugs in build_pt_update_batch_sram() for PAGE_SIZE > 4K systems.
For example if ptes is exactly one gpu_page_size then the chunk size is
rounded down to zero. The simplest fix looks to be forcing PAGE_SIZE
aligned inputs.
Matthew Auld [Wed, 22 Oct 2025 16:38:30 +0000 (17:38 +0100)]
drm/xe/migrate: fix offset and len check
Restriction here is pitch of 4bytes to match pixel width (32b), and hw
restriction where src and dst must be aligned to 64bytes. If any of that
is not possible then we need a bounce buffer.
Retrieve the CRTC's new state with drm_atomic_get_new_crtc_state()
in drm_sysfb_plane_helper_begin_fb_access(). The blit function might
be incorrect otherwise.
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Fixes: cb71de092553 ("drm/sysfb: Lookup blit function during atomic check") Reported-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Closes: https://lore.kernel.org/dri-devel/aPJrs7_u8KcalNsC@intel.com/ Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Javier Martinez Canillas <javierm@redhat.com> Cc: dri-devel@lists.freedesktop.org Reviewed-by: Javier Martinez Canillas <javierm@redhat.com> Link: https://lore.kernel.org/r/20251020125227.41308-1-tzimmermann@suse.de
Matthew Brost [Wed, 22 Oct 2025 00:55:38 +0000 (17:55 -0700)]
drm/xe: Avoid PM wake reference during VF migration
Virtual Functions (VFs) do not use runtime PM. Avoid taking PM
references during VF migration, as lockdep may get confused—VF migration
occurs in the reclaim path, and waking a PM reference can trigger memory
allocation warnings.
Matthew Brost [Wed, 22 Oct 2025 00:55:37 +0000 (17:55 -0700)]
drm/xe: Do not wake device during a GT reset
Waking the device during a GT reset can lead to unintended memory
allocation, which is not allowed since GT resets occur in the reclaim
path. Prevent this by holding a PM reference while a reset is in flight.
Tomasz Lis [Tue, 21 Oct 2025 22:48:17 +0000 (00:48 +0200)]
drm/xe/vf: Do not disable VF migration on ATS-M
Our current support for the VF migration depends on the availability
of the MEMIRQ rather than specific graphics version 20.
Relax our early migration support checks to allow also use some older
platforms like ATS-M for experiments and testing.
Do not allow ADL, as supporting VF migration through MMIO interrupts
would require additional changes in order to achieve reliability.
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://lore.kernel.org/r/20251021224817.1593817-5-tomasz.lis@intel.com
Tomasz Lis [Tue, 21 Oct 2025 22:48:16 +0000 (00:48 +0200)]
drm/xe: Assert that VF will never use fixed placement of BOs
Most BOs do not care at which offset they will be accessed within
GGTT or PPGTT. The few which do care, should be only created
on PF, and mapped within GGTT. On VFs, mapping at fixed offset
is prohibited, as each VF is granted access to a range of
GGTT address space.
Since fixed addresses of GGTT mapping can only be used on PF,
add an assert which makes sure no attempt of fixed placement
will happen for a driver probed on a VF.
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://lore.kernel.org/r/20251021224817.1593817-4-tomasz.lis@intel.com
Tomasz Lis [Tue, 21 Oct 2025 22:48:14 +0000 (00:48 +0200)]
drm/xe/vf: Revert logic of vf.migration.enabled
Convert `enabled` property into `disabled`.
Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Tomasz Lis <tomasz.lis@intel.com> Suggested-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://lore.kernel.org/r/20251021224817.1593817-2-tomasz.lis@intel.com
Gustavo Sousa [Mon, 20 Oct 2025 23:45:57 +0000 (20:45 -0300)]
drm/xe/tests/pci: Check dma_mask_size, va_bits and vm_max_level
Members dma_mask_size, va_bits and vm_max_level of struct xe_device_desc
are all expected to be non-zero. Add checks for that in
check_platform_desc().
Gustavo Sousa [Mon, 20 Oct 2025 23:45:56 +0000 (20:45 -0300)]
drm/xe/tests/pci: Convert GT count check to general device check
We already have check_graphics_ip() and check_media_ip() as general
functions to check the IP descriptors. The check in
check_platform_gt_count() is simple enough such that we can convert the
function to a more general device check. In an upcoming change, we will
also add some checks for other members of struct xe_device_desc. As
such, rename check_platform_gt_count() to check_platform_desc().
While at it, use inline (unsigned int) casting of max_gt_per_tile to
keep checks for each member localized; and use KUNIT_EXPECT_*() variants
of the macros to allow multiple issues to be reported.
José Expósito [Thu, 16 Oct 2025 17:56:14 +0000 (19:56 +0200)]
drm/vkms: Allow to configure the default device creation
Add a new module param to allow to create or not the default VKMS
instance. Useful when combined with configfs to avoid having additional
VKMS instances.
Tested-by: Mark Yacoub <markyacoub@google.com> Reviewed-by: Louis Chauvet <louis.chauvet@bootlin.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: José Expósito <jose.exposito89@gmail.com> Link: https://lore.kernel.org/r/20251016175618.10051-13-jose.exposito89@gmail.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
Louis Chauvet [Thu, 16 Oct 2025 17:56:13 +0000 (19:56 +0200)]
drm/vkms: Allow to attach connectors and encoders via configfs
Create a default subgroup at
/config/vkms/connectors/connector/possible_encoders that will contain
symbolic links to the possible encoders for the connector.
Tested-by: Mark Yacoub <markyacoub@google.com> Reviewed-by: Louis Chauvet <louis.chauvet@bootlin.com> Reviewed-by: Harry Wentland <harry.wentland@amd.com> Reviewed-by: Luca Ceresoli <luca.ceresoli@bootlin.com> Signed-off-by: Louis Chauvet <louis.chauvet@bootlin.com> Co-developed-by: José Expósito <jose.exposito89@gmail.com> Signed-off-by: José Expósito <jose.exposito89@gmail.com> Link: https://lore.kernel.org/r/20251016175618.10051-12-jose.exposito89@gmail.com Signed-off-by: Luca Ceresoli <luca.ceresoli@bootlin.com>
This controller can have both bridges and panels connected to it. In
order to describe panels properly in DT, pull in dsi-controller.yaml
and disallow only unevaluatedProperties, because the panel node is
optional. Include example binding with panel.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Reviewed-by: Tomi Valkeinen <tomi.valkeinen+renesas@ideasonboard.com> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ideasonboard.com> Link: https://lore.kernel.org/r/20250904210147.186728-4-marek.vasut+renesas@mailbox.org
Shuicheng Lin [Thu, 16 Oct 2025 22:55:07 +0000 (22:55 +0000)]
drm/xe: Fix stolen size check to allow equal WOPCM size
On some platforms without dedicated stolen memory, the calculated
stolen size may be exactly equal to the WOPCM size. The current
assertion incorrectly requires it to be strictly greater, causing
a false failure. Relax the check to allow equality.
Fixes: 65369b8e2961 ("drm/xe: Change return type of detect_bar2_dgfx() from s64 to u64") Closes: https://gitlab.freedesktop.org/drm/xe/kernel/-/issues/6359 Cc: Matthew Auld <matthew.auld@intel.com> Cc: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Shuicheng Lin <shuicheng.lin@intel.com> Reviewed-by: Matthew Auld <matthew.auld@intel.com> Link: https://lore.kernel.org/r/20251016225506.2256127-2-shuicheng.lin@intel.com Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com>
Marek Vasut [Sat, 18 Oct 2025 13:00:59 +0000 (15:00 +0200)]
dt-bindings: gpu: img,powervr-rogue: Rework the allOf section
Rework the current allOf: section such that all handling of
clocks/clock-names properties happens first, and all handling
of power-domains/power-domain-names happens second.
This allows the allOf section to limit various GPU models to
matching clocks count in the first half, and apply the same
for power-domains count in the second half, without conflating
the two limits together.
This makes addition of GPU models with different clocks and
power-domains count easier. No functional change intended.
Simona Vetter [Tue, 21 Oct 2025 08:16:34 +0000 (10:16 +0200)]
Merge tag 'drm-misc-next-2025-10-02' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v6.19:
UAPI Changes:
Cross-subsystem Changes:
- fbcon cleanups.
- Make drivers depend on FB_TILEBLITTING instead of selecting it,
and hide FB_MODE_HELPERS.
Core Changes:
- More preparations for rust.
- Throttle dirty worker with vblank
- Use drm_for_each_bridge_in_chain_scoped in drm's bridge code and
assorted fixes.
- Ensure drm_client_modeset tests are enabled in UML.
- Rename ttm_bo_put to ttm_bo_fini, as a further step in removing the
TTM bo refcount.
- Add POST_LT_ADJ_REQ training sequence.
- Show list of removed but still allocated bridges.
- Add a simulated vblank interrupt for hardware without it,
and add some helpers to use them in vkms and hypervdrm.
Driver Changes:
- Assorted small fixes, cleanups and updates to host1x, tegra,
panthor, amdxdna, gud, vc4, ssd130x, ivpu, panfrost, panthor,
sysfb, bridge/sn65dsi86, solomon, ast, tidss.
- Convert drivers from using .round_rate() to .determine_rate()
- Add support for KD116N3730A07/A12, chromebook mt8189, JT101TM023,
LQ079L1SX01, raspberrypi 5" panels.
- Improve reclocking on tegra186+ with nouveau.
- Improve runtime pm in amdxdna.
- Add support for HTX_PAI in imx.
- Use a helper to calculate dumb buffer sizes in most drivers.
Dave Airlie [Tue, 21 Oct 2025 01:09:37 +0000 (11:09 +1000)]
Merge tag 'drm-xe-next-2025-10-20' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next
Highlights:
UAPI Changes:
Loosen used tracking restriction (Matthew Auld)
New SR-IOV debugfs structure and debugfs updates (Michal Wajdeczko)
Hide the GPU madvise flag behind a VM_BIND flag (Thomas Hellström)
Always expose VRAM provisioning data on discrete GPUs (Lukasz Laguna)
Cross-subsystem Changes:
Allow VRAM mappings for userptr when used with SVM (Matthew Brost)
Driver Changes:
Allow pinning of p2p dma-buf (Thomas Hellstrom)
Use per-tile debugfs where appropriate (Michal Wajdeczko)
Add documentation for Execution Queues (Niranjana Vishwanathapura)
PF improvements (Michal Wajdeczko)
VF migration recovery redesign work (Matthew Brost)
User / Kernel VRAM partitioning (Piotr Piórkowski)
Update Tile-based messages (Michal Wajdeczko)
Allow configfs to disable specific GT types (Matt Roper)
VF provisioning improvements (Michal Wajdeczko)
Initial Xe3P support (Various people)
drm/xe/xe3p_lpm: Add special check in Media GT for Main GAMCTRL
For Xe3p arch some subunits of an IP may be different. The GMD_ID
register returns the Xe3p arch and dedicates the reserved field to mark
possible subunit differences. Generally this is an under-the-hood
implementation detail that drivers don't need to worry about, but the
new Main_GAMCTRL may be enabled or not depending on those.
Those reserved bits are described for Xe3p as: "If Zero, No special case
to be handled. If Non-Zero, special case to be handled by Software
agent.". That special case is defined per Arch. So if media version is
35, also check the additional reserved bits. To avoid confusion with the
usual meaning of "reserved", define them as GMD_ID_SUBIP_FLAG_MASK.
Starting from Xe3p, there are two different copies of some of the GAM
registers: the traditional MCR variant at their old locations, and a
new unicast copy known as "main_gamctrl." The Xe driver doesn't use
these registers directly, but we need to instruct the GuC on which set
it should use. Since the new, unicast registers are preferred (since
they avoid the need for unnecessary MCR synchronization), set a new GuC
feature flag, GUC_CTL_MAIN_GAMCTRL_QUEUES to convey this decision. A
new helper function, xe_guc_using_main_gamctrl_queues(), is added for
use in the 3 independent places that need to handle configuration of the
new reporting queues.
The mmio write to enable the main gamctl is only done during the general
GuC upload. The gamctrl registers are not accessed by the GuC during
hwconfig load.
Last, the ADS blob for communicating the queue addresses contains both a
DPA and GGTT offset. The GuC documentation states that DPA is now MBZ
when using the MAIN_GAMCTRL queues.
Ellen Pan [Wed, 8 Oct 2025 20:36:50 +0000 (15:36 -0500)]
drm/amdgpu: Add logic for VF data exchange region to init from dynamic crit_region offsets
1. Added VF logic to init data exchange region using the offsets from dynamic(v2) critical regions;
Signed-off-by: Ellen Pan <yunru.pan@amd.com> Acked-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ellen Pan [Tue, 7 Oct 2025 16:12:39 +0000 (11:12 -0500)]
drm/amdgpu: Add logic for VF ipd and VF bios to init from dynamic crit_region offsets
1. Added VF logic in amdgpu_virt to init IP discovery using the offsets from dynamic(v2) critical regions;
2. Added VF logic in amdgpu_virt to init bios image using the offsets from dynamic(v2) critical regions;
Signed-off-by: Ellen Pan <yunru.pan@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ellen Pan [Wed, 8 Oct 2025 20:01:10 +0000 (15:01 -0500)]
drm/amdgpu: Reuse fw_vram_usage_* for dynamic critical region in SRIOV
- During guest driver init, asa VFs receive PF msg to
init dynamic critical region(v2), VFs reuse fw_vram_usage_*
from ttm to store critical region tables in a 5MB chunk.
Signed-off-by: Ellen Pan <yunru.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ellen Pan [Tue, 7 Oct 2025 16:00:16 +0000 (11:00 -0500)]
drm/amdgpu: Introduce SRIOV critical regions v2 during VF init
1. Introduced amdgpu_virt_init_critical_region during VF init.
- VFs use init_data_header_offset and init_data_header_size_kb
transmitted via PF2VF mailbox to fetch the offset of
critical regions' offsets/sizes in VRAM and save to
adev->virt.crit_region_offsets and adev->virt.crit_region_sizes_kb.
Signed-off-by: Ellen Pan <yunru.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ellen Pan [Tue, 7 Oct 2025 14:46:16 +0000 (09:46 -0500)]
drm/amdgpu: Add SRIOV crit_region_version support
1. Added enum amd_sriov_crit_region_version to support multi versions
2. Added logic in SRIOV mailbox to regonize crit_region version during
req_gpu_init_data
Signed-off-by: Ellen Pan <yunru.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Ellen Pan [Mon, 6 Oct 2025 20:47:45 +0000 (15:47 -0500)]
drm/amdgpu: Updated naming of SRIOV critical region offsets/sizes with _V1 suffix
- This change prepares the later patches to intro _v2 suffix to SRIOV critical regions
Signed-off-by: Ellen Pan <yunru.pan@amd.com> Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
YiPeng Chai [Fri, 17 Oct 2025 07:27:56 +0000 (15:27 +0800)]
drm/amd/ras: Update function and remove redundant code
Update function and remove redundant code:
1. Update function to prepare for internal use.
2. Remove unused function code previously prepared
for ioctl.
V2:
Update commit message content.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/ras: Update ras command context structure name
According to the actual usage of this structure,
it is more appropriate to call it context, the
structure name with ioctl is easy to cause
misunderstanding.
V2:
Update commit message content.
Signed-off-by: YiPeng Chai <YiPeng.Chai@amd.com> Reviewed-by: Tao Zhou <tao.zhou1@amd.com> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Taimur Hassan [Sat, 11 Oct 2025 00:21:13 +0000 (19:21 -0500)]
drm/amd/display: Promote DC to 3.2.355
This version brings along following update:
-Fix GFP_ATOMIC abuse
-Fix several checkpatch issues
-Set DCN32 to use update planes and stream version 3
-Write segment pointer with mot enabled for MST
-Control BW allocation in FW side
-Change clean dsc blocks condition in accelerated mode
-Check disable_fec flag before enabling FEC
Acked-by: Wayne Lin <wayne.lin@amd.com> Signed-off-by: Taimur Hassan <Syed.Hassan@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Lewis Huang [Tue, 7 Oct 2025 08:46:59 +0000 (16:46 +0800)]
drm/amd/display: Change clean dsc blocks condition in accelerated mode
[Why]
On system resume from S4 with the lid closed,
DSC was not cleared because DPMS was already off.
[How]
In accelerated mode, to clean up DSC blocks if eDP dpms off is true
to align the DSC and dpms state when we are not in fast boot and
seamless boot.
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Lewis Huang <Lewis.Huang@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Set DCN32 to use update planes and stream version 3
[Why]
Old minimal transition does not always wait for updates to complete
before proceeding, which can lead to corruption in multi display
scenarios for DCN32.
[How]
Set DCN32 to use update_planes_and_stream_v3 for better pipe transition
handling.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: Nicholas Carbones <Nicholas.Carbones@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Check disable_fec flag before enabling fec.
[Why]
dc debug option disable_fec was not working.
[How]
Check dc debug option disable_fec flag before
enabling fec in dp_should_enable_fec().
Reviewed-by: Wenjing Liu <wenjing.liu@amd.com> Signed-off-by: Meenakshikumar Somasundaram <meenakshikumar.somasundaram@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
There is a lot GFP_ATOMIC allocations which are not in interrupt
context. Change them to use GFP_KERNEL instead.
Reviewed-by: Leo Li <sunpeng.li@amd.com> Signed-off-by: Aurabindo Pillai <aurabindo.pillai@amd.com> Signed-off-by: Tom Chung <chiahsuan.chung@amd.com> Tested-by: Daniel Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Tiezhu Yang [Thu, 16 Oct 2025 06:51:17 +0000 (14:51 +0800)]
drm/amd: Fix set but not used warnings
There are many set but not used warnings under drivers/gpu/drm/amd when
compiling with the latest upstream mainline GCC:
drivers/gpu/drm/amd/amdgpu/amdgpu_gart.c:305:18: warning: variable ‘p’ set but not used [-Wunused-but-set-variable=]
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h:103:26: warning: variable ‘internal_reg_offset’ set but not used [-Wunused-but-set-variable=]
...
drivers/gpu/drm/amd/amdgpu/amdgpu_vcn.h:164:26: warning: variable ‘internal_reg_offset’ set but not used [-Wunused-but-set-variable=]
...
drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:445:13: warning: variable ‘pipe_idx’ set but not used [-Wunused-but-set-variable=]
drivers/gpu/drm/amd/amdgpu/../display/dc/dc_dmub_srv.c:875:21: warning: variable ‘pipe_idx’ set but not used [-Wunused-but-set-variable=]
Remove the variables actually not used or add __maybe_unused attribute for
the variables actually used to fix them, compile tested only.
Signed-off-by: Tiezhu Yang <yangtiezhu@loongson.cn> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
projects / thirdparty / kernel / linux.git / log
