Renjiang Han [Tue, 26 Aug 2025 10:53:38 +0000 (16:23 +0530)]
arm64: dts: qcom: sm6150: add venus node to devicetree
Add the venus node to the devicetree for the sm6150 platform to enable
video functionality. The sm6150 platform currently lacks video
functionality due to the absence of the venus node. Fallback to sc7180 due
to the same video core.
Unfortunately, the rfkill pin is triggered by default, so a workaround
is needed to convince the Linux driver to enable the hw, after which it
works just fine.
Add the sound card for monaco-evk board and verified playback
functionality using the max98357a I2S speaker amplifier and I2S
microphones. The max98357a speaker amplifier is connected via
High-Speed MI2S HS0 interface, while the microphones utilize the
Secondary MI2S interface and also enable required pin controller
gpios for audio.
Monaco EVK is a single board computer, based on the Qualcomm
QCS8300 SoC, with the following features :
- Storage: 1 × 128 GB UFS, micro-SD card, EEPROMs for MACs,
and eMMC.
- Audio/Video, Camera & Display ports.
- Connectivity: RJ45 2.5GbE, WLAN/Bluetooth, CAN/CAN-FD.
- PCIe ports.
- USB & UART ports.
On top of Monaco EVK board additional mezzanine boards can be
stacked in future.
Add support for the following components :
- GPI (Generic Peripheral Interface) and QUPv3-0/1
controllers to facilitate DMA and peripheral communication.
- TCA9534 I/O expander via I2C to provide 8 additional GPIO
lines for extended I/O functionality.
- USB1 controller in device mode to support USB peripheral
operations. USB OTG mode will be enabled for USB1 controller
once the VBUS control based on ID pin is implemented in
hd3ss3220.c.
- Remoteproc subsystems for supported DSPs such as Audio DSP,
Compute DSP and Generic DSP, along with their corresponding
firmware.
- Configure nvmem-layout on the I2C EEPROM to store data for Ethernet
and other consumers.
- QCA8081 2.5G Ethernet PHY on port-0 and expose the
Ethernet MAC address via nvmem for network configuration.
It depends on CONFIG_QCA808X_PHY to use QCA8081 PHY.
- Support for the Iris video codec.
Written with inputs from :
Rakesh Kota <rakesh.kota@oss.qualcomm.com> - Regulators.
Nirmesh Kumar Singh <nirmesh.Singh@oss.qualcomm.com> - GPIO expander.
Viken Dadhaniya <viken.dadhaniya@oss.qualcomm.com> - GPI/QUP.
Mohd Ayaan Anwar <quic_mohdayaa@quicinc.com> - Ethernet.
Monish Chunara <quic_mchunara@quicinc.com> - EEPROM.
Vikash Garodia <quic_vgarodia@quicinc.com> - Iris Video codec.
Swati Agarwal <swati.agarwal@oss.qualcomm.com> - USB.
Enable LPASS macros (WSA, VA, RX, TX) and the lpass_tlmm clock required
for audioreach functionality. In audioreach solution mclk, npl, and fsgen
clocks are managed via the Q6PRM. On SC7280-based boards, the TX CORE
clock is used to drive both RX and WSA audio paths following as per
hardware design.
arm64: dts: qcom: qcs6490-audioreach: Add AudioReach support for QCS6490
Introduce qcs6490-audioreach.dtsi to support AudioReach architecture on
QCS6490 platforms. The existing ADSP Bypass DTSI files such as sc7280.dtsi,
which is tailored for ADSP Bypass architecture as they lack DSP-specific
nodes required for AudioReach. The new qcs6490-audioreach.dtsi file defines
nodes for AudioReach specific components such as APM (Audio Process
Manager), PRM (Proxy Resource Manager), and GPR (Generic Packet Router).
This change enable the audio from the legacy ADSP Bypass solution to
the AudioReach framework.
arm64: dts: qcom: ipq5424: Add reserved memory for TF-A
IPQ5424 supports both TZ and TF-A as secure software options and various
DDR sizes. In most cases, TF-A or TZ is loaded at the same memory
location, but in the 256MB DDR configuration TF-A is loaded at a different
region.
So, add the reserved memory node for TF-A and keep it disabled by default.
During bootup, U-Boot will detect which secure software is running and
enable or disable the node accordingly.
Konrad Dybcio [Tue, 12 Aug 2025 10:48:15 +0000 (12:48 +0200)]
arm64: dts: qcom: sc7180: Describe on-SoC USB-adjacent data paths
USB connector bindings describe a ports subnode, which describes how
its High-/SuperSpeed data lines (as well as the SBU pins for Type-C)
are connected.
On Linux, skipping the graph results in the 'connect_type' sysfs
attribute returning 'unknown', instead of 'hotplug' or similar. This in
turn is parsed by some operating systems (such as CrOS), to e.g. make
security policy decisions.
Define ports {} for the DWC controller & the QMPPHY and connect them
together for the SS lanes.
Leave the DP endpoint unconnected for now, as both Aspire 1 and the
Chromebooks (unmerged, see [1]) seem to have a non-trivial topology.
Take the creative liberty to add a newline before its ports' subnodes
though.
The Laptop is a Snapdragon X1 / X1 Plus (Purwa) based device [1].
Supported features:
- USB type-c and type-a ports
- Keyboard
- Touchpad (all that are described in the dsdt)
- Touchscreen (described in the dsdt, no known SKUss)
- Display including PWM backlight control
- PCIe devices
- nvme
- SDHC card reader
- ath12k WCN7850 Wifi and Bluetooth
- ADSP and CDSP
- GPIO keys (Lid switch)
- Sound via internal speakers / DMIC / USB / headphone jack
- DP Altmode with 2 lanes (as all of these still do)
- Integrated fingerprint reader (FPC)
- Integrated UVC camera
- X1-45 GPU
Not supported yet:
- HDMI port.
- EC and some fn hotkeys.
Limited support yet:
- SDHC card reader is based on the on-chip sdhc_2 controller, but the driver from
the Snapdragon Dev Kit is only a partial match. It can do normal slow sd cards,
but not UHS-I (SD104) and UHS-II.
This work was done without any schematics or non-public knowledge of the device.
So, it is based on the existing x1e device trees, dsdt analysis, using HWInfo
ARM64, and pure guesswork. It has been confirmed, however, that the device really
has 4 NXP PTN3222 eUSB2 repeaters, one of which doesn't have a reset GPIO (eusb5
@43).
Co-developed-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Signed-off-by: Jens Glathe <jens.glathe@oldschoolsolutions.biz> Link: https://lore.kernel.org/r/20250822-tb16-dt-v12-3-bab6c2986351@oldschoolsolutions.biz Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephan Gerhold [Fri, 22 Aug 2025 09:29:01 +0000 (11:29 +0200)]
arm64: dts: qcom: x1e80100-qcp: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Stephan Gerhold [Fri, 22 Aug 2025 09:29:00 +0000 (11:29 +0200)]
arm64: dts: qcom: x1e80100-microsoft-romulus: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Fixes: 09d77be56093 ("arm64: dts: qcom: Add support for X1-based Surface Laptop 7 devices") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-9-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephan Gerhold [Fri, 22 Aug 2025 09:28:59 +0000 (11:28 +0200)]
arm64: dts: qcom: x1e80100-lenovo-yoga-slim7x: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Stephan Gerhold [Fri, 22 Aug 2025 09:28:58 +0000 (11:28 +0200)]
arm64: dts: qcom: x1e80100-hp-omnibook-x14: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Fixes: 6f18b8d4142c ("arm64: dts: qcom: x1e80100-hp-x14: dt for HP Omnibook X Laptop 14") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-7-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephan Gerhold [Fri, 22 Aug 2025 09:28:57 +0000 (11:28 +0200)]
arm64: dts: qcom: x1e80100-dell-xps13-9345: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Fixes: f5b788d0e8cd ("arm64: dts: qcom: Add support for X1-based Dell XPS 13 9345") Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> # 3K OLED Reviewed-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-6-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephan Gerhold [Fri, 22 Aug 2025 09:28:56 +0000 (11:28 +0200)]
arm64: dts: qcom: x1e80100-asus-vivobook-s15: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Fixes: d0e2f8f62dff ("arm64: dts: qcom: Add device tree for ASUS Vivobook S 15") Tested-by: Maud Spierings <maud_spierings@hotmail.com> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-5-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephan Gerhold [Fri, 22 Aug 2025 09:28:55 +0000 (11:28 +0200)]
arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Fixes: 7d1cbe2f4985 ("arm64: dts: qcom: Add X1E78100 ThinkPad T14s Gen 6") Tested-by: Christopher Obbard <christopher.obbard@linaro.org> Reviewed-by: Christopher Obbard <christopher.obbard@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on Lenovo Thinkpad T14s OLED Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-4-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephan Gerhold [Fri, 22 Aug 2025 09:28:54 +0000 (11:28 +0200)]
arm64: dts: qcom: x1-crd: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Stephan Gerhold [Fri, 22 Aug 2025 09:28:53 +0000 (11:28 +0200)]
arm64: dts: qcom: x1-asus-zenbook-a14: Add missing pinctrl for eDP HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Fix this by adding the missing pinctrl for gpio119 (func1/edp0_hot and
bias-disable according to the ACPI DSDT), which is defined as
&edp0_hpd_default template in x1e80100.dtsi.
Fixes: 6516961352a1 ("arm64: dts: qcom: Add support for X1-based Asus Zenbook A14") Tested-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> # FHD OLED Reviewed-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250822-x1e80100-add-edp-hpd-v2-2-6310176239a6@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Stephan Gerhold [Fri, 22 Aug 2025 09:28:52 +0000 (11:28 +0200)]
arm64: dts: qcom: x1e80100: Add pinctrl template for eDP0 HPD
At the moment, we indirectly rely on the boot firmware to set up the
pinctrl for the eDP HPD line coming from the internal display. If the boot
firmware does not configure the display (e.g. because a different display
is selected for output in the UEFI settings), then the display fails to
come up and there are several errors in the kernel log:
[drm:dpu_encoder_phys_vid_wait_for_commit_done:544] [dpu error]vblank timeout: 80020041
[drm:dpu_kms_wait_for_commit_done:524] [dpu error]wait for commit done returned -110
[drm:dpu_encoder_frame_done_timeout:2715] [dpu error]enc40 frame done timeout
...
Add a new &edp0_hpd_default pinctrl template that can be used by boards to
set up the eDP HPD pin correctly. All boards upstream so far need the same
configuration; if a board needs a different configuration it can just avoid
using this template and define a custom one in the board DT.
Barnabás Czémán [Sat, 30 Aug 2025 21:13:20 +0000 (23:13 +0200)]
arm64: dts: qcom: msm8953: correct SPI pinctrls
SPI pinctrls should handle 4 pins MOSI, MISO, CLK and CS.
This change adding the missing pins for pinctrls and correcting
CS pins according to downstream sources.
Jagadeesh Kona [Fri, 22 Aug 2025 09:26:38 +0000 (11:26 +0200)]
arm64: dts: qcom: sm8650: Additionally manage MXC power domain in camcc
Camcc requires both MMCX and MXC rails to be powered ON to configure
the camera PLLs on SM8650 platform. Hence add MXC power domain to
camcc node on SM8650.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-6-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: sm8550: Additionally manage MXC power domain in camcc
Camcc requires both MMCX and MXC rails to be powered ON to configure
the camera PLLs on SM8550 platform. Hence add MXC power domain to
camcc node on SM8550.
Fixes: e271b59e39a6f ("arm64: dts: qcom: sm8550: Add camera clock controller") Reviewed-by: Taniya Das <quic_tdas@quicinc.com> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Vladimir Zapolskiy <vladimir.zapolskiy@linaro.org> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-5-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Jagadeesh Kona [Fri, 22 Aug 2025 09:26:36 +0000 (11:26 +0200)]
arm64: dts: qcom: sm8450: Additionally manage MXC power domain in camcc
Camcc requires both MMCX and MXC rails to be powered ON to configure
the camera PLLs on SM8450 platform. Hence add MXC power domain to
camcc node on SM8450.
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-4-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Jagadeesh Kona [Fri, 22 Aug 2025 09:26:35 +0000 (11:26 +0200)]
arm64: dts: qcom: sm8650: Additionally manage MXC power domain in videocc
Videocc requires both MMCX and MXC rails to be powered ON to configure
the video PLLs on SM8650 platform. Hence add MXC power domain to videocc
node on SM8650.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-3-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Jagadeesh Kona [Fri, 22 Aug 2025 09:26:34 +0000 (11:26 +0200)]
arm64: dts: qcom: sm8550: Additionally manage MXC power domain in videocc
Videocc requires both MMCX and MXC rails to be powered ON to configure
the video PLLs on SM8550 platform. Hence add MXC power domain to videocc
node on SM8550.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-2-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Jagadeesh Kona [Fri, 22 Aug 2025 09:26:33 +0000 (11:26 +0200)]
arm64: dts: qcom: sm8450: Additionally manage MXC power domain in videocc
Videocc requires both MMCX and MXC rails to be powered ON to configure
the video PLLs on SM8450 platform. Hence add MXC power domain to videocc
node on SM8450.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Jagadeesh Kona <quic_jkona@quicinc.com> Signed-off-by: Neil Armstrong <neil.armstrong@linaro.org> Link: https://lore.kernel.org/r/20250822-topic-sm8x50-upstream-pll-multi-pd-voting-dt-v2-1-28f35728a146@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
arm64: dts: qcom: Use GIC_SPI for interrupt-map for readability
Decoding interrupt-map is tricky, because it consists of five
components. Use known GIC_SPI define in final interrupt specifier
component makes easier to read.
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
sm8350.dtsi:1554.4-1557.30: Warning (interrupt_map): /soc@0/pcie@1c00000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
sm8250.dtsi:2166.4-2169.30: Warning (interrupt_map): /soc@0/pcie@1c00000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
sm8150.dtsi:1869.4-1872.30: Warning (interrupt_map): /soc@0/pcie@1c00000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
sm6150.dtsi:1122.4-1125.30: Warning (interrupt_map): /soc@0/pcie@1c08000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
sc8180x.dtsi:1743.4-1746.30: Warning (interrupt_map): /soc@0/pcie@1c00000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
qcs404.dtsi:1496.4-1499.30: Warning (interrupt_map): /soc@0/pcie@10000000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@b000000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
msm8996.dtsi:1931.5-1934.31: Warning (interrupt_map): /soc@0/bus@0/pcie@600000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@9bc0000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
lemans.dtsi:7623.3-7626.29: Warning (interrupt_map): /pcie@1c00000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@17a00000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
ipq5424.dtsi:961.4-964.30: Warning (interrupt_map): /soc@0/pcie@50000000:interrupt-map:
Missing property '#address-cells' in node /soc@0/interrupt-controller@f200000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Stephan Gerhold [Tue, 19 Aug 2025 10:45:23 +0000 (12:45 +0200)]
arm64: dts: qcom: x1e80100-qcp: Fix swapped USB MP repeaters
The &eusb3_repeater belongs to the first port of the USB MP controller and
the &eusb6_repeater belongs to the second. This is obvious if one looks at
e.g. the CRD or the Dell XPS where only the second port of the USB MP is
used: They only have the &eusb6_repeater and already specify it for the
&usb_mp_hsphy1.
Swap them to set the correct repeater for each of the USB ports.
Stephan Gerhold [Tue, 19 Aug 2025 10:45:22 +0000 (12:45 +0200)]
arm64: dts: qcom: x1e80100-asus-vivobook-s15: Fix swapped USB MP repeaters
The &eusb3_repeater belongs to the first port of the USB MP controller and
the &eusb6_repeater belongs to the second. This is obvious if one looks at
e.g. the CRD or the Dell XPS where only the second port of the USB MP is
used: They only have the &eusb6_repeater and already specify it for the
&usb_mp_hsphy1.
Swap them to set the correct repeater for each of the USB ports.
Stephan Gerhold [Tue, 19 Aug 2025 10:45:21 +0000 (12:45 +0200)]
arm64: dts: qcom: x1e78100-lenovo-thinkpad-t14s: Fix swapped USB MP repeaters
The &eusb3_repeater belongs to the first port of the USB MP controller and
the &eusb6_repeater belongs to the second. This is obvious if one looks at
e.g. the CRD or the Dell XPS where only the second port of the USB MP is
used: They only have the &eusb6_repeater and already specify it for the
&usb_mp_hsphy1.
Swap them to set the correct repeater for each of the USB ports.
Stephan Gerhold [Tue, 19 Aug 2025 10:45:20 +0000 (12:45 +0200)]
arm64: dts: qcom: x1e001de-devkit: Fix swapped USB MP repeaters
The &eusb3_repeater belongs to the first port of the USB MP controller and
the &eusb6_repeater belongs to the second. This is obvious if one looks at
e.g. the CRD or the Dell XPS where only the second port of the USB MP is
used: They only have the &eusb6_repeater and already specify it for the
&usb_mp_hsphy1.
Swap them to set the correct repeater for each of the USB ports.
Neil Armstrong [Wed, 20 Aug 2025 09:49:23 +0000 (11:49 +0200)]
arm64: dts: qcom: sm8550: add PPI interrupt partitions for the ARM PMUs
The PMUs shares the same per-cpu (PPI) interrupt, so declare the proper
interrupt partition maps and use the 4th interrupt cell to pass the
partition phandle for each ARM PMU node.
Neil Armstrong [Wed, 20 Aug 2025 09:49:22 +0000 (11:49 +0200)]
arm64: dts: qcom: sm8550: switch to interrupt-cells 4 to add PPI partitions
The ARM PMUs shares the same per-cpu (PPI) interrupt, so we need to switch
to interrupt-cells = <4> in the GIC node to allow adding an interrupt
partition map phandle as the 4th cell value for GIC_PPI interrupts.
Reading the hardware registers of the &slimbam on RB3 reveals that the BAM
supports only 23 pipes (channels) and supports 4 EEs instead of 2. This
hasn't caused problems so far since nothing is using the extra channels,
but attempting to use them would lead to crashes.
The bam_dma driver might warn in the future if the num-channels in the DT
are wrong, so correct the properties in the DT to avoid future regressions.
Shashank Maurya [Thu, 21 Aug 2025 17:54:28 +0000 (23:24 +0530)]
arm64: dts: qcom: lemans-evk: Enable Display Port
Lemans EVK board has two mini-DP connectors, connected to EDP0
and EDP1 phys. Other EDP phys are available on expansion
connectors for the mezzanine boards.
Enable EDP0 and EDP1 along with their corresponding PHYs.
Kamal Wadhwa [Fri, 20 Jun 2025 15:29:57 +0000 (20:59 +0530)]
arm64: dts: qcom: sm8550: Correct the min/max voltages for vreg_l6n_3p3
Voltage regulator 'vreg_l6n_3p3' max-microvolt prop is currently
configured at 3304000uV in different sm8550 board files. However this
is not a valid voltage value for 'pmic5_pldo502ln' type voltage
regulators.
Check below the max value(3200mV) in the regulator summary for min/max
used as 2800mV/3304mV in DT:-
regulator use open bypass opmode voltage current min max
---------------------------------------------------------------------
..
vreg_l6n_3p3 0 0 0 normal 2800mV 0mA 2800mV 3200mV
..
Correct the min/max value to 3200000uV, as that is the closest valid
value to 3.3V and Hardware team has also confirmed that its good to
support the consumers(camera sensors) of this regulator.
Casey Connolly [Thu, 19 Jun 2025 14:55:10 +0000 (16:55 +0200)]
arm64: dts: qcom: sdm845-oneplus-*: set constant-charge-current-max-microamp
Set the maximum constant charge current to use for this battery. While
the battery is likely comfortably capable of 4A or so, OnePlus didn't
include a secondary charger IC for parallel charging (instead they have
their proprietary Dash Charging). It's possible that this value could be
safely increased after some testing (and when we have support for
modelling the charger as a cooling device properly), but for now this
value is acceptable.
This is references from qcom,usb-icl-ua property in the downstream
vendor devicetree.
Gabor Juhos [Wed, 18 Jun 2025 20:14:09 +0000 (22:14 +0200)]
arm64: dts: qcom: ipq9574: use 'pcie' as node name for 'pcie0'
The PCI controller at address 28000000 supports PCIe only, so use 'pcie'
as node name for that. This ensures that all PCIe controller instance
nodes are using the same name.
SPI on SC8280XP requires DMA (GSI) mode to function properly. Without
it, SPI controllers fall back to FIFO mode, which causes:
[ 0.901296] geni_spi 898000.spi: error -ENODEV: Failed to get tx DMA ch
[ 0.901305] geni_spi 898000.spi: FIFO mode disabled, but couldn't get DMA, fall back to FIFO mode
...
[ 45.605974] goodix-spi-hid spi0.0: SPI transfer timed out
[ 45.605988] geni_spi 898000.spi: Can't set CS when prev xfer running
[ 46.621555] spi_master spi0: failed to transfer one message from queue
[ 46.621568] spi_master spi0: noqueue transfer failed
[ 46.621577] goodix-spi-hid spi0.0: spi transfer error: -110
[ 46.621585] goodix-spi-hid spi0.0: probe with driver goodix-spi-hid failed with error -110
Therefore, describe GPI DMA controller nodes for qup{0,1,2}, and
describe DMA channels for SPI and I2C, UART is excluded for now, as
it does not yet support this mode.
Note that, since there is no public schematic, this is derived from
Windows drivers. The drivers do not expose any DMA channel mask
information, so all available channels are enabled.
arm64: dts: qcom: x1e80100-pmics: Disable pm8010 by default
pm8010 is a camera specific PMIC, and may not be present on some
devices. These may instead use a dedicated vreg for this purpose (Dell
XPS 9345, Dell Inspiron..) or use USB webcam instead of a MIPI one
alltogether (Lenovo Thinbook 16, Lenovo Yoga..).
Disable pm8010 by default, let platforms that actually have one onboard
enable it instead.
Cc: stable@vger.kernel.org Fixes: 2559e61e7ef4 ("arm64: dts: qcom: x1e80100-pmics: Add the missing PMICs") Reviewed-by: Bryan O'Donoghue <bryan.odonoghue@linaro.org> Reviewed-by: Johan Hovold <johan+linaro@kernel.org> Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com> Signed-off-by: Aleksandrs Vinarskis <alex.vinarskis@gmail.com> Link: https://lore.kernel.org/r/20250701183625.1968246-2-alex.vinarskis@gmail.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
Konrad Dybcio [Tue, 8 Jul 2025 10:28:42 +0000 (12:28 +0200)]
arm64: dts: qcom: qcm2290: Disable USB SS bus instances in park mode
2290 was found in the field to also require this quirk, as long &
high-bandwidth workloads (e.g. USB ethernet) are consistently able to
crash the controller otherwise.
The same change has been made for a number of SoCs in [1], but QCM2290
somehow escaped the list (even though the very closely related SM6115
was there).
Upon a controller crash, the log would read:
xhci-hcd.12.auto: xHCI host not responding to stop endpoint command
xhci-hcd.12.auto: xHCI host controller not responding, assume dead
xhci-hcd.12.auto: HC died; cleaning up
Add snps,parkmode-disable-ss-quirk to the DWC3 instance in order to
prevent the aforementioned breakage.
Bjorn Andersson [Fri, 15 Aug 2025 13:51:32 +0000 (08:51 -0500)]
Revert "arm64: dts: qcom: sm8450: add initial device tree for Samsung Galaxy S22"
This reverts commit 46952305d2b6 ("arm64: dts: qcom: sm8450: add initial
device tree for Samsung Galaxy S22"), as the merged version had been
superseded and received further feedback.
projects / thirdparty / kernel / linux.git / log
