Jonas Karlman [Mon, 14 Jul 2025 20:34:07 +0000 (20:34 +0000)]
mmc: rockchip_sdhci: Set xx_TAP_VALUE for RK3528
eMMC erase and write support on RK3528 is somewhat unreliable, sometime
e.g. mmc erase and write commands will fail with an error.
Use the delay line lock value for half card clock cycle, DLL_LOCK_VALUE,
to set a manual xx_TAP_VALUE to fix the unreliable eMMC support.
This is only enabled for RK3528, remaining SoCs still use the automatic
tap value, (DLL_LOCK_VALUE * 2) % 256, same value we configure manually
for RK3528.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sat, 12 Jul 2025 21:12:29 +0000 (21:12 +0000)]
rockchip: spl-boot-order: Defer probe of boot device
Boot devices are being probed when SPL boot order is determined. This
may delay boot slightly and can prevent booting from SPI Flash on boards
that use same pins for SPI Flash and eMMC due to pinctrl being applied
prior to booting.
Instead defer probe of the boot device until SPL try to load image from
the boot device by using uclass_find_device_by_of_offset() instead of
the get variant.
Peter Robinson [Fri, 26 Sep 2025 16:29:56 +0000 (17:29 +0100)]
board: rockchip: Add support for rk3588 MNT Reform2
Add support for MNT Reform2, it works as a carrier board
with a Firefly iCore-3588Q SoM.
Specification:
- Rockchip RK3588
- LPDDR5X 16/32 GB
- eMMC 128/256 GB
- HDMI Type A out x 1
- USB 3.0 Host x 1
- USB-C 3.0 with DisplayPort AltMode
- PCIE M.2 E Key for Wireless connection
- PCIE M.2 M Key for NVME connection
- DSI to eDP panel
- 1Gb Ethernet w/ Microchip KSZ9310 PHY
Tested using Fedora boot on USB stick and eMMC.
Signed-off-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
David Barbion [Wed, 10 Sep 2025 21:18:55 +0000 (23:18 +0200)]
board: rockchip: Fix RG353M model renaming
Anbernic RG353M is hardware compatible with RG353P. Only the form-factor
differs. So only one DTS is created for both machines with
"Anbernic RG353P" as default model. If a RG353M is detected, the model
should be overwritten with the correct name.
Actually, it's overwritten with "Anbernic" only making the process of
machine detection a little harder.
However, to determine the size of the string "Anbernic RG353M", it is
sizeof() which is used resulting in obtaining the size of the pointer
(which is 8 bytes on ARM64) not the size of the pointed string.
strlen() should be used instead.
Signed-off-by: David Barbion <davidb@230ruedubac.fr> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Wed, 29 Oct 2025 11:34:25 +0000 (12:34 +0100)]
rockchip: imply most symbols for ARCH_ROCKCHIP
Forcing all those symbols on means we cannot make the binary smaller or
with unnecessary features or drivers disabled. This is especially useful
for security, auditing and certification where less code built means
less to look at (and less surface attack) and less to patch, but also
for making binary images smaller which typically means faster boot.
It is possible to have boards without MMC, NAND or SPI flashes, without
anything on SPI or I2C buses, nothing to control over PWM or GPIO or for
which we have no interest in regulator control or serial output so make
it possible to remove all that if desired.
No intended change in default selected symbols.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Commit 65e2c14d5a5a ("binman: btool: mkimage: use Bintool.version")
removed the version argument from the run method but forgot to remove it
from the method docstring, so let's fix this oversight.
Fixes: 65e2c14d5a5a ("binman: btool: mkimage: use Bintool.version") Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 28 Oct 2025 16:57:37 +0000 (17:57 +0100)]
rockchip: spl_common: fix TIMER_FMODE constant
The free running mode is 0 at bit offset 1. User mode is 1 at bit offset
1. Currently, free running mode is 1 at offset 0, which is already the
case thanks to TIME_EN.
So, this essentially does not change the actual value written to the
register as it is TIME_EN | TIMER_FMODE which currently is 0x1 | BIT(0)
= 0b1, and will become 0x1 | (0 << 1) = 0b1.
I checked PX30, RK3128, RK3188, RK3228, RK3288, RK3308, RK3328, RK3368
RK3506, RK3562 and RK3568 TRMs.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 28 Oct 2025 16:57:36 +0000 (17:57 +0100)]
rockchip: rk3399: fix TIMER_FMODE constant
The free running mode is 0 at bit offset 1. User mode is 1 at bit offset
1. Currently, free running mode is 1 at offset 0, which is already the
case thanks to TIME_EN.
So, this essentially does not change the actual value written to the
register as it is TIME_EN | TIMER_FMODE which currently is 0x1 | BIT(0)
= 0b1, and will become 0x1 | (0 << 1) = 0b1.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 28 Oct 2025 16:57:35 +0000 (17:57 +0100)]
rockchip: rk3036: use rockchip_stimer_init from spl_common.o
The only difference with the implementation in spl_common.c is that we
check whether the timer has already been enabled. Considering this is
running in SPL, the first stage on RK3036, I feel like it's guaranteed
to not be enabled by default. No public TRM though and I don't have
access to an RK3036 device so take this as a guess.
Size of SPL binary increases by 8B for evb-rk3036.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Quentin Schulz [Tue, 28 Oct 2025 16:57:34 +0000 (17:57 +0100)]
rockchip: px30: use rockchip_stimer_init from spl_common.o for TPL
Instead of redefining what is essentially the same code in
secure_timer_init, let's simply use rockchip_stimer_init from
spl_common.o instead.
This increases the size of the TPL by 16B, due to the added check of
STIMER already being enabled. Experimentally, STIMER is not already
enabled when in TPL.
Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit 3ba04aa78ba71faab4a339f5ab15bc81a3e0a51b) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
(cherry picked from commit d272bc0c747a5af49cf98140ebd25a702f84ab52) Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Oct 2025 16:50:50 +0000 (16:50 +0000)]
board: rockchip: Add Luckfox Omni3576
Luckfox Omni3576 Carrier Board with Core3576 Module, powered by the
Rockchip RK3576 SoC with four Cortex-A72 cores, four Cortex-A53 cores,
and a Mali-G52 MC3 GPU.
Features tested with a Core3576 Rev1.1 on a Omni3576 carrier board:
- SD-card boot
- eMMC boot
- LED
- PCIe/NVMe
- USB2.0 HOST
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Oct 2025 15:47:19 +0000 (15:47 +0000)]
board: rockchip: Add Radxa ROCK 4D
The Radxa ROCK 4D is a compact single-board computer (SBC) featuring
numerous top-tier functions, features, and expansion options.
Equipped with the Rockchip RK3576 or RK3576J SoC, the ROCK 4D boasts an
octa-core CPU (4x Cortex-A72 + 4x Cortex-A53), Mali-G52 GPU, and a
powerful 6 TOPS NPU, making it ideal for AI and multimedia tasks.
Features tested on a Radxa ROCK 4D v1.112:
- SPI Flash boot
- Ethernet
- PCIe/NVMe
- USB host
ROCK 4D boards with SPI Flash is configured to boot from FSPI0->UFS->USB,
or directly from USB when the MASKROM button is pressed, booting
directly from SD-card is not possible on these boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Oct 2025 15:47:18 +0000 (15:47 +0000)]
rockchip: rk3576: Add SPI Flash boot support
The bootsource ids reported by BootROM of RK3576 for SPI NOR and USB
differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81.
Add a RK3576 specific read_brom_bootsource_id() function to help decode
the new bootsource id values and the required boot_devices mapping of
sfc0 and sfc1 to help support booting from SPI flash on RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 19 Oct 2025 15:47:16 +0000 (15:47 +0000)]
rockchip: spl: Add a read_brom_bootsource_id() helper
The bootsource ids reported by BootROM of RK3528 and RK3576 for e.g.
SPI NOR and USB differs slightly compared to prior SoCs:
- Booting from sfc0 (ROCK 4D) report the normal bootsource id 0x3.
- Booting from sfc1 M1 (NanoPi M5) report a new bootsource id 0x23.
- Booting from sfc1 M0 has not been tested (no board using this config).
- Booting from USB report a new bootsource id 0x81 on RK3528 and RK3576.
Add a helper function to read the bootsource id. This helper function
will be used to translate the new values to the common BROM_BOOTSOURCE
enum values on RK3528 and RK3576.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 31 Aug 2025 16:49:35 +0000 (16:49 +0000)]
arm: dts: rockchip: Include OTP in U-Boot pre-reloc phase for RK3326
Update rk3326-u-boot.dtsi to include OTP in U-Boot pre-reloc phase for
checkboard() to be able to read information about the running SoC model
and variant from OTP and print it during boot:
Jonas Karlman [Sun, 31 Aug 2025 16:49:30 +0000 (16:49 +0000)]
rockchip: odroid-go2: Use env from same storage FIT was loaded from
Change to dynamically select what storage media to use for the U-Boot
environment depending on from what storage media the FIT images was
loaded from, fall back to use env from nowhere.
U-Boot SPL 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Trying to boot from MMC1
...
Loading Environment from MMC... Reading from MMC(0)...
or
U-Boot SPL 2025.07 (Jul 13 2025 - 10:07:16 +0000)
Trying to boot from SPI
...
Loading Environment from SPIFlash...
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Sun, 31 Aug 2025 16:49:27 +0000 (16:49 +0000)]
rockchip: odroid-go2: Use power off at power plug-in event
Include the RK817 PMIC in SPL and enable Kconfig options to power off
the handheld gaming device when it was powered on due to a power cable
plug-in event:
DDR3, 333MHz
BW=32 Col=10 Bk=8 CS0 Row=15 CS=1 Die BW=16 Size=1024MB
out
Power Off due to plug-in event
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
- Fix a i.MX6ULL regression related to the REFTOP_VBGADJ setting.
- Shrink SPL size for the Liebherr BTT board.
- Add suppot for Toradex SMARC iMX95.
- Fix Aquila imx95 0098 Product ID.
Tom Rini [Thu, 30 Oct 2025 14:03:02 +0000 (08:03 -0600)]
Merge tag 'qcom-for-2026.01-rc2' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
A variety of Qualcomm features/fixes for this cycle, notably with a few
new platforms gaining support:
* Initial support for SDM670 (similar to SDM845), SM6350, and SM7150
platforms is added
* USB and UART issues on MSM8916 are addressed (improving stability/
reliability)
* Firmware loading is implemented for the GENI serial engine, this is
used on some platforms to load firmware for i2c/spi/uart to work
Some additional patches like binman support for building MBN files still
need some additional work.
Stephan Gerhold [Mon, 7 Apr 2025 09:54:26 +0000 (11:54 +0200)]
usb: host: ehci-msm: Register ULPI PHY through NOP wrapper
The UCLASS_USB device is removed and rebound each time you run "usb stop"
followed by "usb start", or when you switch between USB device and USB host
mode. Unfortunately, this causes issues with the current ehci-msm driver:
In ehci_usb_remove() we call generic_shutdown_phy(), but at that point the
ULPI PHY we registered in ehci_usb_of_bind() was already removed again by
the DM core.
Fix this by adding a UCLASS_NOP driver that keeps the PHY driver bound
permanently, and then just re-probe the actual USB part.
Reported-by: Jianfeng Zhu <JianfengA.Zhu@sony.com> Closes: https://lore.kernel.org/u-boot/OSQPR04MB774067EBEEADD714EFE18C2A90882@OSQPR04MB7740.apcprd04.prod.outlook.com/ Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Tested-by: Sam Day <me@samcday.com> Link: https://patch.msgid.link/20250407-ehci-msm-fixes-v1-6-f8b30eb05d07@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Stephan Gerhold [Mon, 7 Apr 2025 09:54:25 +0000 (11:54 +0200)]
usb: host: ehci-msm: Drop redundant EHCI register writes
ehci_unregister() already clears the CMD_RUN bit with more careful checks.
It also ensures that we only do this in case we were actually in USB host
(rather than USB device) mode. It's not clear what the extra register
writes in the Qualcomm-specific ehci-msm driver are supposed to do, so just
drop them.
Stephan Gerhold [Mon, 7 Apr 2025 09:54:21 +0000 (11:54 +0200)]
usb: host: ehci-msm: Fix pointer check
dev_read_addr_ptr() returns a null pointer on error, not FDT_ADDR_T_NONE.
Fixes: 2be1130a9305 ("usb: ehci-msm: Use dev interface to get device address") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Acked-by: Caleb Connolly <caleb.connolly@linaro.org> Tested-by: Sam Day <me@samcday.com> Link: https://patch.msgid.link/20250407-ehci-msm-fixes-v1-1-f8b30eb05d07@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Stephen Boyd [Mon, 14 Jul 2025 13:13:17 +0000 (15:13 +0200)]
serial: msm-geni: Enable SE clk in probe
Enable the serial engine clk in probe so that this driver can work on
platforms that don't already initialize the clk for this device before
this driver runs. This fixes a problem I see on Coreboot platforms like
Trogdor where the UART hardware isn't enabled by coreboot unless the
serial console build is used.
Qualcomm peripherals like UART, SPI, I2C, etc are all exposed under a
common GENI Serial Engine wrapper device. Replace the stub driver we use
for this currently with a full-on misc device and implement support for
loading peripheral firmware.
Each of the peripherals has it's own protocol-specific firmware, this is
stored on the internal storage of the device with a well-known partition
type GUID.
To support this, GENI will bind peripherals in two stages. First the
ones that already have firmware loaded (such as the serial port) are
bound in the typical way. But devices that require firmware loading are
deferred until EVT_LAST_STAGE_INIT. At this point we can be sure that
the storage device is available, so we load the firmware and then bind
and probe the remaining children.
Child devices are expected to determine if firmware loading is necessary
and call qcom_geni_load_firmware().
Since Linux currently doesn't support loading firmware (and firmware may
not be available), we probe all GENI peripherals to ensure that they
always load firmware if necessary.
Ye Li [Mon, 27 Oct 2025 11:56:38 +0000 (08:56 -0300)]
imx: Revert "imx: mx6ull: fix REFTOP_VBGADJ setting" and fix comments
The change in commit c1af358cf51a ("imx: mx6ull: fix REFTOP_VBGADJ
setting") is not correct. According to latest i.MX6ULL fuse table,
the REFTOP_TRIM[2:0] fuse is defined as below. So the previous codes
are correct, only need to fix the comments.
Set the REFTOP_VBGADJ field in PMU_MISC0 register based on the
REFTOP_TRIM fuse:
'000" - set REFTOP_VBGADJ[2:0] to 3'b000
'001" - set REFTOP_VBGADJ[2:0] to 3'b001
'010" - set REFTOP_VBGADJ[2:0] to 3'b010
'011" - set REFTOP_VBGADJ[2:0] to 3'b011
'100" - set REFTOP_VBGADJ[2:0] to 3'b100
'101" - set REFTOP_VBGADJ[2:0] to 3'b101
'110" - set REFTOP_VBGADJ[2:0] to 3'b110
'111" - set REFTOP_VBGADJ[2:0] to 3'b111
Sven Schwermer reported:
"These are the symptoms: Very few of the thousands of devices that we
manufacture (< 1%) fail to decompress a large XZ archive once in Linux
userspace. We have not found any form of memory testing or other load
that reproduces this issue. Reverting the offending patch fixes this
behavior on the affected devices."
Revert the offending commit to fix the regression.
Reported-by: Sven Schwermer <u-boot@schwermer.no> Signed-off-by: Ye Li <ye.li@nxp.com>
[fabio: Fixed checkpatch warning and added Sven's report] Signed-off-by: Fabio Estevam <festevam@gmail.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Link: https://www.toradex.com/computer-on-modules/smarc-arm-family/nxp-imx95 Link: https://www.toradex.com/products/carrier-board/smarc-development-board-kit Signed-off-by: João Paulo Gonçalves <joao.goncalves@toradex.com> Co-developed-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Co-developed-by: Max Krummenacher <max.krummenacher@toradex.com> Signed-off-by: Max Krummenacher <max.krummenacher@toradex.com> Co-developed-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com> Signed-off-by: Ernest Van Hoecke <ernest.vanhoecke@toradex.com>
Emanuele Ghidoli [Fri, 24 Oct 2025 05:40:32 +0000 (07:40 +0200)]
arm: imx8: select ARCH_MISC_INIT if FSL_CAAM is enabled
Commit 2a7acc865b9d ("configs: colibri-imx8x: enable RNG support for KASLR")
enables FSL_CAAM which requires initialization in arch_misc_init().
The ARCH_MISC_INIT configuration was added to the relevant defconfig.
Commit d0ed9636902b ("global: Make ARCH_MISC_INIT a selected symbol")
changed ARCH_MISC_INIT to require explicit selection by the developer.
With this change the colibri-imx8x defconfig is no longer sufficient to
enable ARCH_MISC_INIT when FSL_CAAM is selected.
Add the necessary selection to automatically enable ARCH_MISC_INIT when
FSL_CAAM is enabled on i.MX8 platforms.
Fixes: d0ed9636902b ("global: Make ARCH_MISC_INIT a selected symbol") Signed-off-by: Emanuele Ghidoli <emanuele.ghidoli@toradex.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
The repeated "lookup and request" pattern in spl_board_init() suggests
a low-hanging fruit for reducing the code size. This reduces the
object size of spl/board/liebherr/btt/btt.o by 300 bytes.
I've left the lack of error handling as-is; there isn't really
anything to do if it fails, so I suppose the printfs are the best that
can be done.
Primoz Fiser [Wed, 15 Oct 2025 06:33:47 +0000 (08:33 +0200)]
thermal: imx_tmu: Always set thermal trips from fuses
NXP i.MX SoCs are available in different temperature grades. By default,
device-tree contains only thermal trips for consumer grade parts. On the
other hand, part temp grade fuse can be used to determine thermal trip
points. We already do this in imx_tmu_bind() function. Now, factor out
this functionality to a standalone function imx_tmu_set_trips() and use
it for both cases. This fixes an issue where 'cpu-thermal' child device
would set different thermal trips than the parent 'tmu@44482000' sensor,
depending on which gets used.
- Add support for Samsung Exynos 7870 DW-MMC device
- Add support for Samsung S2MPU05 PMIC device
- Add compatible string for Exynos5250 in Exynos DW-MMC driver
- Add support for handling UHS-I voltage signaling without power-cycle
- Minor misc cleanup
Peng Fan [Thu, 23 Oct 2025 13:11:04 +0000 (21:11 +0800)]
mmc: exynos_dw_mmc: guard execute_tuning
Guard execute_tuning with MMC_SUPPORTS_TUNING, otherwise there will be
build failure:
drivers/mmc/exynos_dw_mmc.c:484:10: error: 'struct dm_mmc_ops' has no member
named 'execute_tuning'
.execute_tuning = exynos_dwmmc_execute_tuning,
^~~~~~~~~~~~~~
Tanmay Kathpalia [Tue, 21 Oct 2025 20:54:10 +0000 (13:54 -0700)]
sdhci: Reorder interrupt flags in SDHCI_INT_DATA_MASK definition
Reorder the SDHCI_INT_SPACE_AVAIL and SDHCI_INT_DATA_AVAIL flags in the
SDHCI_INT_DATA_MASK definition to match the bit order as defined in the
SDHCI specification and maintain consistency with the register layout.
The functional behavior remains unchanged as this only affects the
order of OR operations in the mask definition.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Tanmay Kathpalia [Tue, 21 Oct 2025 20:45:26 +0000 (13:45 -0700)]
mmc: sd: Handle UHS-I voltage signaling without power cycle
Some boards have SD card connectors where the power rail cannot be switched
off by the driver. However there are various circumstances when a card
might be re-initialized, such as after system resume, warm re-boot, or
error handling. However, a UHS card will continue to use 1.8V signaling
unless it is power cycled.
If the card has not been power cycled, it may still be using 1.8V
signaling. According to the SD spec., the Bus Speed Mode (function group 1)
bits 2 to 4 are zero if the card is initialized at 3.3V signal level. Thus
they can be used to determine if the card has already switched to 1.8V
signaling. Detect that situation and try to initialize a UHS-I (1.8V)
transfer mode.
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
power: pmic: s2mps11: add support for Samsung S2MPU05 PMIC
Samsung S2MPU05 PMIC is used in devices with the Exynos7870 SoC, it
houses voltage regulators and an RTC module. Add support for this device
variant in the driver, which also binds the corresponding voltage
regulator driver.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
The functions s2mps11_{buck,ldo}_mode use the s2mps11_{buck,ldo}_modes
arrays directly in order to extract the mode of a certain register.
This approach does not allow similar devices of other variants (which
may support a different set of modes) to work with the same driver.
Instead of using these arrays hardcoded, extract them from the device's
uclass platform data. Now the responsibility of setting these arrays
properly is done by functions s2mps11_{buck,ldo}_probe, by implementing
a switch-case block which can support modes of multiple variants if and
when added.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
power: regulator: s2mps11: declaratively define LDOs and BUCKs
In the Linux kernel driver, all information related to LDO and BUCK
regulators are stored in descriptive arrays. This also allows multiple
variants to be supported by the same driver.
Define a struct sec_regulator_desc which holds all values required by a
regulator. Create an array of said struct containing all regulators. The
descriptors are designed to follow a style similar to what's seen in the
Linux driver, so comparing one with the other is simple.
In functions such as s2mps11_{buck,ldo}_{val,mode} these values are to
be used, make necessary modifications to pull them from the descriptors.
Since multiple variants have varying descriptors, select them from
within a switch-case block.
Functions s2mps11_{buck,ldo}_{volt2hex,hex2volt} and arrays
s2mps11_buck_{ctrl,out} are phased out as the calculations are now
hardcoded in descriptors, thusly, it reduces clutter and enhances
readability.
Two macros in s2mps11.h, S2MPS11_LDO_NUM and S2MPS11_BUCK_NUM are
removed as they are no longer being used.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
power: pmic: s2mps11: add support for allowing multiple device variants
There are multiple PMICs by Samsung which are similar in architecture
(register layout, interface, etc.) and is possible to be driven by a
single driver. Variant specific code and data should be managed properly
in the driver.
And an enum which describes all supported variants. Pass the enum as the
device driver data. Introduce a switch-case block on the enum for any
variant specific code.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
power: pmic: s2mps11: change the probe function to bind
The probe function, s2mps11_probe() is responsible for binding its PMIC
children. The driver doesn't have any functionality directly, but has
sub-devices which are parts of the device. Therefore, this should be a
bind function. This is the case in the Samsung S5M8767 PMIC driver.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
mmc: exynos_dw_mmc: add compatible for exynos7870-dw-mshc-smu
Exynos7870 is documented in upstream dt-schema. Add it in the U-Boot
driver.
Note that here it seems that Exynos7 DW MMC is perfectly compatible with
Exynos7870 DW MMC. It's not always true, especially in SDIO cards where
data from a 64-bit FIFO is read in two 32-bit halves [1]. Since SDIO
isn't used or implemented here, it's oblivious. But upstream's schema
considers that quirk, so that compatible is followed.
SD UHS mode is already supported by the Exynos DW-MMC driver in mainline
Linux. Using that as reference, add support in the U-Boot driver.
The maximum frequency was capped to 200000000, increase it to 208000000,
which is the required frequency for UHS_SDR104, which has the highest
frequency of all UHS modes. Moreover, add UHS_CAPS to host capailities.
These changes allow both host and card to recognize support for all UHS
modes.
SDR104, SDR50, and DDR50 have their own CLKSEL timing values, which
requires the CIU div value to be set in bits 18:16. Move the function
exynos_dwmci_clksel() below exynos_dwmmc_get_ciu_div() so that the
latter is accessible from the former, and add cases for said timing
modes.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
mmc: exynos_dw_mmc: add support for MMC HS200 and HS400 modes
MMC HS200 and HS400 modes are already supported by the Exynos DW-MMC
driver in mainline Linux. Using that as reference, add support in the
U-Boot driver.
The maximum frequency was capped to 50000000, increase it to 200000000,
which is the required frequency for HS200/HS400. Moreover, add
MMC_MODE_HS200 and MMC_MODE_HS400 to host capailities. These changes
allow both host and card to recognize support for HS200/HS400.
This change also includes a new ops function, namely execute_tuning.
Implementing it would mean that we can no longer rely on the default ops
provided by dw_mmc.c, thus a new ops instance is created with proper
fields. The execute_tuning function is modeled after the one available
in the Linux driver.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
mmc: enable/disable VQMMC regulator only during MMC power cycle
Disrupting the regulator voltage during ios configuration messes with
the MMC initialization sequence. Move the VQMMC regulator enable/disable
functions to the MMC power cycle function, similar to how its done for
the VMMC regulator.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
mmc: dw_mmc: return error for invalid voltage setting
In certain cases, the VQMMC regulator may not support certain voltages.
For instance, a VQMMC regulator which supports only up to 2.7V will not
accept 3.3V as an argument. This is unaccounted for, and thus the driver
incorrectly assumes that the voltage is set successfully.
Fetch the return value in a variable and return if it's non-zero.
(-ENOSYS is exempted as it implies that the voltage adjustment
functionality as a whole isn't supported).
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
During a voltage switch command (CMD11, opcode: SD_CMD_SWITCH_UHS18V),
certain hosts tend to stop responding to subsequent commands. This is
addressed by introducing an additional command flag,
DWMCI_CMD_VOLT_SWITCH.
The associated interrupt bit is defined as DWMCI_INTMSK_VOLTSW. This is
set high when a voltage switch is issued, this needs to be waited for
and set to low. Implement the same in the timeout loop. Do note that
since DWMCI_INTMSK_VOLTSW shares the same bit as DWMCI_INTMSK_HTO (bit
10), the interrupt bit needs to be polled for only if the volt switch
command is issued.
DWMCI_CMD_VOLT_SWITCH also needs to be set for subsequent clken commands
after the volt switch. To ensure this, add a boolean member in the host
private struct (herein named volt_switching), which informs if the last
command issued was for volt switching or not.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
mmc: dw_mmc: properly address command completion in dwmci_control_clken()
The current implementation polls for the DWMCI_CMD register, for the
DWMCI_CMD_START bit to turn off, which indicates that the command has
been completed. The problem with this approach is that it doesn't
address the DWMCI_INTMSK_CDONE bit in the interrupt register,
DWMCI_RINTSTS. As a result, subsequent commands result in timeout errors.
Re-implement the waiting logic by polling for said interrupt status bit
and setting it low if raised.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Signed-off-by: Peng Fan <peng.fan@nxp.com>
mmc: dw_mmc: do not skip dwmci_setup_bus() for same non-zero clock frequency
In dwmci_setup_bus(), if the requested frequency is equal to the current
frequency, the function is returned, assuming no changes are required in
associated registers.
On certain SD cards, skipping in such situations may result in a timeout
errors during MMC initialization. Due to the lack of documentation, the
cause is unknown, but removing said check seems to fix the issue.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
mmc: dw_mmc: export dwmci_send_cmd() and dwmci_set_ios()
These commands are required by struct dm_mmc_ops. Any platform specific
driver may use some or all of the functions in their own ops. Make them
accessible by moving the prototype to the dwmmc.h header.
Signed-off-by: Kaustabh Chakraborty <kauschluss@disroot.org> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Lukas Timmermann [Tue, 14 Oct 2025 11:40:32 +0000 (13:40 +0200)]
mmc: exynos_dw_mmc: Add compatible string for Exynos5250
This driver got successfully tested with an upstream device tree
and an Exynos5250. The board in question is samsung-manta
(Google Nexus 10) which we are getting ready for upstream.
For the u-boot port was just this additional compatible string needed.
Signed-off-by: Lukas Timmermann <uboot@timmermann.space> Reviewed-by: Peng Fan <peng.fan@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
- riscv: dts: starfive: cherry-pick jh7110 updates from v6.18-rc1-dts
- riscv: Add upstream boards Milk-V Mars CM and Mars CM Lite
- timer: sifive_clint: Add GHRTv2 compaible string
Stephan Gerhold [Mon, 8 Sep 2025 11:31:26 +0000 (13:31 +0200)]
serial: msm: Use single character mode
The UART DM controller supports different channel data packing modes,
either the 4-character packing mode (where 32-bit are read/written at once)
or the single-character mode (where only a single character is read/written
at a time). The 4-character mode can be more efficient, but the
single-character mode is much easier to implement.
At the moment, serial_msm uses the 4-character mode. Since the
dm_serial_ops operate on one character at the time, the code goes through
quite some hoops in order to break this down to single characters. This
code is prone to race conditions (e.g. priv->chars_cnt is read from the
registers, then a command is issued, what if another char came in
inbetween?). It also seems to cause another subtle issue with autoboot:
Unlike the previous autoboot failures that happened when UART was
disconnected, this problem occurs when UART is connected and open in a
terminal: For EFI boot, the console size is queried in efi_console.c
query_console_serial() by sending an ANSI escape code via UART. For some
reason, with the current driver we get yet another 0x00 byte (UART break
event?) when reading the reply from serial input. Because of that, reading
the console size fails in efi_console.c, the actual reply remains in the
UART buffer, and later the boot flow aborts because it detects input after
printing a prompt.
Rather than trying to fix the issue in the current complicated approach,
switch the driver to use the single-character mode. This is simple and
straightforward to implement without race conditions:
- We write one character at a time to UARTDM_TF, as long as the TX FIFO
has space available (TX_READY). To flush the console before starting
Linux, we wait for TX_EMPTY.
- We read one character at a time from UARTDM_RF and strip off the
additional error information (assuming there is something in the
RX FIFO, as indicated by RX_READY).
In this mode, querying the serial console size works and autoboot is no
longer interrupted. The overall code is also much shorter.
Stephan Gerhold [Mon, 8 Sep 2025 11:31:25 +0000 (13:31 +0200)]
serial: msm: Re-enable after resetting
The documentation for the UART controller in the APQ8016E specifies that
both RESET and ENABLE commands must be issued to set up the receiver and
transmitter, but at the moment we only issue RESET. This doesn't seem to
cause issues in practice (looks like the reset already re-enables the
receiver/transmitter), but let's add the two writes to RX_ENABLE/TX_ENABLE
to better match the recommendations in the documentation.
projects / thirdparty / u-boot.git / log
