Ivan Lipski [Thu, 30 Oct 2025 15:25:33 +0000 (11:25 -0400)]
drm/amd/display: Add an HPD filter for HDMI
[Why]
Some monitors perform rapid “autoscan” HPD re‑assertions right after a
disconnect or powersaving mode enablement. These appear as a quick
disconnect→reconnect with an identical EDID. Since Linux has no HDMI
hotplug detection (HPD) filter, these quick reconnects are seen as hotplug
events, which can unintentionally wake a system with DPMS off.
An example: https://gitlab.freedesktop.org/drm/amd/-/issues/2876
Such 'fake reconnects' are considered when the interval between a
disconnect and a connect is within 1500ms (experimentally chosen using
several monitors), and the two connections have the same EDID.
[How]
Implement a time-based debounce mechanism:
1. On HDMI disconnect detection, instead of immediately processing the
HPD event, save the current sink and schedule delayed work (default 1500ms)
2. If another HDMI disconnect HPD event arrives during the debounce period,
it reschedules the pending work, ensuring only the final state is processed.
3. When the debounce timer expires, re-detect the display and compare the
new sink with the cached one using EDID comparison.
4. If sinks match (same EDID), this was a spontaneous HPD toggle:
- Update connector state internally
- Skip hotplug event to prevent desktop rearrangement
If sinks differ, this was a real display change:
- Process normally with the hotplug event
The debounce delay is configurable via module parameter
'hdmi_hpd_debounce_delay_ms'.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/2876 Reviewed-by: Sun peng (Leo) Li <sunpeng.li@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why]
Empirical measurement of some monitors that fail to read EDID while
booting shows that the number of retries with a 30ms delay between
tries is as high as 16.
[How]
Increase number of retries to 20.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4672 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
drm/amd/display: Move sleep into each retry for retrieve_link_cap()
[Why]
When a monitor is booting it's possible that it isn't ready to retrieve
link caps and this can lead to an EDID read failure:
```
[drm:retrieve_link_cap [amdgpu]] *ERROR* retrieve_link_cap: Read receiver caps dpcd data failed.
amdgpu 0000:c5:00.0: [drm] *ERROR* No EDID read.
```
[How]
Rather than msleep once and try a few times, msleep each time. Should
be no changes for existing working monitors, but should correct reading
caps on a monitor that is slow to boot.
Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4672 Reviewed-by: Alex Hung <alex.hung@amd.com> Signed-off-by: Mario Limonciello (AMD) <superm1@kernel.org> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Paul Hsieh [Thu, 30 Oct 2025 04:17:53 +0000 (12:17 +0800)]
drm/amd/display: Re-check seamless boot can be enabled or not
[Why]
If the seamless boot feature has already been enabled, and
dc_commit_streams is called again before receiving a flip, the
driver will adjust the engine clock without turning off the screen,
which will cause garbage to occur. However, in reality, the Pixel
Clock from the first dc_commit_streams and the second dc_commit_streams
are different.
[How]
If the apply seamless boot flag in the previous stream has not been
cleared, and dc_commit_streams is received again, we need to recheck
whether seamless boot should be disabled
Reviewed-by: Nicholas Kazlauskas <nicholas.kazlauskas@amd.com> Signed-off-by: Paul Hsieh <Paul.Hsieh@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Chang [Wed, 20 Aug 2025 08:59:08 +0000 (16:59 +0800)]
drm/amd/display: Get panel replay capability from DPCD
[Why&How]
Read Panel replay caps from DPCD when retrieving link capability
Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Jack Chang <jack.chang@amd.com> Signed-off-by: Leon Huang <Leon.Huang1@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Jack Chang [Thu, 21 Aug 2025 05:19:23 +0000 (13:19 +0800)]
drm/amd/display: Add panel replay enablement option and logic
[Why&How]
1.Add flow to enable and configure panel replay enablement and
configuration
2.Add registry key for enable option
3.Add replay version check to be compatible with freesync replay
4.Add AC/DC switch function to notify ac/dc change.
5.Add flow in set event function to check and decide Replay
enable/disable
Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Jack Chang <jack.chang@amd.com> Signed-off-by: Leon Huang <Leon.Huang1@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
[Why&How]
For supporting VESA PR, add flow to determine the support capability
Reviewed-by: Robin Chen <robin.chen@amd.com> Signed-off-by: Jack Chang <jack.chang@amd.com> Signed-off-by: Leon Huang <Leon.Huang1@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
George Shen [Wed, 29 Oct 2025 15:27:32 +0000 (11:27 -0400)]
drm/amd/display: Add interface to capture expected HW state from SW state
[Why]
To debug certain issues, such as underflow, it is common practice to
dump the HW state of all registers for analysis. The first thing to
check with the dump is to ensure all values are programmed as expected
according to SW state.
[How]
Add interface to DC to capture expected HW register values based on SW
state.
Reviewed-by: Dillon Varone <dillon.varone@amd.com> Signed-off-by: George Shen <george.shen@amd.com> Signed-off-by: Ivan Lipski <ivan.lipski@amd.com> Tested-by: Dan Wheeler <daniel.wheeler@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Dave Airlie [Mon, 17 Nov 2025 20:52:08 +0000 (06:52 +1000)]
Merge tag 'drm-intel-gt-next-2025-11-14' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
Driver Changes:
Fixes/improvements/new stuff:
- Avoid lock inversion when pinning to GGTT on CHV/BXT+VTD (Janusz Krzysztofik)
- Use standard API for seqcount read in TLB invalidation [gt] (Andi Shyti)
Miscellaneous:
- Wait longer for threads in migrate selftest on CHV/BXT+VTD (Janusz Krzysztofik)
- Wait for page_sizes_gtt in gtt selftest on CHV/BXT+VTD (Janusz Krzysztofik)
Dave Airlie [Mon, 17 Nov 2025 19:55:51 +0000 (05:55 +1000)]
Merge tag 'drm-intel-next-2025-11-14' of https://gitlab.freedesktop.org/drm/i915/kernel into drm-next
drm/i915 feature pull #2 for v6.19:
Features and functionality:
- Add initial display support for Xe3p_LPD, display version 35 (Sai Teja, Matt
R, Gustavo, Matt A, Ankit, Juha-pekka, Luca, Ravi Kumar)
- Compute LT PHY HDMI params when port clock not in predefined tables (Suraj)
Refactoring and cleanups:
- Refactor intel_frontbuffer split between i915, xe, and display (Ville)
- Clean up intel_de_wait_custom() usage (Ville)
- Unify display register polling interfaces (Ville)
- Finish removal of the expensive format info lookups (Ville)
- Cursor code cleanups (Ville)
- Convert intel_rom interfaces to struct drm_device (Jani)
Fixes:
- Fix uninitialized variable in DSI exec packet (Jonathan)
- Fix PIPEDMC logging (Alok Tiwari)
- Fix PSR pipe to vblank conversion (Jani)
- Fix intel_frontbuffer lifetime handling (Ville)
- Disable Panel Replay on DP MST for the time being (Imre)
Merges:
- Backmerge drm-next to get the drm_print.h changes (Jani)
Dave Airlie [Mon, 17 Nov 2025 04:21:48 +0000 (14:21 +1000)]
Merge tag 'drm-misc-next-2025-11-14-1' of https://gitlab.freedesktop.org/drm/misc/kernel into drm-next
drm-misc-next for v6.19:
UAPI Changes:
- Add sysfs entries, coredump support and uevents to QAIC.
- Add fdinfo memory statistics to ivpu.
Cross-subsystem Changes:
- Handle stub fence initialization during module init.
- Stop using system_wq in scheduler and drivers.
Core Changes:
- Documentation updates to ttm, vblank.
- Add EDID quirk for sharp panel.
- Use drm_crtc_vblank_(crtc,waitqueue) more in core and drivers.
Driver Changes:
- Small updates and fixes to panfrost, amdxdna, vmwgfx, ast, ivpu.
- Handle preemption in amdxdna.
- Add PM support to qaic.
- Huge refactor of sun4i's layer code to decouple plane code from output
and improve support for DE33.
- Add larger page and compression support to nouveau.
Dave Airlie [Sun, 16 Nov 2025 22:21:58 +0000 (08:21 +1000)]
Merge tag 'drm-xe-next-2025-11-05' of https://gitlab.freedesktop.org/drm/xe/kernel into drm-next
UAPI Changes:
Limit number of jobs per exec queue (Shuicheng)
Add sriov_admin sysfs tree (Michal)
Driver Changes:
Fix an uninitialized value (Thomas)
Expose a residency counter through debugfs (Mohammed Thasleem)
Workaround enabling and improvement (Tapani, Tangudu)
More Crescent Island-specific support (Sk Anirban, Lucas)
PAT entry dump imprement (Xin)
Inline gt_reset in the worker (Lucas)
Synchronize GT reset with device unbind (Balasubramani)
Do clean shutdown also when using flr (Jouni)
Fix serialization on burst of unbinds (Matt Brost)
Pagefault Refactor (Matt Brost)
Remove some unused code (Gwan-gyeong)
Timur Kristóf [Fri, 14 Nov 2025 12:07:36 +0000 (13:07 +0100)]
drm/amdgpu: Use amdgpu by default on SI dedicated GPUs (v2)
Now that the DC analog connector support and VCE1 support landed,
amdgpu is at feature parity with the old radeon driver
on SI dGPUs.
Enabling the amdgpu driver by default for SI dGPUs has the
following benefits:
- More stable OpenGL support through RadeonSI
- Vulkan support through RADV
- Improved performance
- Better display features through DC
Users who want to keep using the old driver can do so using:
amdgpu.si_support=0 radeon.si_support=1
v2:
- Update documentation in Kconfig file
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Fri, 14 Nov 2025 14:26:08 +0000 (09:26 -0500)]
drm/amdgpu: Use amdgpu by default on CIK dedicated GPUs
The amdgpu driver has been working well on CIK dGPUs for years.
Now that the DC analog connector support landed,
amdgpu is at feature parity with the old radeon driver
on CIK dGPUs.
Enabling the amdgpu driver by default for CIK dGPUs has the
following benefits:
- More stable OpenGL support through RadeonSI
- Vulkan support through RADV
- Improved performance
- Better display features through DC
Users who want to keep using the old driver can do so using:
amdgpu.cik_support=0 radeon.cik_support=1
v2:
- Update documentation in Kconfig file
v3:
- Rebase documentation updates (Alex)
Reviewed-by: Christian König <christian.koenig@amd.com> Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Tue, 28 Oct 2025 10:16:12 +0000 (11:16 +0100)]
drm/amdgpu: use GFP_ATOMIC instead of NOWAIT in the critical path
Otherwise job submissions can fail with ENOMEM.
We probably need to re-design the per VMID tracking at some point.
Signed-off-by: Christian König <christian.koenig@amd.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4258 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Christian König [Wed, 29 Oct 2025 14:36:32 +0000 (15:36 +0100)]
drm/amdgpu: avoid memory allocation in the critical code path v3
When we run out of VMIDs we need to wait for some to become available.
Previously we were using a dma_fence_array for that, but this means that
we have to allocate memory.
Instead just wait for the first not signaled fence from the least recently
used VMID to signal. That is not as efficient since we end up in this
function multiple times again, but allocating memory can easily fail or
deadlock if we have to wait for memory to become available.
v2: remove now unused VM manager fields
v3: fix dma_fence reference
Signed-off-by: Christian König <christian.koenig@amd.com> Closes: https://gitlab.freedesktop.org/drm/amd/-/issues/4258 Reviewed-by: Alex Deucher <alexander.deucher@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Will Aitken [Tue, 7 Oct 2025 14:49:15 +0000 (14:49 +0000)]
drm/amdgpu: Enable xgmi extended peer links for sriov guest
The amd-smi tool relies on extended peer link information to report xgmi
link metrics. The necessary xgmi ta command, GET_EXTEND_PEER_LINKS, has
been enabled in the host driver and this change is necessary for the
guest to make use of it. To handle the case where the host driver does
not have the latest xgmi ta, the guest driver checks for guest support
through a pf2vf feature flag before invoking psp.
Signed-off-by: Will Aitken <wiaitken@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Will Aitken [Tue, 30 Sep 2025 16:24:07 +0000 (16:24 +0000)]
drm/amdgpu: Refactor sriov xgmi topology filling to common code
amdgpu_xgmi_fill_topology_info and psp_xgmi_reflect_topology_info
perform the same logic of copying topology info of one node to every
other node in the hive. Instead of having two functions that purport to
do the same thing, this refactoring moves the logic of the fill function
to the reflect function and adds reflecting port number info as well for
complete functionality.
Signed-off-by: Will Aitken <wiaitken@amd.com> Reviewed-by: Lijo Lazar <lijo.lazar@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Timur Kristóf [Sun, 9 Nov 2025 15:41:06 +0000 (16:41 +0100)]
drm/amdgpu: Use amdgpu by default on CIK dedicated GPUs
The amdgpu driver has been working well on CIK dGPUs for years.
Now that the DC analog connector support landed, these GPUs
are at feature parity with the old radeon driver.
Additionally, amdgpu yields extra performance, supports Vulkan
and provides more display features through DC as well as more
robust power management.
Signed-off-by: Timur Kristóf <timur.kristof@gmail.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Matt Roper [Mon, 10 Nov 2025 23:20:21 +0000 (15:20 -0800)]
drm/xe/oa: Store forcewake reference in stream structure
Calls to xe_force_wake_put() should generally pass the exact reference
returned by xe_force_wake_get(). Since OA grabs and releases forcewake
in different functions, xe_oa_stream_destroy() is currently calling put
with a hardcoded ALL mask. Although this works for now, it's somewhat
fragile in case OA moves to more precise power domain management in the
future.
Stash the original reference obtained during stream initialization
inside the stream structure so that we can use it directly when the
stream is destroyed.
Matt Roper [Mon, 10 Nov 2025 23:20:20 +0000 (15:20 -0800)]
drm/xe/eustall: Store forcewake reference in stream structure
Calls to xe_force_wake_put() should generally pass the exact reference
returned by xe_force_wake_get(). Since EU stall grabs and releases
forcewake in different functions, xe_eu_stall_disable_locked() is
currently calling put with a hardcoded RENDER domain. Although this
works for now, it's somewhat fragile in case the power domain(s)
required by stall sampling change in the future, or if workarounds show
up that require us to obtain additional domains.
Stash the original reference obtained during stream enable inside the
stream structure so that we can use it directly when the stream is
disabled.
Lizhi Hou [Fri, 7 Nov 2025 18:10:50 +0000 (10:10 -0800)]
accel/amdxdna: Fix deadlock between context destroy and job timeout
Hardware context destroy function holds dev_lock while waiting for all jobs
to complete. The timeout job also needs to acquire dev_lock, this leads to
a deadlock.
Fix the issue by temporarily releasing dev_lock before waiting for all
jobs to finish, and reacquiring it afterward.
Lizhi Hou [Fri, 7 Nov 2025 18:11:15 +0000 (10:11 -0800)]
accel/amdxdna: Clear mailbox interrupt register during channel creation
The mailbox interrupt register is not always cleared when a mailbox channel
is created. This can leave stale interrupt states from previous operations.
Fix this by explicitly clearing the interrupt register in the mailbox
channel creation function.
drm/imx/ipuv3: Fix dumb-buffer allocation for non-RGB formats
Align pitch to multiples of 8 pixels for bpp values that do not map
to RGB formats. The call to drm_driver_color_mode_format() fails with
DRM_INVALID_FORMAT in these cases. Fall back to manually computing
the pitch alignment from which drm_mode_size_dumb() can compute the
correct pitch.
Fixes userspace that allocates dumb buffers for YUV formats, where
bpp equals 12. A common example is the IGT kms_getfb test.
v2:
- ignore width in calculation
Suggested-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com> Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de> Fixes: b1d0e470f881 ("drm/imx/ipuv3: Compute dumb-buffer sizes with drm_mode_size_dumb()") Cc: Thomas Zimmermann <tzimmermann@suse.de> Cc: Philipp Zabel <p.zabel@pengutronix.de> Cc: Shawn Guo <shawnguo@kernel.org> Cc: Sascha Hauer <s.hauer@pengutronix.de> Cc: Pengutronix Kernel Team <kernel@pengutronix.de> Cc: Fabio Estevam <festevam@gmail.com> Cc: dri-devel@lists.freedesktop.org Cc: imx@lists.linux.dev Cc: linux-arm-kernel@lists.infradead.org Tested-by: Philipp Zabel <p.zabel@pengutronix.de> Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de> Link: https://patch.msgid.link/20251104153832.189666-1-tzimmermann@suse.de
Michal Wajdeczko [Wed, 12 Nov 2025 12:44:08 +0000 (13:44 +0100)]
drm/xe/pf: Use migration-friendly GGTT auto-provisioning
Instead of trying very hard to find the largest fair GGTT size that
could be allocated for VFs on the current tile, pick some smaller
rounded down to power-of-two value that is more likely to be
provisioned in the same manner by the other PF instance:
Note that due to FW/HW limitations we can't share all 4GiB GGTT
address space with VFs, so for the larger (>7) number of the VFs
the change in the outcome is happening at different points than
we have in case of GuC contexts/doorbells IDs.
Michał Winiarski [Wed, 12 Nov 2025 13:22:20 +0000 (14:22 +0100)]
drm/intel/bmg: Allow device ID usage with single-argument macros
When INTEL_BMG_G21_IDS were added as a subplatform, token concatenation
operator usage was omitted, making INTEL_BMG_IDS not usable with
single-argument macros.
Fix that by adding the missing operator.
Michał Winiarski [Wed, 12 Nov 2025 13:22:19 +0000 (14:22 +0100)]
drm/xe/pf: Add wait helper for VF FLR
VF FLR requires additional processing done by PF driver.
The processing is done after FLR is already finished from PCIe
perspective.
In order to avoid a scenario where migration state transitions while
PF processing is still in progress, additional synchronization
point is needed.
Add a helper that will be used as part of VF driver struct
pci_error_handlers .reset_done() callback.
Lukasz Laguna [Wed, 12 Nov 2025 13:22:17 +0000 (14:22 +0100)]
drm/xe/migrate: Add function to copy of VRAM data in chunks
Introduce a new function to copy data between VRAM and sysmem objects.
The existing xe_migrate_copy() is tailored for eviction and restore
operations, which involves additional logic and operates on entire
objects.
The xe_migrate_vram_copy_chunk() allows copying chunks of data to or
from a dedicated buffer object, which is essential in case of VF
migration.
Michał Winiarski [Wed, 12 Nov 2025 13:22:13 +0000 (14:22 +0100)]
drm/xe/pf: Add helpers for VF GGTT migration data handling
In an upcoming change, the VF GGTT migration data will be handled as
part of VF control state machine. Add the necessary helpers to allow the
migration data transfer to/from the HW GGTT resource.
Michał Winiarski [Wed, 12 Nov 2025 13:22:11 +0000 (14:22 +0100)]
drm/xe/pf: Switch VF migration GuC save/restore to struct migration data
In upcoming changes, the GuC VF migration data will be handled as part
of separate SAVE/RESTORE states in VF control state machine.
Now that the data is decoupled from both guc_state debugfs and PAUSE
state, we can safely remove the struct xe_gt_sriov_state_snapshot and
modify the GuC save/restore functions to operate on struct
xe_sriov_migration_data.
Michał Winiarski [Wed, 12 Nov 2025 13:22:10 +0000 (14:22 +0100)]
drm/xe/pf: Don't save GuC VF migration data on pause
In upcoming changes, the GuC VF migration data will be handled as part
of separate SAVE/RESTORE states in VF control state machine.
Remove it from PAUSE state.
Michał Winiarski [Wed, 12 Nov 2025 13:22:09 +0000 (14:22 +0100)]
drm/xe/pf: Remove GuC migration data save/restore from GT debugfs
In upcoming changes, SR-IOV VF migration data will be extended beyond
GuC data and exported to userspace using VFIO interface (with a
vendor-specific variant driver) and a device-level debugfs interface.
Remove the GT-level debugfs.
Michał Winiarski [Wed, 12 Nov 2025 13:22:08 +0000 (14:22 +0100)]
drm/xe/pf: Increase PF GuC Buffer Cache size and use it for VF migration
Contiguous PF GGTT VMAs can be scarce after creating VFs.
Increase the GuC buffer cache size to 8M for PF so that we can fit GuC
migration data (which currently maxes out at just over 4M) and use the
cache instead of allocating fresh BOs.
Michał Winiarski [Wed, 12 Nov 2025 13:22:07 +0000 (14:22 +0100)]
drm/xe: Allow the caller to pass guc_buf_cache size
An upcoming change will use GuC buffer cache as a place where GuC
migration data will be stored, and the memory requirement for that is
larger than indirect data.
Allow the caller to pass the size based on the intended usecase.
Michał Winiarski [Wed, 12 Nov 2025 13:22:06 +0000 (14:22 +0100)]
drm/xe: Add sa/guc_buf_cache sync interface
In upcoming changes the cached buffers are going to be used to read data
produced by the GuC. Add a counterpart to flush, which synchronizes the
CPU-side of suballocation with the GPU data and propagate the interface
to GuC Buffer Cache.
Michał Winiarski [Wed, 12 Nov 2025 13:22:04 +0000 (14:22 +0100)]
drm/xe/pf: Add minimalistic migration descriptor
The descriptor reuses the KLV format used by GuC and contains metadata
that can be used to quickly fail migration when source is incompatible
with destination.
Michał Winiarski [Wed, 12 Nov 2025 13:22:03 +0000 (14:22 +0100)]
drm/xe/pf: Add support for encap/decap of bitstream to/from packet
Add debugfs handlers for migration state and handle bitstream
.read()/.write() to convert from bitstream to/from migration data
packets.
As descriptor/trailer are handled at this layer - add handling for both
save and restore side.
Michał Winiarski [Wed, 12 Nov 2025 13:22:02 +0000 (14:22 +0100)]
drm/xe/pf: Add helpers for migration data packet allocation / free
Now that it's possible to free the packets - connect the restore
handling logic with the ring.
The helpers will also be used in upcoming changes that will start
producing migration data packets.
Michał Winiarski [Wed, 12 Nov 2025 13:22:01 +0000 (14:22 +0100)]
drm/xe/pf: Add data structures and handlers for migration rings
Migration data is queued in a per-GT ptr_ring to decouple the worker
responsible for handling the data transfer from the .read() and .write()
syscalls.
Add the data structures and handlers that will be used in future
commits.
Michał Winiarski [Wed, 12 Nov 2025 13:21:59 +0000 (14:21 +0100)]
drm/xe/pf: Convert control state to bitmap
In upcoming changes, the number of states will increase as a result of
introducing SAVE and RESTORE states.
This means that using unsigned long as underlying storage won't work on
32-bit architectures, as we'll run out of bits.
Use bitmap instead.
Reported-by: kernel test robot <lkp@intel.com> Closes: https://lore.kernel.org/oe-kbuild-all/202510231918.XlOqymLC-lkp@intel.com/ Reviewed-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Link: https://patch.msgid.link/20251112132220.516975-4-michal.winiarski@intel.com Signed-off-by: Michał Winiarski <michal.winiarski@intel.com>
Michał Winiarski [Wed, 12 Nov 2025 13:21:58 +0000 (14:21 +0100)]
drm/xe: Move migration support to device-level struct
Upcoming changes will allow users to control VF state and obtain its
migration data with a device-level granularity (not tile/gt).
Change the data structures to reflect that and move the GT-level
migration init to happen after device-level init.
Michał Winiarski [Wed, 12 Nov 2025 13:21:57 +0000 (14:21 +0100)]
drm/xe/pf: Remove GuC version check for migration support
Since commit 4eb0aab6e4434 ("drm/xe/guc: Bump minimum required GuC
version to v70.29.2"), the minimum GuC version required by the driver
is v70.29.2, which should already include everything that we need for
migration.
Remove the version check.
Jonathan Cavitt [Tue, 4 Nov 2025 16:41:51 +0000 (16:41 +0000)]
drm/i915/display: Add default case to mipi_exec_send_packet
Add a default case to the switch case statement in mipi_exec_send_packet
to prevent attempts to read an uninitialized ret value. It's unlikely
the default case will ever occur during regular exeuction, but if more
MIPI DSI Processor-to-Peripheral transaction types are ever added, then
having this in place will be a useful safety guard.
Signed-off-by: Jonathan Cavitt <jonathan.cavitt@intel.com> Fixes: 23db1577ce2d ("drm/i915/dsi: log send packet sequence errors") Reviewed-by: Jani Nikula <jani.nikula@intel.com> Link: https://patch.msgid.link/20251104164150.16795-2-jonathan.cavitt@intel.com Signed-off-by: Jani Nikula <jani.nikula@intel.com>
Sk Anirban [Wed, 12 Nov 2025 18:51:55 +0000 (00:21 +0530)]
drm/xe/guc: Eliminate RPe caching for SLPC parameter handling
RPe is runtime-determined by PCODE and caching it caused stale values,
leading to incorrect GuC SLPC parameter settings.
Drop the cached rpe_freq field and query fresh values from hardware
on each use to ensure GuC SLPC parameters reflect current RPe.
v2: Remove cached RPe frequency field (Rodrigo)
v3: Remove extra variable (Vinay)
Modify function name (Vinay)
v4: Maintain a separate function for PVC (Rodrigo)
v5: Avoid RPn update while fetching RPe frequency (Rodrigo)
v6: Split platform-specific RPe comments (Vinay)
Ville Syrjälä [Fri, 7 Nov 2025 18:11:24 +0000 (20:11 +0200)]
drm/i915: Use mode_config->cursor_width for cursor DDB allocation
Replace the hardcoded 256 with mode_config->cursor_width
when doing the cursor DDB allocation. Currently 256 is correct
for all SKL+, but this might change in the future. One less place
to change should that happen.
Ville Syrjälä [Fri, 7 Nov 2025 18:11:23 +0000 (20:11 +0200)]
drm/i915/wm: Use drm_get_format_info() in SKL+ cursor DDB allocation
Replace the technically inaccurate drm_format_info() with the
accurate drm_get_format_info() in the SKL+ cursor DDB
allocation code.
Since we're only interested in the linear modifier here, the two
functions do actually return the same information. But let's not
use drm_format_info() to avoid setting a bad example.
Ville Syrjälä [Fri, 7 Nov 2025 18:11:22 +0000 (20:11 +0200)]
drm/i915/fb: Init 'ret' in each error branch in intel_framebuffer_init()
Make the order of things a bit less fragile in
intel_framebuffer_init() by assigning 'ret' in each
error branch instead of depending on some earlier
assignment.
Ville Syrjälä [Fri, 7 Nov 2025 18:11:21 +0000 (20:11 +0200)]
drm/i915: Nuke intel_plane_config.tiling
Use intel_fb_modifier_to_tiling() to convert the modifier into
the fence tiling mode during BIOS FB readout, rather than hand
rolling it. With this we can also stop tracking the tiling mode
in the intel_plane_config.
Ville Syrjälä [Fri, 7 Nov 2025 18:11:20 +0000 (20:11 +0200)]
drm/i915: Populate fb->format accurately in BIOS FB readout
Use drm_get_format_info() instead of drm_format_info() to populate
fb->format during the BIOS FB readout. The difference being that
drm_get_format_info() knows about compressed formats whereas
drm_format_info() doesn't.
This doesn't actually matter in practice since the BIOS FB should
never be compressed, but no reason we shouldn't use the more accurate
function here anyway.
Ville Syrjälä [Fri, 7 Nov 2025 18:11:19 +0000 (20:11 +0200)]
drm/i915: Pass drm_format_info into plane->max_stride()
Pass the format info into plane->max_stride() from the
caller instead of doing yet another drm_format_info()
lookup on the spot.
drm_format_info() is both rather expensive, and technically
incorrect since it doesn't return the correct format info
for compressed formats (though that doesn't actually matter
for the current .max_stride() implementations since they
are just interested in the cpp value).
Most callers already have the format info available. The
only exception is intel_dumb_fb_max_stride() where we shall
use the actually correct drm_get_format_info() variant.
Ville Syrjälä [Fri, 7 Nov 2025 18:11:18 +0000 (20:11 +0200)]
drm/i915: Introduce intel_dumb_fb_max_stride()
Wrap intel_plane_fb_max_stride() in intel_dumb_fb_max_stride()
for the purposes of dumb fb creation. I want to change
intel_plane_fb_max_stride() to take a 'struct drm_format_info'
instead of the 'u32 pixel_format' so we need an excplicit format
info lookup in the dumb fb path and I don't really want to have
that in i915_gem_dumb_create() directly.
This makes intel_plane_fb_max_stride() internal to the display
code again, and thus we can pass in struct intel_display instead
of struct drm_device.
Timur Tabi [Fri, 10 Oct 2025 22:39:57 +0000 (17:39 -0500)]
drm/nouveau: fully define nvfw_hs_load_header_v2
Add the missing fields of the nvfw_hs_load_header_v2 struct, so that the
struct matches the actual contents of the firmware images.
nvfw_hs_load_header_v2 is a struct that defines a header for some firmware
images used by Nouveau. The current structure definition is incomplete;
it omits the last two fields because they are unused.
To maintain consistency between Nouveau, OpenRM, and Nova, and to
make it easier to support possible future images, we should fully define
the struct. Also add a __counted_by tag for the flex array.
Mohamed Ahmed [Mon, 10 Nov 2025 15:33:00 +0000 (16:33 +0100)]
drm/nouveau/drm: Bump the driver version to 1.4.1 to report new features
The HW can only do compression on large and huge pages, and enabling it on
4K pages leads to a MMU fault. Compression also needs kernel support for
handling the compressed kinds and managing the compression tags.
This increments the nouveau version number which allows NVK to enable it
only when the kernel actually supports both features and avoid breaking
the system if a newer mesa version is paired with an older kernel version.
For the associated userspace MR, please see !36450:
https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/36450
Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mary Guillemard <mary@mary.zone> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-5-83b05475f57c@mary.zone
Ben Skeggs [Mon, 10 Nov 2025 15:32:59 +0000 (16:32 +0100)]
drm/nouveau/mmu/tu102: Add support for compressed kinds
Allow compressed PTE kinds to be written into PTEs when GSP-RM is
present, rather than reverting to their non-compressed versions.
Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mary Guillemard <mary@mary.zone> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-4-83b05475f57c@mary.zone
Ben Skeggs [Mon, 10 Nov 2025 15:32:58 +0000 (16:32 +0100)]
drm/nouveau/mmu/gp100: Remove unused/broken support for compression
From GP100 onwards it's not possible to initialise comptag RAM without
PMU firmware, which nouveau has no support for.
As such, this code is essentially a no-op and will always revert to the
equivalent non-compressed kind due to comptag allocation failure. It's
also broken for the needs of VM_BIND/Vulkan.
Remove the code entirely to make way for supporting compression on GPUs
that support GSM-RM.
Signed-off-by: Ben Skeggs <bskeggs@nvidia.com> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mary Guillemard <mary@mary.zone> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-3-83b05475f57c@mary.zone
Mary Guillemard [Mon, 10 Nov 2025 15:32:57 +0000 (16:32 +0100)]
drm/nouveau/uvmm: Allow larger pages
Now that everything in UVMM knows about the variable page shift, we can
select larger values.
The proposed approach relies on nouveau_bo::page unless if it would cause
alignment issues (in which case we fall back to searching for an
appropriate shift)
Signed-off-by: Mary Guillemard <mary@mary.zone> Co-developed-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-2-83b05475f57c@mary.zone
Mary Guillemard [Mon, 10 Nov 2025 15:32:56 +0000 (16:32 +0100)]
drm/nouveau/uvmm: Prepare for larger pages
Currently memory allocated by VM_BIND uAPI can only have a granuality
matching PAGE_SIZE (4KiB in common case)
To have a better memory management and to allow big (64KiB) and huge
(2MiB) pages later in the series, we are now passing the page shift all
around the internals of UVMM.
Signed-off-by: Mary Guillemard <mary@mary.zone> Co-developed-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Signed-off-by: Mohamed Ahmed <mohamedahmedegypt2001@gmail.com> Reviewed-by: Lyude Paul <lyude@redhat.com> Reviewed-by: James Jones <jajones@nvidia.com> Signed-off-by: Lyude Paul <lyude@redhat.com> Link: https://patch.msgid.link/20251110-nouveau-compv6-v6-1-83b05475f57c@mary.zone
drm/xe/pf: Allow to lockdown the PF using custom guard
Some driver components, like eudebug or ccs-mode, can't be used
when VFs are enabled. Add functions to allow those components
to block the PF from enabling VFs for the requested duration.
Introduce trivial counter to allow lockdown or exclusive access
that can be used in the scenarios where we can't follow the strict
owner semantics as required by the rw_semaphore implementation.
Before enabling VFs, the PF will try to arm the "vfs_enabling"
guard for the exclusive access. This will fail if there are
some lockdown requests already initiated by the other components.
For testing purposes, add debugfs file which will call these new
functions from the file's open/close hooks.
Signed-off-by: Michal Wajdeczko <michal.wajdeczko@intel.com> Cc: Matthew Brost <matthew.brost@intel.com> Cc: Christoph Manszewski <christoph.manszewski@intel.com> Reviewed-by: Christoph Manszewski <christoph.manszewski@intel.com> Link: https://patch.msgid.link/20251109162451.4779-1-michal.wajdeczko@intel.com
Lucas De Marchi [Mon, 10 Nov 2025 16:41:08 +0000 (08:41 -0800)]
drm/xe/pcode: Rework error mapping
The sparse array used for error decoding from is unnecessarily big. It
should be better handled by a switch statement that will also allow us
to more easily improve this code.
Add a CASE_ERR() macro to keep the table compact and use it instead of
the 256-entries array, which saves some space:
Kriish Sharma [Mon, 10 Nov 2025 18:42:06 +0000 (18:42 +0000)]
drm/xe: fix kernel-doc function name mismatch in xe_pm.c
Documentation build reported:
WARNING: ./drivers/gpu/drm/xe/xe_pm.c:131 expecting prototype for xe_pm_might_block_on_suspend(). Prototype was for xe_pm_block_on_suspend() instead
The kernel-doc comment for xe_pm_block_on_suspend() incorrectly used
the function name xe_pm_might_block_on_suspend(). Fix the header to
match the actual function prototype.
drm/tidss: Move OLDI mode validation to OLDI bridge mode_valid hook
After integrating OLDI support[0], it is necessary to identify which VP
instances use OLDI, since the OLDI driver owns the video port clock
(as a serial clock). Clock operations on these VPs must be delegated to
the OLDI driver, not handled by the TIDSS driver. This issue also
emerged in upstream discussions when DSI-related clock management was
attempted in the TIDSS driver[1].
To address this, add an 'is_ext_vp_clk' array to the 'tidss_device'
structure, marking a VP as 'true' during 'tidss_oldi_init()' and as
'false' during 'tidss_oldi_deinit()'. TIDSS then uses 'is_ext_vp_clk'
to skip clock validation checks in 'dispc_vp_mode_valid()' for VPs
under OLDI control.
Since OLDI uses the DSS VP clock directly as a serial interface and
manages its own rate, mode validation should be implemented in the OLDI
bridge's 'mode_valid' hook. This patch adds that logic, ensuring proper
delegation and avoiding spurious clock handling in the TIDSS driver.
drm/tidss: Remove max_pclk_khz and min_pclk_khz from tidss display features
The TIDSS hardware does not have independent maximum or minimum pixel
clock limits for each video port. Instead, these limits are determined
by the SoC's clock architecture. Previously, this constraint was
modeled using the 'max_pclk_khz' and 'min_pclk_khz' fields in
'dispc_features', but this approach is static and does not account for
the dynamic behavior of PLLs.
This patch removes the 'max_pclk_khz' and 'min_pclk_khz' fields from
'dispc_features'. The correct way to check if a requested mode's pixel
clock is supported is by using 'clk_round_rate()' in the 'mode_valid()'
hook. If the best frequency match for the mode clock falls within the
supported tolerance, it is approved. TIDSS supports a 5% pixel clock
tolerance, which is now reflected in the validation logic.
This change allows existing DSS-compatible drivers to be reused across
SoCs that only differ in their pixel clock characteristics. The
validation uses 'clk_round_rate()' for each mode, which may introduce
additional delay (about 3.5 ms for 30 modes), but this is generally
negligible. Users desiring faster validation may bypass these calls
selectively, for example, checking only the highest resolution mode,
as shown here[1].
Jernej Skrabec [Tue, 4 Nov 2025 18:09:39 +0000 (19:09 +0100)]
drm/sun4i: mixer: split out layer config
Later special plane only driver for DE33 will provide separate
configuration. This change will also help layer driver migrate away from
mixer structure.
Jernej Skrabec [Tue, 4 Nov 2025 18:09:38 +0000 (19:09 +0100)]
drm/sun4i: mixer: Add quirk for number of VI scalers
On DE2 and DE3, UI scalers are located right after VI scalers. So in
order to calculate proper UI scaler base address, number of VI scalers
must be known. In practice, it is same as number of VI channels, but it
doesn't need to be.
Let's make a quirk for this number. Code for configuring channels and
associated functions won't have access to vi_num quirk anymore after
rework for independent planes.
Jernej Skrabec [Tue, 4 Nov 2025 18:09:37 +0000 (19:09 +0100)]
drm/sun4i: ui_scaler: drop sanity checks
They can't be triggered if mixer configuration is properly specified in
quirks. Additionally, number of VI channels won't be available in future
due to rework for DE33 support.
Jernej Skrabec [Tue, 4 Nov 2025 18:09:36 +0000 (19:09 +0100)]
drm/sun4i: mixer: Convert heuristics to quirk
Determination if FCC unit can be used for VI layer alpha depends on
number of VI channels. This info won't be available anymore in future
to VI layer driver because of DE33 way of allocating planes from same
pool to different mixers.
While order is slightly changed, it doesn't affect anything due to
double buffering of registers. New order keeps related registers
together and quirk separate.
Jernej Skrabec [Tue, 4 Nov 2025 18:09:35 +0000 (19:09 +0100)]
drm/sun4i: vi_scaler: Update DE33 base calculation
Now that channel base calculation is straightforward, let's update VI
scaler base calculation to be simpler. At the same time, also introduce
macro to avoid magic numbers.
Note, reason why current magic value and new macro value isn't the same
is because sun8i_channel_base() already introduces offset to channel
registers. Previous value is just the difference to VI scaler registers.
However, new code calculates scaler base from channel base. This is also
easier to understand when looking into BSP driver. Macro value can be
easily found whereas old diff value was not.
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