Merge tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx into soc/dt
ARM: nxp: lpc: device tree updates for v6.18
This pull request contains device tree changes for ARM NXP LPC32xx and
ARM NXP LPC18xx/LPC43xx for v6.18, please pull the following:
- Frank fixes a multitude of device tree checker warnings reported for
NXP LPC18xx/LPC43xx powered boards,
- Vladimir fixes a number of compile time warnings issued by a dt checker
for NXP LPC32xx powered boards,
- Vladimir replaces Roland as a maintainer of NXP LPC32xx platform
device trees, Roland is inactive for more than 10 years.
* tag 'lpc32xx-dt-for-6.18' of https://github.com/vzapolskiy/linux-lpc32xx:
ARM: dts: lpc32xx: Correct PL080 DMA controller device node name
ARM: dts: lpc32xx: Specify #dma-cells property of PL080 DMA controller
ARM: dts: lpc32xx: Specify a precise version of the SD/MMC controller IP
ARM: dts: lpc32xx: Correct SD/MMC controller device node name
ARM: dts: lpc32xx: Correct motor PWM device tree node name
ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
ARM: dts: lpc18xx: add missed arm,num-irq-priority-bits
ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller
ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio
ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]'
ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92
ARM: dts: lpc: add cfg surfix in pinctrl child node
ARM: dts: lpc: add #address-cells and #size-cells for sram node
ARM: dts: lpc18xx: swap clock-names bic and cui
ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0
ARM: dts: lpc18xx: rename node name mmcsd to mmc
ARM: dts: lpc18xx: rename node name flash-controller to spi
Merge tag 'arm-soc/for-6.18/devicetree' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM SoC Device Tree changes for
6.18, please pull the following:
- Taishi-san adds support for the Buffalo WXR-1750DHP using a BCM4708
SoC
* tag 'arm-soc/for-6.18/devicetree' of https://github.com/Broadcom/stblinux:
ARM: dts: BCM5301X: Add support for Buffalo WXR-1750DHP
dt-bindings: arm: bcm: Add support for Buffalo WXR-1750DHP
Merge tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux into soc/dt
This pull request contains Broadcom ARM64-based SoCs Device Tree updates
for 6.18, please pull the following:
- Krzysztof fixes a DTC warning for the ARM GIC in bcm2712.dtsi
- Ivan adds the pin controller node(s), an additional GPIO controller,
the second SDHCI controller node for SDIO Wi-Fi, and the UARTA for
Bluetooth to the BCM2712 DTS (Raspberry Pi 5)
- Stanimir adds the Ethernet DT node and enables it for the RP1 sister
chip
- Andrea deletes a number of redundant PCIe DT node enablement, updates
a comment to describe the relationship between bcm2712 and RP1 and
finally enables the USB controllers with RP1
* tag 'arm-soc/for-6.18/devicetree-arm64' of https://github.com/Broadcom/stblinux:
arm64: dts: broadcom: Enable USB devicetree entries for Rpi5
arm64: dts: broadcom: rp1: Add USB nodes
arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTS
arm64: dts: broadcom: delete redundant pcie enablement nodes
arm64: dts: broadcom: Enable RP1 ethernet for Raspberry Pi 5
arm64: dts: rp1: Add ethernet DT node
dt-bindings: mmc: Add support for capabilities to Broadcom SDHCI controller
arm64: dts: broadcom: bcm2712: Add UARTA controller node
arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
arm64: dts: broadcom: bcm2712: Add one more GPIO node
arm64: dts: broadcom: bcm2712: Add pin controller nodes
arm64: dts: broadcom: bcm2712: Add default GIC address cells
Merge tag 'samsung-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM changes for v6.18
1. Drop S3C2416 SoC from bindings, because it was removed from kernel
in 2023.
2. Add Ethernet attached via SROM controller (memory bus) on SMDK5250.
This wasn't tested, but code should work just like it is working on
Exynos5410-based boards.
* tag 'samsung-dt-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
ARM: dts: samsung: smdk5250: add sromc node
ARM: dts: samsung: exynos5250: describe sromc bank memory map
ARM: dts: samsung: exynos5410: use multiple tuples for sromc ranges
dt-bindings: arm: samsung: Drop S3C2416
Merge tag 'samsung-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into soc/dt
Samsung DTS ARM64 changes for v6.18
1. Exynos850 e850 board: Enable Ethernet.
2. Exynos990: Enable watchdog and USB, add more clock controllers.
3. Exynos2200: Switch to 32-bit address space for blocks, because all
peripherals fit there. Add remaining serial engine (USI) nodes
(serial, I2C).
4. New Artpec ARTPEC-8 SoC with board. That's a design from Samsung,
sharing all basic blocks with other Samsung SoCs (busses, clock
controllers, pin controllers, PCIe, USB) and having media/video
related blocks from Axis.
Only basic support is added here: few clock controllers, pin
controller and UART.
5. Several cleanups.
* tag 'samsung-dt64-6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
arm64: dts: exynos990: Enable PERIC0 and PERIC1 clock controllers
arm64: dts: axis: Add ARTPEC-8 Grizzly dts support
arm64: dts: exynos: axis: Add initial ARTPEC-8 SoC support
dt-bindings: arm: axis: Add ARTPEC-8 grizzly board
arm64: dts: exynos8895: Minor whitespace cleanup
dt-bindings: arm: Convert Axis board/soc bindings to json-schema
arm64: dts: exynos2200: Add default GIC address cells
arm64: dts: fsd: Add default GIC address cells
arm64: dts: google: gs101: Add default GIC address cells
arm64: dts: exynos5433: Add default GIC address cells
arm64: dts: exynos2200: define all usi nodes
arm64: dts: exynos2200: increase the size of all syscons
arm64: dts: exynos2200: use 32-bit address space for /soc
arm64: dts: exynos2200: fix typo in hsi2c23 bus pins label
arm64: dts: exynos990-r8s: Enable USB
arm64: dts: exynos990-c1s: Enable USB
arm64: dts: exynos990-x1s-common: Enable USB
arm64: dts: exynos990: Add USB nodes
arm64: dts: exynos990: Enable watchdog timer
arm64: dts: exynos: Add Ethernet node for E850-96 board
Merge tag 'socfpga_dts_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into soc/dt
SoCFPGA DTS updates for v6.18
- Add and enable gmac for Agilex5
* tag 'socfpga_dts_updates_for_v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit
arm64: dts: Agilex5 Add gmac nodes to DTSI for Agilex5
Merge tag 'v6.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into soc/dt
New boards: FriendlyElec NanoPi Zero2, ArmSoM Sige1, Radxa ROCK 2A/2F,
HINLINK H66K / H68K .
Interesting new peripherals: I guess the most interesting one is likely
the NPU on RK3588. The rocket driver has been merged into both the DRM
tree as well as mainline Mesa.
Other stll interesting ones are DW-Displayport on RK3588, DSI on RK3576
(missing soc pwm-support to be useful on most boards), thermal support
and watchdog on RK3576.
The rest peripheral additions on a number of boards (Beelink A1,
Pine{phone,book}, rk3576-evb1-v10, Rock 5*, ...)
* tag 'v6.18-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (46 commits)
arm64: dts: rockchip: Enable DP2HDMI for ROCK 5 ITX
arm64: dts: rockchip: Enable DisplayPort for rk3588s Cool Pi 4B
arm64: dts: rockchip: Add DP1 for rk3588
arm64: dts: rockchip: Add DP0 for rk3588
arm64: dts: rockchip: Add FriendlyElec NanoPi Zero2
dt-bindings: arm: rockchip: Add FriendlyElec NanoPi Zero2
arm64: dts: rockchip: Add ArmSoM Sige1
dt-bindings: arm: rockchip: Add ArmSoM Sige1
arm64: dts: rockchip: Add Radxa ROCK 2A/2F
dt-bindings: arm: rockchip: Add Radxa ROCK 2A/2F
dt-bindings: soc: rockchip: add missing clock reference for rk3576-dcphy syscon
arm64: dts: rockchip: add USB3 on Beelink A1
arm64: dts: rockchip: add SPDIF audio to Beelink A1
arm64: dts: rockchip: add IR receiver to rk3328-roc
arm64: dts: rockchip: Further describe the WiFi for the Pinephone Pro
arm64: dts: rockchip: Further describe the WiFi for the Pinebook Pro
arm64: dts: rockchip: Enable the NPU on NanoPi R6C/R6S
arm64: dts: rockchip: enable NPU on OPI5/5B
arm64: dts: rockchip: Add Bluetooth on rk3576-evb1-v10
arm64: dts: rockchip: Add WiFi on rk3576-evb1-v10
...
Merge tag 'thead-dt-for-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/fustini/linux into soc/dt
T-HEAD Devicetrees for v6.18
Add a device tree node for the IMG BXM-4-64 GPU present in the T-HEAD
TH1520 SoC used by the Lichee Pi 4A board. This node enables support for
the GPU using the drm/imagination driver.
By adding this node, the kernel can recognize and initialize the GPU,
providing graphics acceleration capabilities on the Lichee Pi 4A and
other boards based on the TH1520 SoC. The display controller and HDMI
output are still a work in progress.
Also included is a MAINTAINERS patch that adds an entry for the T-Head
SoC patchwork.
ARM: dts: lpc32xx: Set motor PWM #pwm-cells property value to 3 cells
Since commit 4cd2f417a0ac ("dt-bindings: pwm: Convert lpc32xx-pwm.txt
to yaml format") both types of PWM controlles on NXP LPC32xx SoC
fairly gained 3 cells, reflect it in the platform dtsi file.
dt-bindings: arm: nxp: lpc: Assign myself as maintainer of NXP LPC32xx platforms
Make a formal change to reflect the actual NXP LPC32xx maintainership
for the last years.
Cc: Roland Stigge <stigge@antcom.de> Acked-by: Rob Herring (Arm) <robh@kernel.org> Reviewed-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Add missed arm,num-irq-priority-bits to fix below CHECK_DTBS warning:
arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: interrupt-controller@e000e100 (arm,armv7m-nvic): 'arm,num-irq-priority-bits' is a required property
from schema $id: http://devicetree.org/schemas/interrupt-controller/arm,nvic.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:47:06 +0000 (14:47 -0400)]
ARM: dts: lpc18xx: add #address-cell and #szie-cell for spi flash controller
Add #address-cells and #szie-cells for spi flash controller to fix below
CHECK_DTB warning:
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi:103.23-112.5: Warning (spi_bus_bridge): /soc/spi@40003000: incorrect #address-cells for SPI bus
also defined at arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts:452.8-479.3
arch/arm/boot/dts/nxp/lpc/lpc18xx.dtsi:103.23-112.5: Warning (spi_bus_bridge): /soc/spi@40003000: incorrect #size-cells for SPI bus
also defined at arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dts:452.8-479.3
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:47:05 +0000 (14:47 -0400)]
ARM: dts: lpc4357-myd-lpc4357: change node name mdio0 to mdio
Change node name mdio0 to mdio to fix below CHECK_DTB warning:
arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dtb: ethernet@40010000 (nxp,lpc1850-dwmac): Unevaluated properties are not allowed ('mdio0' was unexpected)
from schema $id: http://devicetree.org/schemas/net/nxp,lpc1850-dwmac.yaml
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:47:04 +0000 (14:47 -0400)]
ARM: dts: lpc: change node name 'button[0-9]' to button-[0-9]'
Change node name 'button[0-9]' to button-[0-9]' to fix below CHECK_DTB
warning:
arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: pca_buttons (gpio-keys-polled): 'button0', ... do not match any of the regexes: '^(button|...', 'pinctrl-[0-9]+'
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:47:03 +0000 (14:47 -0400)]
ARM: dts: lpc4357-myd-lpc4357: add power-supply for innolux,at070tn92
Add power-supply for innolux,at070tn92 to fix below CHECK_DTB warning:
arch/arm/boot/dts/nxp/lpc/lpc4357-myd-lpc4357.dtb: panel (innolux,at070tn92): 'power-supply' is a required property
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:47:02 +0000 (14:47 -0400)]
ARM: dts: lpc: add cfg surfix in pinctrl child node
Add cfg surfix in pinctrl child node to fix below CHECK_DTB warning:
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: pinctrl@40086000 (nxp,lpc1850-scu): ssp-pins: 'ssp1_cs', 'ssp1_miso_mosi', 'ssp1_sck' do not match any of the regexes: '^pinctrl-[0-9]+$', '_cfg$'
from schema $id: http://devicetree.org/schemas/pinctrl/nxp,lpc1850-scu.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:47:01 +0000 (14:47 -0400)]
ARM: dts: lpc: add #address-cells and #size-cells for sram node
Add #address-cells and #size-cells for sram node to fix below DTB_CHECK
warnings:
arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: sram@2,0 (mmio-sram): '#address-cells' is a required property
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:46:59 +0000 (14:46 -0400)]
ARM: dts: lpc4350-hitex-eval: change node name flash to flash@0
Change node name 'flash' to 'flash@0' to fix below CHECK_DTB warnings.
arch/arm/boot/dts/nxp/lpc/lpc4350-hitex-eval.dtb: flash-controller@40003000 (nxp,lpc1773-spifi): Unevaluated properties are not allowed ('flash' was unexpected)
from schema $id: http://devicetree.org/schemas/mtd/nxp,lpc1773-spifi.yaml#
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:46:58 +0000 (14:46 -0400)]
ARM: dts: lpc18xx: rename node name mmcsd to mmc
Change node name mmcsd to mmc to fix CHECK_DTB warnings:
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: mmcsd@40004000 (snps,dw-mshc): $nodename:0: 'mmcsd@40004000' does not match '^mmc(@.*)?$'
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Frank Li [Sun, 6 Jul 2025 18:46:57 +0000 (14:46 -0400)]
ARM: dts: lpc18xx: rename node name flash-controller to spi
Anyway it is SPI controller although intent to connect qspi flash.
Rename node name flash-controller to spi to fix below CHECK_DTB warning:
arch/arm/boot/dts/nxp/lpc/lpc4337-ciaa.dtb: flash-controller@40003000 (nxp,lpc1773-spifi): $nodename:0: 'flash-controller@40003000' does not match '^spi(@.*|-([0-9]|[1-9][0-9]+))?$
Signed-off-by: Frank Li <Frank.Li@nxp.com> Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
Add device tree bindings support for the Grinn GenioSBC-510, a
single-board computer based on the MediaTek Genio 510 SoC.
More details about the hardware:
- https://grinn-global.com/products/grinn-geniosom-510
- https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc
Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250908130620.2309399-5-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Add device tree bindings support for the Grinn GenioSBC-700, a
single-board computer based on the MediaTek Genio 700 SoC.
More details about the hardware:
- https://grinn-global.com/products/grinn-geniosom-700
- https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc
Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250908130620.2309399-3-mateusz.koza@grinn-global.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arm64: dts: mediatek: mt7988a-bpi-r4: configure switch phys and leds
Assign pinctrl to switch phys and leds.
Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250709111147.11843-14-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arm64: dts: mediatek: mt7988a-bpi-r4: add sfp cages and link to gmac
Add SFP cages to Bananapi-R4 board. The 2.5g phy variant only contains the
wan-SFP, so add this to common dtsi and the lan-sfp only to the dual-SFP
variant.
Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250709111147.11843-13-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arm64: dts: mediatek: mt7988a-bpi-r4: add aliases for ethernet
Add aliases for gmacs to allow bootloader setting mac-adresses.
Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250709111147.11843-12-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Signed-off-by: Daniel Golle <daniel@makrotopia.org> Signed-off-by: Frank Wunderlich <frank-w@public-files.de> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250709111147.11843-11-linux@fw-web.de Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arm64: dts: mediatek: add thermal sensor support on mt7981
The temperature sensor in the MT7981 is same as in the MT7986.
Signed-off-by: Aleksander Jan Bajkowski <olek2@wp.pl> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Link: https://lore.kernel.org/r/20250907111742.23195-2-olek2@wp.pl Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
arm64: dts: mediatek: mt8395-nio-12l: add PMIC and GPIO keys support
Add support for PMIC and GPIO keys on the Radxa NIO 12L board:
Declare a gpio-keys node for the Volume Up button using GPIO106.
Add the corresponding pin configuration in the pinctrl node.
Add a mediatek,mt6359-keys subnode under the PMIC to handle the
power and home buttons exposed by the MT6359.
arm64: dts: mediatek: mt8183: Fix out of range pull values
A value of 10 is not valid for "mediatek,pull-down-adv" and
"mediatek,pull-up-adv" properties which have defined values of 0-3. It
appears the "10" was written as a binary value. The driver only looks at
the lowest 2 bits, so the value "10" decimal works out the same as if
"2" was used.
arm64: dts: mediatek: mt8195: Remove suspend-breaking reset from pcie0
When test suspend resume with 6.8 based kernel, system can't resume
and I got below error which can be also reproduced with 6.16 rc6+
kernel.
mtk-pcie-gen3 112f0000.pcie: PCIe link down, current LTSSM state: detect.quiet (0x0)
mtk-pcie-gen3 112f0000.pcie: PM: dpm_run_callback(): genpd_resume_noirq returns -110
mtk-pcie-gen3 112f0000.pcie: PM: failed to resume noirq: error -110
After investigation, looks pcie0 has the same problem as pcie1 as
decribed in commit 3d7fdd8e38aa ("arm64: dts: mediatek: mt8195:
Remove suspend-breaking reset from pcie1").
Fixes: ecc0af6a3fe6 ("arm64: dts: mt8195: Add pcie and pcie phy nodes") Signed-off-by: Guoqing Jiang <guoqing.jiang@canonical.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Link: https://lore.kernel.org/r/20250721095959.57703-1-guoqing.jiang@canonical.com Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
Henrik Grimler [Mon, 8 Sep 2025 07:26:56 +0000 (09:26 +0200)]
ARM: dts: samsung: exynos5250: describe sromc bank memory map
According to public user manual for Exynos 5250 [1], the SROM
controller has 4 banks, at same addresses as for example Exynos
5410. Describe the bank memory map of the SoC.
Henrik Grimler [Mon, 8 Sep 2025 07:26:55 +0000 (09:26 +0200)]
ARM: dts: samsung: exynos5410: use multiple tuples for sromc ranges
Preferred style is to have comma separated tuples when multiple
addresses and sizes are defined in ranges. Therefore, change the
format to clarify the node.
Signed-off-by: Henrik Grimler <henrik@grimler.se> Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
arm64: dts: broadcom: amend the comment about the role of BCM2712 board DTS
Current board DTS for Raspberry Pi5 states that bcm2712-rpi-5-b.dts
should not be modified and all declarations should go in the overlay
board DTS instead (bcm2712-rpi-5-b-ovl-rp1.dts).
There's a caveat though: there's currently no infrastructure to reliably
reference nodes that have not been declared yet, as is the case when
loading those nodes from a runtime overlay. For more details about
these limitations see [1] and follow-ups.
Change the comment to make it clear which DTS file will host specific
nodes, especially the RP1 related nodes which should be customized
outside the overlay DTS.
Link
[1] - https://lore.kernel.org/all/CAMEGJJ3=W8_R0xBvm8r+Q7iExZx8xPBHEWWGAT9ngpGWDSKCaQ@mail.gmail.com/
The pcie1 and pcie2 override nodes to enable the respective peripherals are
declared both in bcm2712-rpi-5-b.dts and bcm2712-rpi-5-b-ovl-rp1.dts, which
makes those declared in the former file redundant.
Drop those redundant nodes from the board devicetree.
On RPi5 device Bluetooth chips is connected to UARTA
port. Add Bluetooth chips and related pin definitions.
With this and firmware already provided by distributions,
at least on openSUSE Tumbleweed, this is sufficient to make
Bluetooth operational on RPi5 \o/.
Ivan T. Ivanov [Thu, 28 Aug 2025 13:17:13 +0000 (15:17 +0200)]
arm64: dts: broadcom: bcm2712: Add second SDHCI controller node
Add SDIO2 node. On RPi5 it is connected to WiFi chip.
Add related pin, gpio and regulator definitions and
add WiFi node. With this and firmware already provided by
distributions, at least on openSUSE Tumbleweed, this is
sufficient to make WiFi operational on RPi5 \o/.
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
tmpv7708.dtsi:503.4-507.28: Warning (interrupt_map): /soc/pcie@28400000:interrupt-map:
Missing property '#address-cells' in node /soc/interrupt-controller@24001000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0)
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
alpine-v3.dtsi:342.4-349.33: Warning (interrupt_map): /soc/pcie@fbd00000:interrupt-map:
Missing property '#address-cells' in node /soc/interrupt-controller@f0800000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0)
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
alpine-v2.dtsi:138.4-139.33: Warning (interrupt_map): /soc/pci@fbc00000:interrupt-map:
Missing property '#address-cells' in node /soc/interrupt-controller@f0200000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0)
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
apm-storm.dtsi:636.4-639.42: Warning (interrupt_map): /soc/pcie@1f2b0000:interrupt-map:
Missing property '#address-cells' in node /interrupt-controller@78010000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0)
Document the Axis ARTPEC-8 SoC binding and the grizzly board
which uses ARTPEC-8 SoC.
Signed-off-by: SungMin Park <smn1196@coasia.com> Signed-off-by: SeonGu Kang <ksk4725@coasia.com> Signed-off-by: Ravi Patel <ravi.patel@samsung.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20250901051926.59970-4-ravi.patel@samsung.com Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
bcm2712.dtsi:494.4-497.31: Warning (interrupt_map): /axi/pcie@1000110000:interrupt-map:
Missing property '#address-cells' in node /soc@107c000000/interrupt-controller@7fff9000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0)
Samsung S3C24xx family of SoCs was removed from the Linux kernel in the
commit 61b7f8920b17 ("ARM: s3c: remove all s3c24xx support"), in January
2023. There are no in-kernel users of remaining S3C24xx compatibles.
Andy Yan [Fri, 22 Aug 2025 06:39:54 +0000 (14:39 +0800)]
arm64: dts: rockchip: Enable DP2HDMI for ROCK 5 ITX
The HDMI0(Port next to Headphone Jack) is driven by DP1 on rk3588
via RA620(a dp2hdmi converter).
Add related dt nodes to enable it.
Note: ROCKCHIP_VOP2_EP_DP1 is defined as 11 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address
error, expected "b"" if we use it directly after endpoint, so we
use "b" instead here.
Andy Yan [Fri, 22 Aug 2025 06:39:53 +0000 (14:39 +0800)]
arm64: dts: rockchip: Enable DisplayPort for rk3588s Cool Pi 4B
Enable the Mini DisplayPort on this board.
Note that ROCKCHIP_VOP2_EP_DP0 is defined as 10 in dt-binding header,
but it will trigger a dtc warning like "graph node unit address error,
expected "a"" if we use it directly after endpoint, so we use "a"
instead here.
Jonas Karlman [Thu, 17 Jul 2025 10:37:04 +0000 (10:37 +0000)]
arm64: dts: rockchip: Add Radxa ROCK 2A/2F
The ROCK 2A and ROCK 2F is a high-performance single board computer
developed by Radxa, based on the Rockchip RK3528A SoC.
Add initial device tree for the Radxa ROCK 2A and ROCK 2F boards.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Yao Zi <ziyao@disroot.org> Reviewed-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Tested-by: Nicolas Frattaroli <nicolas.frattaroli@collabora.com> Link: https://lore.kernel.org/r/20250717103720.2853031-3-jonas@kwiboo.se Signed-off-by: Heiko Stuebner <heiko@sntech.de>
ARM: dts: qcom: Use GIC_SPI for interrupt-map for readability
Decoding interrupt-map is tricky, because it consists of five
components. Use known GIC_SPI define in final interrupt specifier
component makes easier to read.
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
qcom-sdx55.dtsi:343.4-346.30: Warning (interrupt_map): /soc/pcie@1c00000:interrupt-map:
Missing property '#address-cells' in node /soc/interrupt-controller@17800000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
qcom-ipq8064.dtsi:1201.4-1204.29: Warning (interrupt_map): /soc/pcie@1b900000:interrupt-map:
Missing property '#address-cells' in node /soc/interrupt-controller@2000000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
qcom-apq8064.dtsi:1353.4-1356.29: Warning (interrupt_map): /soc/pcie@1b500000:interrupt-map:
Missing property '#address-cells' in node /soc/interrupt-controller@2000000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Add missing address-cells 0 to GIC interrupt node to silence W=1
warning:
qcom-ipq4019.dtsi:431.4-434.30: Warning (interrupt_map): /soc/pcie@40000000:interrupt-map:
Missing property '#address-cells' in node /soc/interrupt-controller@b000000, using 0 as fallback
Value '0' is correct because:
1. GIC interrupt controller does not have children,
2. interrupt-map property (in PCI node) consists of five components and
the fourth component "parent unit address", which size is defined by
'#address-cells' of the node pointed to by the interrupt-parent
component, is not used (=0).
Merge tag 'sti-dt-for-v6.18-round1' of https://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti into soc/dt
STi dt fixes:
- Drop STiH407/10-B2120 DT boards and bindings.
- Remove remaining STiH415/6 reference from STi machine.
- Fix phy-names value for stih407-family.dtsi.
* tag 'sti-dt-for-v6.18-round1' of https://git.kernel.org/pub/scm/linux/kernel/git/pchotard/sti:
ARM: sti: drop B2120 board support
ARM: sti: removal of stih415/stih416 related entries
dt-bindings: arm: sti: drop B2120 board support
ARM: dts: sti: rename SATA phy-names
Merge tag 'renesas-dts-for-v6.18-tag1' of https://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-devel into soc/dt
Renesas DTS updates for v6.18
- Add initial support for the RZ/T2H (R9A09G077) and RZ/N2H
(R9A09G087) SoCs and their evaluation boards,
- Add SPI support for the RZ/V2H SoC,
- Add DMAC and I3C support for the RZ/G3E SoC,
- Add I3C support for the RZ/G3S SoCs,
- Miscellaneous fixes and improvements.
Merge tag 'ux500-dts-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into soc/dt
Ux500 DTS changes for v6.18
- Fix a GPIO hog name.
- Move custom wakeup GPIO to a proper GPIO IRQ
line rising edge wakeup.
* tag 'ux500-dts-v6.18' of https://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: dts: ste-ux500-samsung: dts bluetooth wakeup interrupt
ARM: dts: st: ste-nomadik: Align GPIO hog name with bindings
Merge tag 'nuvoton-arm-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux into soc/dt
Early Nuvoton ARM devicetree updates for 6.18
So far we have just the one fix from Krzysztof that switches some nodes to use
generic names, as recommended by the spec.
* tag 'nuvoton-arm-6.18-devicetree-0' of https://git.kernel.org/pub/scm/linux/kernel/git/bmc/linux:
ARM: dts: nuvoton: Use generic "ethernet" as node name
projects / thirdparty / kernel / linux.git / log
