arm64: zynqmp: Add generic compatible string for I2C EEPROM
The at24 driver allows to register I2C EEPROM chips using different vendor
and devices, but the I2C subsystem does not take the vendor into account
when matching using the I2C table since it only has device entries.
But when matching using an OF table, both the vendor and device has to be
taken into account so the driver defines only a set of compatible strings
using the "atmel" vendor as a generic fallback for compatible I2C devices.
So add this generic fallback to the device node compatible string to make
the device to match the driver using the OF device ID table.
Signed-off-by: Javier Martinez Canillas <javier@dowhile0.org> Acked-by: Michal Simek <michal.simek@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
net: xilinx_axi_emac: Use readl and writel for io ops
This patch uses readl and writel instead of in_be32 and
out_be32 for io ops as these internally uses readl,
writel for microblaze and for Zynq, ZynqMP there is
no need of endianness conversion and readl, writel
should work straightaway. This patch starts supporting
the driver for Zynq and ZynqMP platforms.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Nathan Rossi [Tue, 14 Nov 2017 07:44:32 +0000 (17:44 +1000)]
arm64: zynqmp: Setup partid for QEMU to match silicon
During board late init the environment is 'setup' to set the partid to 0
for QEMU. Change this so that QEMU targets behave just like silicon and
emulation targets such that partid is set to auto.
Signed-off-by: Nathan Rossi <nathan@nathanrossi.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Fri, 3 Nov 2017 12:01:14 +0000 (13:01 +0100)]
arm: zynq: Fix zynq_cse_qspi testing
The patch:
"dts: zynq_cse: Add dts files for all mini u-boot qspi configurations"
(sha1: d7446e231302d82dced967598cf95fb751830bcb)
changed device tree wiring which is handling SPL configuration.
zynq_cse_qspi target is using zc706 as testing platform that's why
it is required to link zynq-cse-qspi-single with zc706 ps7_init*.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 18 Oct 2017 13:35:21 +0000 (15:35 +0200)]
arm64: zynqmp: update psu_init_gpl* files for zc1751-dc1
Origin psu_init files are not fully setup system timer (freq reg)
Issue was caused by this patch:
"arm64: zynqmp: Do not setup time if already setup"
(sha1: 20d730f8f5c85196e38896a72bfa1b2a3f6c7913)
where setting up CLKACT bit was enough for CLK detection in connection
to actual vivado version.
dpll_prog() is commented because it is not called.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: remove smmu info from lpd dma channels
ARM Linux SMMU implementation supports only 16 context banks.
To have SMMU support for all relevant peripherals, smmu information in
lpd dma channels are commented by default. Users can add back by
uncommenting the smmu info.
Keep there #stream-id-cells because stream-id-cells property is
mandatory for SMMU driver over xen.
Since just removing "iommus" property suffice to bypass SMMU over
native linux,SMMU would be still bypassed for lpd-dma over linux.
This patch adds no-1-8-v property to sdhci1 node for zcu102
and zcu106 such that SD operates at 50MHz by default. The
property no-1-8-v can be removed to operate SD at 200Mhz
mode if hw supports.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
dts: zynqmp: mini_qspi: Changes misc frequnecy to 125MHz
Change misc clock to 125MHz as this frequnecy is being used
by qspi driver and this is what we ship as a part of defaults.
This fixes the issue with Spansion parts programming.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The current authentication and device key support have
security violations as mentioned below and hence these
features have to be reverted.
- Devicekey support from Non secure software prone to DPA attack.
- Current authentication using single RSA key pair and not associated
with device which is security violation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The current authentication and device key support have
security violations as mentioned below and hence these
features have to be reverted.
- Devicekey support from Non secure software prone to DPA attack.
- Current authentication using single RSA key pair and not associated
with device which is security violation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The current authentication and device key support have
security violations as mentioned below and hence these
features have to be reverted.
- Devicekey support from Non secure software prone to DPA attack.
- Current authentication using single RSA key pair and not associated
with device which is security violation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The current authentication and device key support have
security violations as mentioned below and hence these
features have to be reverted.
- Devicekey support from Non secure software prone to DPA attack.
- Current authentication using single RSA key pair and not associated
with device which is security violation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The current authentication and device key support have
security violations as mentioned below and hence these
features have to be reverted.
- Devicekey support from Non secure software prone to DPA attack.
- Current authentication using single RSA key pair and not associated
with device which is security violation.
Signed-off-by: Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq: cse_nand: Increase malloc size for cse and target
This patch increases malloc pool size for cse nand target
as the provided 4k is not sufficient for and and hence
incrasing it to big 128K. 128K would nt be an issue for
cse_nand as it anyway runs from DDR and has sufficient
space for flashing. This solves issue of programming
fail while using it for flashing purpose from SDK.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch decreases initial malloc size as keeping
it more decreases the init stack size and hence
causing exception due to stack overflow. Also 0x800
should be fine for malloc before relocation.
The initial stack pointer is calculated as below.
CONFIG_SYS_INIT_RAM_SIZE - \
GENERATED_GBL_DATA_SIZE)
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
py: test_qspi: Update qspi tests to run at different frequencies
This patch updates the qspi tests to run at five different
randomized frequency values. This test gets the frequency
range to be tested from the board_env as qspi range will
vary for different flash devices.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch removes qspi_detected flag because if
a test has been failed then pytest framework will reset
board and continue with other test. In this case from
pytest point of view it already probed the device but
from device side it hasnt probed after reset. So removing
this flag allows device to probe the qspi for every test
and works even if one test failed in between.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
spi: zynq_qspi: Determine stacked mode using is-stacked
Determine stacked configuration using is-stacked property in dts
Incase if is-stacked is not defined in dts, default to single
mode. This change was done in order to be aligned with kernel.
Modified the required dts files as well.
spi: zynqmp_qspi: Determine stacked mode using is-stacked
Determine stacked configuration using is-stacked property in dts
Incase if is-stacked is not defined in dts, default to single
mode. This change was done in order to be aligned with kernel.
Modified the required dts files as well.
cmd: aes: Add support for using device key while decryption
This patch adds support for using device key while decryption
Devicekey is nothing but a key which was programmed in device
such as eFUSE or BBRAM. Having this feature support in this
command helps to inform hardware to use key from device instead
of user provided key.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
mtd: nand: Use the calculated ecc address for updating ecc register
This patch corrects the ecc address calculation before updating
to ecc register. The ecc address has to be calculated based on
page, oob and ecc sizes of the device.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: mp: Correct the R5 release sequence
This patch corrects the R5 release sequence by adding the
below steps.
1. Flush dcache to ensure that image loaded into memory.
2. Keep R5 reset just to ensure R5 in reset.
3. Disable caches before accesing TCM as with out this
A53 can do speculative and may result in ECC failures
if TCM's are not intialized. So, it is always better
to disable dcaches before accessing TCM and enable back.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Reported-by: John Linn <linnj@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Dont define CONFIG_MP through header file
Dont define CONFIG_MP through .h file, define it through defconfig as
it now moved to Kconfig. This ensures all dependent configs enabled.
This patch just removes MP support from existing platforms because
access to TCM/OCM was removed by patch
"arm64: zynqmp: Do not map unused OCM/TCM region"
(sha1: 4256d81f99f111731dd8196d680b00de849f9672)
and enabling CONFIG_MP re enables OCM/TCM which again result in
failures with isolation.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynqmp: tapdelays: Remove usage of SD0_OTAPDLYENA and SD1_OTAPDLYENA
This patch removes usage SD0_OTAPDLYENA and SD1_OTAPDLYENA bits.
This bits have impact on functionality of RTL due to one issue in
RTL where SD0_OTAPDLYENA (Bit 6) has been wrongly connected to both
SD0 and SD1 instances. This makes SD1_OTPDLYENA redundant. Also, these
signals are not used anywhere in silicon and hence there is
really no need to set these bits.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 26 Jul 2017 07:18:44 +0000 (09:18 +0200)]
arm64: zynqmp: Add new psu_init* files for zcu104 with proper DP setup
Changes are related DP clock setup.
psu_init* are generated with Vivado v2017.3 with these paramaters:
-board zcu104 -build hdf -ddr ddr4auto2133_component -clk video
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 20 Jun 2017 10:43:52 +0000 (12:43 +0200)]
arm64: zynqmp: Remove additional phy-names for second GT lane
This should be the part of:
"ARM64: zynqmp: zcu102: Use only one lane for DP"
(sha1: 0fef1fb0fd555a3fa2cb056b36b3245b15bf24b3)
where second GT line was removed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 20 Jul 2017 08:58:50 +0000 (10:58 +0200)]
arm64: zynqmp: Move dts zcu102 to zcu102-revA
Not using board revision is causing confusion about which board is
supported and tested. Mark dts files exactly with board revision which
was tested. When new board revision arives it can be symlink if SW view is
the same. Also add -revX suffix to compatible string because user space
tools are parsing this string and can change behavior depends of board
revision.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 20 Jul 2017 08:53:15 +0000 (10:53 +0200)]
arm64: zynqmp: Label zcu106 with board revision
Not using board revision is causing confusion about which board is
supported and tested. Mark dts files exactly with board revision which was
tested. When new board revision arives it can be symlink if SW view is
the same. Also add -revX suffix to compatible string because user space
tools are parsing this string and can change behavior depends of board
revision.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Add quirk for enabling workaround for BULK IN streams
This patch adds support for enabling workaround for BULK IN stream
rings by adding "xhci-stream-quirk" flag to dts node. Enabling this
flag activates the timer for every BULK IN stream ring at the time
of queuing TRB's into BULK IN stream ring.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Manish Narani [Mon, 27 Mar 2017 12:17:00 +0000 (17:47 +0530)]
arm64: zynqmp: Enabled CCI support for USB
This patch adds CCI support for USB when CCI is enabled in design.
This patch also adds 'reg' property for Xilinx USB 3.0 IP. The 'reg'
property is added in order to modify a register in that to enable
coherency in Hardware.
Also add address to unit name to avoid dtc warning
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: sdhci: set host quirk2 for no 1.8V support for 1.0 silicon
This patch sets host quirk2 bit field for No 1.8V supported in case of
1.0 silicon. The 1.0 silicon doesn't have support for UHS-I modes. This
property will ensure the SD runs on High Speed mode.
Signed-off-by: Manish Narani <mnarani@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
AXI master interface in CEVA AHCI controller requires two unique
Write/Read ID tags per port. This is because, ahci controller uses
different AXI ID[3:0] bits for identifying non-data transfers(like
reading descriptors, updating PRD tables, etc) and data transfers
(like sending/receiving FIS).To make SMMU work with SATA we need to
add correct SMMU stream id for SATA. SMMU stream id for SATA is
determined based on the AXI ID[1:0] as shown below
SATA SMMU ID = <TBU number>, 0011, 00, 00, AXI ID[1:0]
Note: SATA in ZynqMp uses TBU1 so TBU number = 0x1, so
SMMU ID = 001, 0011, 00, 00, AXI ID[1:0]
Since we have four different AXI ID[3:0] (2 for port0 & 2 for port1
as said above) we get four different SMMU stream id's combinations
for SATA. These AXI ID can be configured using PAXIC register.
In this patch we assumed the below AXI ID values
Read ID/ Write ID for Non-Data Port0 transfers = 0
Read ID/ Write ID for Data Port0 transfers = 1
Read ID/ Write ID for Non-Data Port1 transfers = 2
Read ID/ Write ID for Data Port1 transfers = 3
Based on the above values,SMMU stream ID's for SATA will be 0x4c0 &
0x4c1 for PORT0, 0x4c2 & 0x4c3 for PORT1. These values needed to be
added to iommus dts property. This patch does the same.
Signed-off-by: Anurag Kumar Vulisha <anuragku@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Jolly Shah [Wed, 14 Jun 2017 22:03:52 +0000 (15:03 -0700)]
arm64: zynqmp: Reduced min-residency time for idle state node
Changed min-residence to 10ms(was 100 ms) for cpu-sleep-0.
Tried lower values 5ms and 8ms and it worked fine with Debug Off.
But to accommodate PM Debug On case, 10 ms is required. With this
change, low power idle state is into effect more frequently.
Measured boot time with PM debugs On and Off. No change observed
compared to 100ms value.
Signed-off-by: Jolly Shah <jollys@xilinx.com> Acked-by: Will Wong <willw@xilinx.com> Tested-by: Koteswararao Nayudu <kotin@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 5 Jul 2017 12:50:44 +0000 (14:50 +0200)]
arm64: zynqmp: Remove leading 0s from mtd table for spi flashes
dtc reports issues with it.
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-zc1751-xm016-dc2.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff040000/spi0_flash0@0/spi0_flash0@00000000 unit name should
not have leading 0s
arch/arm64/boot/dts/xilinx/zynqmp-ep108.dtb: Warning
(unit_address_format): Node
/amba/spi@ff050000/spi1_flash0@0/spi1_flash0@00000000 unit name should
not have leading 0s
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 19 Jul 2017 08:09:01 +0000 (10:09 +0200)]
arm64: zynqmp: Add gpio line names to zcu100 revB and revC
Add gpio line names for fixed PS part. This can be reused by new
libgpiod library (https://github.com/brgl/libgpiod).
Examples are also available at tools/gpio.
EMIO gpio PL part needs to be generated to cover current HW design.
By purpose there is MIO/EMIO separation for easier EMIO description.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Remove no-1-8-v property to add UHS-I support for SD
This patch removes the property 'no-1-8-v' to add support
for Running SD in UHS-I mode. This will enable SD to operate
at 1.8V and maximum of 200MHz frequency if the SD card supports
the same
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arm64: zynqmp: Make chip_id routine to handle based on el.
Modify chip_id() routine such that to handle based on
the current el. Also make it available even if FPGA is
not enabled in system such it can be used always.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / thirdparty / u-boot.git / log
