Michal Simek [Wed, 21 Oct 2015 13:10:54 +0000 (15:10 +0200)]
ARM64: zynqmp: update the nand node with clock and chip select info
Added clock specification.
Added chip select information.
It is possible that the nand flash device(s) size can be > 4GB. So,
Increased
the address cycles property value to 2.
Since DC2 hw contains two flash devices and each flash size is 4GB,
modified the
partition table to accommodate the second flash and also added
partitions to
cover the whole flash size.
Signed-off-by: Punnaiah Choudary Kalluri <punnaia@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 21 Oct 2015 11:24:07 +0000 (13:24 +0200)]
ARM64: zynqmp: List all i2c muxes as separate buses for ZCU102
Simplify work with I2C muxes by definitely i2c bus topology.
Here is example of it:
ZynqMP> i2c bus
Bus 0: zynq_0
Bus 1: zynq_0->PCA9544A@0x75:0
Bus 2: zynq_0->PCA9544A@0x75:1
Bus 3: zynq_0->PCA9544A@0x75:2
Bus 4: zynq_1
Bus 5: zynq_1->PCA9548@0x74:0
Bus 6: zynq_1->PCA9548@0x74:1
Bus 7: zynq_1->PCA9548@0x74:2
Bus 8: zynq_1->PCA9548@0x74:3
Bus 9: zynq_1->PCA9548@0x74:4
Bus 10: zynq_1->PCA9548@0x75:0
Bus 11: zynq_1->PCA9548@0x75:1
Bus 12: zynq_1->PCA9548@0x75:2
Bus 13: zynq_1->PCA9548@0x75:3
Bus 14: zynq_1->PCA9548@0x75:4
Bus 15: zynq_1->PCA9548@0x75:5
Bus 16: zynq_1->PCA9548@0x75:6
Bus 17: zynq_1->PCA9548@0x75:7
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 7 Oct 2015 14:42:56 +0000 (16:42 +0200)]
net: zynq: Add support for different PHY interface types
MII is setup by default for all cases. The most of boards are using
RGMII but PHY drivers are not doing any specific setting that's why MII
setting was working file. With TI DP83867 is necessary to setup
paramaters based on interface type.
Use one setting per board for it which is something what will be removed
when driver is moved to DM.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Zynq has no priority queues.
ZynqMP requires this change to get network working.
This patch was not needed on ep108 for uknown reason even it should be
used.
Tested on Zynq and ZynqMP.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 5 Oct 2015 09:02:33 +0000 (11:02 +0200)]
zynqmp: Setup correct memory size for ep108
Move memory configuration to board configuration file to ensure memory
setup for every particular board.
Support 2GB ram for dc1 and dc2. Patch for extending it to 4GB will be
added when it is properly tested.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
This patch adds support for Microchip part
SST26WF016B. This device needs unlock
block protection command to be sent for
all the erase and write ops to be successful.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 8 Sep 2015 15:20:01 +0000 (17:20 +0200)]
net: zynq: Change MDC setup for arm64
MDC setting depends on pclk input clocks which varies across SoC. This
driver is used by xilinx zynq and zynqmp SOC.
Origin 224 divider is coming from RTL3.1 setting. The latest RTL doesn't
require this setting on EP108.
Input clock frequence on silicon is 125MHz where divider 64 put
frequency below 2.5MHz requires by spec (125/64=1.95).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 8 Sep 2015 15:07:01 +0000 (17:07 +0200)]
net: zynq: Fix MDC setting for zynq
Based on spec:
"MDC must not exceed 2.5 MHz (MDC is only active during MDIO read and
write operations)"
Zynq is running on 111MHz. Current setting is 32 which is 111/32=3.47
which is above of 2.5MHz.
Using 48 divider will give us correct setting according spec
(111/48=2.31).
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 8 Sep 2015 14:55:42 +0000 (16:55 +0200)]
net: zynq: Fix mdc clock division setting for 100Mbit/s
Using set and clear macro is incorrect because it is not overwritting
origin mdc clock division setup.
For example origin setup is 8(0b001) and new setup is 64(0b100) which
means 0b101 is setup which is 96 divider.
Using writel to rewrite all setting like for 1000Mbit/s case.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Tue, 8 Sep 2015 15:34:17 +0000 (17:34 +0200)]
net: zynq: Add missing const to wait_for_bit()
Remove compilation warning:
../drivers/net/zynq_gem.c:407:19: note: expected 'char *' but argument
is of type 'const char *'
../drivers/net/zynq_gem.c:476:8: warning: passing argument 1 of
'wait_for_bit' discards 'const' qualifier from pointer target type
[enabled by default]
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 3 Sep 2015 08:50:37 +0000 (10:50 +0200)]
ARM: zynqmp: Extend cache handling
- Add cache on/off functions to Kconfig. ARC has already done it and this
should be the same for all platforms.
- Disable caches for noatf dc1/dc2 configurations
- Enable CMD_CACHE
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 3 Sep 2015 06:16:32 +0000 (08:16 +0200)]
ARM: zynqmp: Remove incorrect command
The bug was introduced by:
"zynqmp: usb: Add usb dwc3 driver support for zynqmp"
(sha1: 2d5bc2183fa6484e8411ffa8edf1a33c63cb54b6)
with incorrect conflict resolution.
Remove this additional line.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Mon, 17 Aug 2015 07:58:54 +0000 (09:58 +0200)]
net: gem: Add dummy packet to fix packet duplication issue
Target is duplicating packets. IP prefetches another BD and process it
when the first one is sent. Adding one dummy BD to the chain fix the
problem with packet duplication.
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Thu, 13 Aug 2015 07:23:31 +0000 (09:23 +0200)]
net: Return -EINTR when ctrl+c is pressed
Current behavior is that if CTRL+C is pressed command returns 0 that was
successful which is not correct behavior.
The easiest test case is "tftpboot 80000 uImage && echo yes"
and press CTRL+C. Then the second command is called which is incorrect.
Error log:
zynq-uboot> tftpb 80000 uImage && echo yes
Gem.e000b000:7 is connected to Gem.e000b000. Reconnecting to
Gem.e000b000
Gem.e000b000 Waiting for PHY auto negotiation to complete....... done
Using Gem.e000b000 device
TFTP from server 192.168.0.102; our IP address is 192.168.0.101
Filename 'uImage'.
Load address: 0x80000
Loading: ################
Abort
yes
zynq-uboot>
This patch adds -EINTR return value when CTRL+C is pressed.
Signed-off-by: Michal Simek <michal.simek@xilinx.com> Reviewed-by: Tom Rini <trini@konsulko.com> Acked-by: Joe Hershberger <joe.hershberger@ni.com>
For more than 16MiB SPI flash chips, there are 3-Byte and 4-Byte address
mode, and only the 3-Byte address mode is supported in U-Boot so far.
So, reset the SPI flash to 3-Byte address mode in probe to ensure the SPI
flash work correctly, because it may has been set to 4-Byte address mode
after warm boot.
Signed-off-by: Hou Zhiqiang <B48286@freescale.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
zynq-common: Fix redefinition error with configs CMD_SF and CMD_SPI
Define CMD_SF and CMD_SPI configs incase of either
the ZYNQ_SPI or ZYNQ_QSPI or both. This is to avoid
the redefinition error if both ZYNQ_SPI and ZYNQ_QSPI
are enabled.
Signed-off-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Michal Simek [Wed, 12 Aug 2015 09:25:05 +0000 (11:25 +0200)]
ARM: dts: Rename memory@0 to memory
zynq-7000.dtsi include skeleton.dtsi which contains memory node with
base address and size zero. If you add memory@0 node to the platform DTS
in final DTB there are two memory nodes and U-Boot works with the first
one (with zeros) which end up in failing in dram_init because size is
zero.
Platform memory node should rewrite default memory node setup from
skeleton.dtsi that's why platfroms needs to also use memory as node name
instead of memory@0.
Reported-by: Siva Durga Prasad Paladugu <sivadur@xilinx.com> Signed-off-by: Michal Simek <michal.simek@xilinx.com>
projects / thirdparty / u-boot.git / log
