James Greenhalgh [Tue, 18 Nov 2014 09:54:22 +0000 (09:54 +0000)]
[Patch ARM Refactor Builtins 4/8] Refactor "VAR<n>" Macros
gcc/
* config/arm/arm-builtins.c (VAR1): Add a comma.
(VAR2): Rewrite in terms of VAR1.
(VAR3-10): Likewise.
(arm_builtins): Remove leading comma before ARM_BUILTIN_MAX.
* config/arm/arm_neon_builtins.def: Remove trailing commas.
Michael Meissner [Mon, 17 Nov 2014 22:32:26 +0000 (22:32 +0000)]
rs6000.c (RELOAD_REG_AND_M16): Add support for Altivec style vector loads that ignore the bottom 3 bits of the...
[gcc]
2014-11-17 Michael Meissner <meissner@linux.vnet.ibm.com>
Ulrich Weigand <Ulrich.Weigand@de.ibm.com>
* config/rs6000/rs6000.c (RELOAD_REG_AND_M16): Add support for
Altivec style vector loads that ignore the bottom 3 bits of the
address.
(rs6000_debug_addr_mask): New function to print the addr_mask
values if debugging.
(rs6000_debug_print_mode): Call rs6000_debug_addr_mask to print
out addr_mask.
(rs6000_setup_reg_addr_masks): Add support for Altivec style
vector loads that ignore the bottom 3 bits of the address. Allow
pre-increment and pre-decrement on floating point, even if the
-mupper-regs-{sf,df} options were used.
(rs6000_init_hard_regno_mode_ok): Rework DFmode support if
-mupper-regs-df. Add support for -mupper-regs-sf. Rearrange code
placement for direct move support.
(rs6000_option_override_internal): Add checks for -mupper-regs-df
requiring -mvsx, and -mupper-regs-sf requiring -mpower8-vector.
If -mupper-regs, set both -mupper-regs-sf and -mupper-regs-df,
depending on the underlying cpu.
(rs6000_secondary_reload_fail): Add ATTRIBUTE_NORETURN.
(rs6000_secondary_reload_toc_costs): Helper function to identify
costs of a TOC load for secondary reload support.
(rs6000_secondary_reload_memory): Helper function for secondary
reload, to determine if a particular memory operation is directly
handled by the hardware, or if it needs support from secondary
reload to create a valid address.
(rs6000_secondary_reload): Rework code, to be clearer. If the
appropriate -mupper-regs-{sf,df} is used, use FPR registers to
reload scalar values, since the FPR registers have D-form
addressing. Move most of the code handling memory to the function
rs6000_secondary_reload_memory, and use the reg_addr structure to
determine what type of address modes are supported. Print more
debug information if -mdebug=addr.
(rs6000_secondary_reload_inner): Rework entire function to be more
general. Use the reg_addr bits to determine what type of
addressing is supported.
(rs6000_preferred_reload_class): Rework. Move constant handling
into a single place. Prefer using FLOAT_REGS for scalar floating
point.
(rs6000_secondary_reload_class): Use a FPR register to move a
value from an Altivec register to a GPR, and vice versa. Move VSX
handling above traditional floating point.
* config/rs6000/rs6000.md (mov<mode>_hardfloat, FMOVE32 case):
Delete some spaces in the constraints.
(DF->DF move peephole2): Disable if -mupper-regs-{sf,df} to
allow using FPR registers to load/store an Altivec register for
scalar floating point types.
(SF->SF move peephole2): Likewise.
(DFmode splitter): Add a define_split to move floating point
constants to the constant pool before register allocation.
Normally constants are put into the pool immediately, but
-ffast-math delays putting them into the constant pool for the
reciprocal approximation support.
(SFmode splitter): Likewise.
* config/rs6000/rs6000.opt (-mupper-regs-df): Make option public.
(-mupper-regs-sf): Likewise.
* config/rs6000/rs6000-c.c (rs6000_target_modify_macros): Define
__UPPER_REGS_DF__ if -mupper-regs-df. Define __UPPER_REGS_SF__ if
-mupper-regs-sf.
(-mupper-regs): New combination option that sets -mupper-regs-sf
and -mupper-regs-df by default if the cpu supports the instructions.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mupper-regs, -mupper-regs-sf, and -mupper-regs-df.
* config/rs6000/predicates.md (memory_fp_constant): New predicate
to return true if the operand is a floating point constant that
must be put into the constant pool, before register allocation
occurs.
* config/rs6000/rs6000-cpus.def (ISA_2_6_MASKS_SERVER): Enable
-mupper-regs-df by default.
(ISA_2_7_MASKS_SERVER): Enable -mupper-regs-sf by default.
(POWERPC_MASKS): Add -mupper-regs-{sf,df} as options set by the
various -mcpu=... options.
(power7 cpu): Enable -mupper-regs-df by default.
* doc/invoke.texi (RS/6000 and PowerPC Options): Document
-mupper-regs.
[gcc/testsuite]
2014-11-17 Michael Meissner <meissner@linux.vnet.ibm.com>
* gcc.target/powerpc/p8vector-ldst.c: Rewrite to use 40 live
floating point variables instead of using asm to test allocating
values to the Altivec registers.
* gcc.target/powerpc/upper-regs-sf.c: New -mupper-regs-sf and
-mupper-regs-df tests.
* gcc.target/powerpc/upper-regs-df.c: Likewise.
* config/rs6000/predicates.md (memory_fp_constant): New predicate
Jason Merrill [Mon, 17 Nov 2014 20:17:56 +0000 (15:17 -0500)]
re PR c++/50473 ([C++0x] ICE in type_has_nontrivial_copy_init, at cp/tree.c:2574)
PR c++/50473
* decl.c (cp_finish_decl): Don't try to process a non-dependent
constant initializer for a reference.
* pt.c (value_dependent_expression_p): A reference is always
dependent.
* call.c (extend_ref_init_temps_1): Also clear TREE_SIDE_EFFECTS
on any NOP_EXPRs.
Jason Merrill [Mon, 17 Nov 2014 18:16:14 +0000 (13:16 -0500)]
C++14 constexpr support (minus loops and multiple returns)
C++14 constexpr support (minus loops and multiple returns)
gcc/
* tree-inline.c (copy_fn): New.
* tree-inline.h: Declare it.
gcc/cp/
* constexpr.c (use_new_call): New macro.
(build_data_member_initialization): Ignore non-mem-inits.
(check_constexpr_bind_expr_vars): Remove C++14 checks.
(constexpr_fn_retval): Likewise.
(check_constexpr_ctor_body): Do nothing in C++14.
(massage_constexpr_body): In C++14 only collect mem-inits.
(get_function_named_in_call): Handle null CALL_EXPR_FN.
(cxx_bind_parameters_in_call): Build bindings in same order as
parameters. Don't treat iniviref parms specially in new call mode.
(cxx_eval_call_expression): If use_new_call, do constexpr expansion
based on DECL_SAVED_TREE rather than the massaged constexpr body.
Set up ctx->object from AGGR_INIT_EXPR_SLOT if we don't have one.
(is_sub_constant_expr): Don't mess with ctx.ctor here.
(cxx_eval_component_reference): A null element means we're mid-
initialization.
(cxx_eval_store_expression, cxx_eval_increment_expression): New.
(cxx_eval_constant_expression): Handle RESULT_DECL, DECL_EXPR,
MODIFY_EXPR, STATEMENT_LIST, BIND_EXPR, USING_STMT,
PREINCREMENT_EXPR, POSTINCREMENT_EXPR, PREDECREMENT_EXPR,
POSTDECREMENT_EXPR. Don't look into DECL_INITIAL of variables in
constexpr functions. In new-call mode find parms in the values table.
(potential_constant_expression_1): Handle null CALL_EXPR_FN.
Handle STATEMENT_LIST, MODIFY_EXPR, MODOP_EXPR, IF_STMT,
PREINCREMENT_EXPR, POSTINCREMENT_EXPR, PREDECREMENT_EXPR,
POSTDECREMENT_EXPR, BIND_EXPR, WITH_CLEANUP_EXPR,
CLEANUP_POINT_EXPR, MUST_NOT_THROW_EXPR, TRY_CATCH_EXPR,
EH_SPEC_BLOCK, EXPR_STMT, DECL_EXPR, CASE_LABEL_EXPR, BREAK_STMT,
CONTINUE_STMT, USING_STMT, IF_STMT, DO_STMT, FOR_STMT, WHILE_STMT,
SWITCH_STMT, ASM_EXPR.
(cxx_eval_vec_init_1): Call build_aggr_init_expr.
(cxx_eval_indirect_ref): Don't return a CONSTRUCTOR when the
caller wants an lvalue.
(cxx_eval_outermost_constant_expr): Pull object out of AGGR_INIT_EXPR.
(maybe_constant_init): Look through INIT_EXPR.
(ensure_literal_type_for_constexpr_object): Set
cp_function_chain->invalid_constexpr.
* cp-tree.h (struct language_function): Add invalid_constexpr bitfield.
* decl.c (start_decl): Set cp_function_chain->invalid_constexpr.
(check_for_uninitialized_const_var): Likewise.
(maybe_save_function_definition): Check it.
* parser.c (cp_parser_jump_statement): Set
cp_function_chain->invalid_constexpr.
(cp_parser_asm_definition): Likewise.
Jason Merrill [Mon, 17 Nov 2014 17:00:38 +0000 (12:00 -0500)]
re PR c++/52282 ([C++0x] rejects-valid issues with decltype/constexpr)
PR c++/52282
* decl.c (build_ptrmemfunc_type): Don't build a different
RECORD_TYPE for a qualified PMF.
* cp-tree.h (TYPE_PTRMEMFUNC_FN_TYPE): Merge cv-quals.
(TYPE_PTRMEMFUNC_FN_TYPE_RAW): New.
* decl2.c (cplus_decl_attributes): Use TYPE_PTRMEMFUNC_FN_TYPE_RAW.
* tree.c (cp_walk_subtrees): Likewise.
(cp_build_qualified_type_real): Remove special PMF handling.
* config/aarch64/aarch64-modes.def: Define ccmp CC mode.
* config/aarch64/aarch64.c (aarch64_get_condition_code_1): New function
extacted from aarch64_get_condition_code.
(aarch64_get_condition_code): Call aarch64_get_condition_code_1.
config/aarch64/predicates.md (ccmp_cc_register): New predicate.
* cfgexpand.c (expand_gimple_cond): Check ccmp.
* expmed.c (emit_cstore): Make it global.
* expmed.h: #include "insn-codes.h"
(emit_cstore): New prototype.
* expr.c (expand_operands): Make it global.
* expr.h (expand_operands): New prototype.
* optabs.c (get_rtx_code): Make it global.
* optabs.h (get_rtx_code): New prototype.
Jan Hubicka [Sun, 16 Nov 2014 21:01:45 +0000 (22:01 +0100)]
* ipa-polymorphic-call.c
(ipa_polymorphic_call_context::speculation_consistent_p): Constify.
(ipa_polymorphic_call_context::meet_speculation_with): New function.
(ipa_polymorphic_call_context::combine_with): Handle types in construction
better.
(ipa_polymorphic_call_context::equal_to): Do not bother about useless
speculation.
(ipa_polymorphic_call_context::meet_with): New function.
* cgraph.h (class ipa_polymorphic_call_context): Add
meet_width, meet_speculation_with; constify speculation_consistent_p.
* ipa-cp.c (ipa_context_from_jfunc): Handle speculation; combine with incomming
context.
(propagate_context_accross_jump_function): Likewise; be more cureful.
about set_contains_variable.
(ipa_get_indirect_edge_target_1): Fix handling of dynamic type changes.
(find_more_scalar_values_for_callers_subset): Fix.
(find_more_contexts_for_caller_subset): Perform meet operation.
Jan Hubicka [Sun, 16 Nov 2014 19:36:37 +0000 (20:36 +0100)]
passes.c (execute_one_pass): Do not apply all transforms prior every simple IPA pass.
* passes.c (execute_one_pass): Do not apply all transforms prior
every simple IPA pass.
* cgraphunit.c: Do not include fibheap.h
(expand_thunk): Use get_untransformed_body.
(cgraph_node::expand): Likewise.
* tree-ssa-structalias.c (ipa_pta_execute): Skip inline clones.
* cgraph.c (release_function_body): Do not push cfun when CFG is not there.
(cgraph_node::get_untransformed_body): Break out from ...
(cgraph_node::get_body): ... here; add code to apply all transforms.
* cgraph.h (cgraph_node): Add get_untransformed_body.
* ipa-icf.c (sem_function::init): Use get_untransformed_body.
* cgraphclones.c (duplicate_thunk_for_node): Likewise.
* tree-inline.c (expand_call_inline): LIkewise.
* i386.c (ix86_reset_to_default_globals): Break out from ...
(ix86_set_current_function): ... here;
(ix86_reset_previous_fndecl): Use it.
(ix86_simd_clone_adjust): Use ix86_reset_previous_fndecl.
Andrew Pinski [Sun, 16 Nov 2014 08:01:09 +0000 (08:01 +0000)]
memset-4.c: New test.
2014-11-16 Andrew Pinski <apinski@cavium.com>
* gcc.c-torture/execute/memset-4.c: New test.
* gcc.c-torture/execute/20110418-1.c: New test.
* gcc.c-torture/execute/20141022-1.c: New test.
* gcc.c-torture/execute/strcpy-2.c: New test.
* gcc.c-torture/execute/20140212-2.c: New test.
* gcc.c-torture/compile/20120913-1.c: New test.
* gcc.c-torture/compile/20121010-1.c: New test.
* gcc.c-torture/compile/20120917-1.c: New test.
* gcc.c-torture/compile/20140110-1.c: New test.
* gcc.c-torture/compile/20121220-1.c: New test.
* gcc.c-torture/compile/20120822-1.c: New test.
* gcc.c-torture/compile/20121027-1.c: New test.
* gcc.c-torture/compile/20120830-2.c: New test.
Janne Blomqvist [Sun, 16 Nov 2014 01:56:54 +0000 (03:56 +0200)]
PR 60324 VLA related fixes to random number generator.
2014-11-16 Janne Blomqvist <jb@gcc.gnu.org>
PR libfortran/60324
* intrinsics/random.c (kiss_size): Rename to KISS_SIZE, make it a
macro instead of a variable.
(random_seed_i4): Make seed correct size, remove assert, KISS_SIZE
related changes.
(random_seed_i8): KISS_SIZE related changes.
Eric Botcazou [Sat, 15 Nov 2014 12:34:20 +0000 (12:34 +0000)]
tree-cfg.c (replace_loop_annotate_in_block): New function extracted from...
* tree-cfg.c (replace_loop_annotate_in_block): New function extracted
from...
(replace_loop_annotate): ...here. Call it on the header and on the
latch block, if any. Restore proper behavior of final cleanup.
Andrew Pinski [Fri, 14 Nov 2014 21:21:25 +0000 (21:21 +0000)]
[AARCH64] Add scheduler for ThunderX
This adds the schedule model for ThunderX. There are a few TODOs in that
not all of the SIMD is model currently. Also the idea of a simple
shift/extend is not modeled and all cases where there is a shift/extend
is considered as non simple and take up two cycles rather than correct
value of one cycle. Also the 32bit divide and the 64bit divide
have different cycle counts but there is no way to model that currently.
Also multiply high takes one cycle more than the normal multiply but
there is no way to model that currently either.
Build and tested for aarch64-elf with no regressions.
ChangeLog:
* config/aarch64/aarch64-cores.def (thunderx): Change the scheduler
over to thunderx.
* config/aarch64/aarch64.md: Include thunderx.md.
(generic_sched): Set to no for thunderx.
* config/aarch64/thunderx.md: New file.
Michael Meissner [Fri, 14 Nov 2014 20:45:21 +0000 (20:45 +0000)]
predicates.md (easy_fp_constant): Delete redunant tests for 0.0.
[gcc]
2014-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
* config/rs6000/predicates.md (easy_fp_constant): Delete redunant
tests for 0.0.
* config/rs6000/vector.md (VEC_R): Move secondary reload support
insns to rs6000.md from vector.md.
(reload_<VEC_R:mode>_<P:mptrsize>_store): Likewise.
(reload_<VEC_R:mode>_<P:mptrsize>_load): Likewise.
(vec_reload_and_plus_<mptrsize>): Likewise.
* config/rs6000/rs6000.md (Fa): New mode attribute to give
constraint for the Altivec registers for a type.
(RELOAD): New mode iterator for all of the types that have
secondary reload address support to load up a base register.
(extendsfdf2_fpr): Use correct constraint.
(copysign<mode>3_fcpsgn): For SFmode, use correct xscpsgndp
instruction.
(floatsi<mode>2_lfiwax): Add support for -mupper-regs-{sf,df}.
Generate the non-VSX instruction if all registers were FPRs. Do
not use the patterns in vsx.md for scalar operations.
(floatsi<mode>2_lfiwax_mem): Likewise.
(floatunssi<mode>2_lfiwzx): Likewise.
(floatunssi<mode>2_lfiwzx_mem): Likewise.
(fix_trunc<mode>di2_fctidz): Likewise.
(fixuns_trunc<mode>di2_fctiduz): Likewise.
(fctiwz_<mode>): Likewise.
(fctiwuz_<mode>): Likewise.
(friz): Likewise.
(floatdidf2_fpr): Likewise.
(floatdidf2_mem): Likewise.
(floatunsdidf2): Likewise.
(floatunsdidf2_fcfidu): Likewise.
(floatunsdidf2_mem): Likewise.
(floatdisf2_fcfids): Likewise.
(floatdisf2_mem): Likewise.
(floatdisf2_internal1): Add explicit test for not FCFIDS to make
it more obvious that the code is for pre-ISA 2.06 machines.
(floatdisf2_internal2): Likewise.
(floatunsdisf2_fcfidus): Add support for -mupper-regs-{sf,df}.
Generate the non-VSX instruction if all registers were FPRs. Do
not use the patterns in vsx.md for scalar operations.
(floatunsdisf2_mem): Likewise.
(reload_<RELOAD:mode>_<P:mptrsize>_store): Move the reload
handlers here from vector.md, and expand the types we generate
reload handlers for.
(reload_<RELOAD:mode>_<P:mptrsize>_load): Likewise.
(vec_reload_and_plus_<mptrsize>): Likewise.
* config/rs6000/vsx.md (vsx_float<VSi><mode>2): Only provide the
vector forms of the instructions. Move VSX scalar forms to
rs6000.md, and add support for -mupper-regs-sf.
(vsx_floatuns<VSi><mode>2): Likewise.
(vsx_fix_trunc<mode><VSi>2): Likewise.
(vsx_fixuns_trunc<mode><VSi>2): Likewise.
(vsx_float_fix_<mode>2): Delete DF version, rename to
vsx_float_fix_v2df2.
(vsx_float_fix_v2df2): Likewise.
[gcc/testsuite]
2014-11-14 Michael Meissner <meissner@linux.vnet.ibm.com>
Martin Jambor [Fri, 14 Nov 2014 20:07:39 +0000 (21:07 +0100)]
ipa-prop.h (jump_func_type): Removed value IPA_JF_KNOWN_TYPE.
2014-11-14 Martin Jambor <mjambor@suse.cz>
* ipa-prop.h (jump_func_type): Removed value IPA_JF_KNOWN_TYPE.
(ipa_pass_through_data): Removed field type_preserved.
(ipa_ancestor_jf_data): removed fields type and type_preserved.
(ipa_jump_func): Removed field known_type.
(ipa_get_jf_known_type_offset): Removed.
(ipa_get_jf_known_type_base_type): Likewise.
(ipa_get_jf_known_type_component_type): Likewise.
(ipa_get_jf_ancestor_type): Likewise.
* ipa-cp.c (print_ipcp_constant_value): Removed BINFO handling.
(ipa_get_jf_pass_through_result): Likewise.
(ipa_get_jf_ancestor_result): Always build ptr_node_type accesses.
(values_equal_for_ipcp_p): Removed BINFO handling.
(ipa_get_indirect_edge_target_1): Updated comment.
* ipa-prop.c (ipa_print_node_jump_functions_for_edge): Removed handling
of IPA_JF_KNOWN_TYPE jump functions. Do not print removed fields.
(ipa_set_jf_known_type): Removed.
(ipa_set_jf_simple_pass_through): Do not set removed fields. Update
all callers.
(ipa_set_jf_arith_pass_through): Likewise.
(ipa_set_ancestor_jf): Likewise.
(ipa_binfo_from_known_type_jfunc): Removed.
(prop_type_change_info): Removed fields known_current_type and
multiple_types_encountered.
(extr_type_from_vtbl_ptr_store): Removed.
(check_stmt_for_type_change): Do not attempt to identify changed type.
(detect_type_change_from_memory_writes): Do not set the removed fields,
always set jfunc to unknown.
(compute_complex_assign_jump_func): Do not detect dynamic type change.
(compute_complex_ancestor_jump_func): Likewise.
(compute_known_type_jump_func): Removed.
(ipa_compute_jump_functions_for_edge): Do not detect dynamic type
change. Do not comute known type jump functions.
(combine_known_type_and_ancestor_jfs): Removed.
(update_jump_functions_after_inlining): Removed handling of
IPA_JF_KNOWN_TYPE jump functions. Do not set removed fields.
(ipa_write_jump_function): Do not stream removed fields or known type
jump functions.
(ipa_read_jump_function): Likewise.
* lra-int.h (lra_create_live_ranges): Add parameter.
* lra-lives.c (temp_bitmap): Move higher.
(initiate_live_solver): Move temp_bitmap initialization into
lra_live_ranges_init.
(finish_live_solver): Move temp_bitmap clearing into
live_ranges_finish.
(process_bb_lives): Add parameter. Use it to control live info
update and dead insn elimination. Pass it to mark_regno_live and
mark_regno_dead.
(lra_create_live_ranges): Add parameter. Pass it to
process_bb_lives.
(lra_live_ranges_init, lra_live_ranges_finish): See changes in
initiate_live_solver and finish_live_solver.
* lra-remat.c (do_remat): Process insn non-operand hard regs too.
Use temp_bitmap to update avail_cands.
* lra.c (lra): Pass new parameter to lra_create_live_ranges. Move
check with lra_need_for_spill_p after live range pass. Switch on
rematerialization pass.
projects / thirdparty / gcc.git / log
