Alfie Richards [Tue, 14 Oct 2025 15:08:18 +0000 (15:08 +0000)]
docs: fmv: Update Function multi-versioning documentation [PR c/122202]
This updates the FMV documentation to the current state of things, including
the addition of "target_version" based FMV.
Left as much of the x86 target based FMV documentation unchanged as
the behaviour change there should be unchanged. Though highlights some of
the differences between it and target_version FMV to try avoid confusion there.
PR c/122202
gcc/ChangeLog:
* doc/extend.texi (target function attribute): Update to describe FMV
behaviour.
(target_version function attribute): New section.
(target_clones attribute): Update to descrbe new behaviour with
target_version.
(Function Multiversioning): Update to discuss both target_version and
target based FMV.
Kito Cheng [Wed, 22 Oct 2025 09:06:03 +0000 (17:06 +0800)]
RISC-V: Fix the ABI of empty unions and zero length array in struct
The RISC-V ABI currently defines that empty unions and zero length array
in struct should be ignored, but the implementation in GCC is not
correct.
e.g. for the following code:
```
struct S2eu_2f {
union{} e1;
float f;
float g;
};
```
The RISC-V ABI defines that the layout of S2eu_2f should be equivalent
to:
```
struct S2eu_2f {
float f;
float g;
};
```
However, the current GCC implementation passes S2eu_2f in a0 (lp64d)
rather than fa0 and fa1 (lp64d).
Also for the following code:
```
struct S0ae_2f {
struct{} e1[0];
float f;
float g;
};
```
The RISC-V ABI defines that the layout of S0ae_2f should be equivalent
to:
```
struct S0ae_2f {
float f;
float g;
};
```
And again, the current GCC implementation passes S0ae_2f in a0 (lp64d)
rather than fa0 and fa1 (lp64d).
This patch fixes the issue by updating the relevant functions to correctly
handle empty unions, also we have implemented the ABI change warning to
notify user that the ABI of empty unions and zero length array in struct
has been changed/fixed.
Generally ABI should not be changed, but the psABI is defined there for
long time and clang/LLVM has already implemented it correctly, so we
decide to fix it in GCC as well to maintain compatibility, and another
reason to fix that in GCC is zero length array and empty union in struct
should be rarely used in practice, so the impact should be limited.
* config/riscv/riscv.cc (riscv_flatten_aggregate_field): Skip
empty unions and zero-length arrays when flattening aggregate
fields for ABI classification.
(riscv_pass_aggregate_in_fpr_pair_p): Refactor to use separate
field parsing and emit ABI change warning for affected types.
(riscv_pass_aggregate_in_fpr_and_gpr_p): Likewise.
gcc/testsuite/ChangeLog:
* g++.dg/abi/param2.C: Add -Wno-psabi option for RISC-V.
* g++.target/riscv/abi/empty-struct+union-1.cc: New test.
* g++.target/riscv/abi/empty-struct+union-2.cc: New test.
* g++.target/riscv/abi/empty-struct+union-3.cc: New test.
* g++.target/riscv/abi/empty-struct+union-4.cc: New test.
* g++.target/riscv/abi/empty-struct-1.cc: New test.
* g++.target/riscv/abi/empty-struct-2.cc: New test.
* g++.target/riscv/abi/empty-struct-3.cc: New test.
* g++.target/riscv/abi/empty-struct-4.cc: New test.
* g++.target/riscv/abi/empty-struct-5.cc: New test.
* g++.target/riscv/abi/empty-struct-6.cc: New test.
* g++.target/riscv/abi/empty-struct-7.cc: New test.
* g++.target/riscv/abi/empty-struct-8.cc: New test.
* g++.target/riscv/abi/empty-struct-9.cc: New test.
* g++.target/riscv/abi/empty-struct-10.cc: New test.
* g++.target/riscv/abi/empty-struct-11.cc: New test.
* g++.target/riscv/abi/empty-struct-12.cc: New test.
* g++.target/riscv/abi/empty-union-1.cc: New test.
* g++.target/riscv/abi/empty-union-2.cc: New test.
* g++.target/riscv/abi/empty-union-3.cc: New test.
* g++.target/riscv/abi/empty-union-4.cc: New test.
* g++.target/riscv/riscv.exp: Add abi subdirectory.
* gcc.dg/compat/pr83487-1_x.c: Add -Wno-psabi option for RISC-V.
* gcc.dg/compat/pr83487-1_y.c: Likewise.
* gcc.dg/compat/pr83487-2_x.c: Likewise.
* gcc.dg/compat/pr83487-2_y.c: Likewise.
* gcc.dg/torture/pr28814.c: Likewise.
* gcc.target/riscv/abi/empty-struct+union-1.c: New test.
* gcc.target/riscv/abi/empty-struct+union-2.c: New test.
* gcc.target/riscv/abi/empty-struct+union-3.c: New test.
* gcc.target/riscv/abi/empty-struct+union-4.c: New test.
* gcc.target/riscv/abi/empty-struct-1.c: New test.
* gcc.target/riscv/abi/empty-struct-2.c: New test.
* gcc.target/riscv/abi/empty-struct-3.c: New test.
* gcc.target/riscv/abi/empty-struct-4.c: New test.
* gcc.target/riscv/abi/empty-struct-5.c: New test.
* gcc.target/riscv/abi/empty-struct-6.c: New test.
* gcc.target/riscv/abi/empty-struct-7.c: New test.
* gcc.target/riscv/abi/empty-struct-8.c: New test.
* gcc.target/riscv/abi/empty-struct-9.c: New test.
* gcc.target/riscv/abi/empty-struct-10.c: New test.
* gcc.target/riscv/abi/empty-struct-11.c: New test.
* gcc.target/riscv/abi/empty-struct-12.c: New test.
* gcc.target/riscv/abi/empty-union-1.c: New test.
* gcc.target/riscv/abi/empty-union-2.c: New test.
* gcc.target/riscv/abi/empty-union-3.c: New test.
* gcc.target/riscv/abi/empty-union-4.c: New test.
* gcc.target/riscv/riscv.exp: Add abi subdirectory.
Alfie Richards [Mon, 20 Oct 2025 12:01:13 +0000 (12:01 +0000)]
aarch64: Add missing fmv features.
Add all the missing FMV features from the ACLE.
gcc/ChangeLog:
* config/aarch64/aarch64-option-extensions.def (dit): New fmv feature.
(dpb): New fmv feature.
(dpb2): New fmv feature.
(memtag): Change to also define an FMV feature.
(ssbs): Change to also define an FMV feature.
(bti): New fmv feature.
* config/aarch64/aarch64.cc (FEAT_SSBS): Add macro.
(FEAT_MEMTAG): Ditto.
gcc/testsuite/ChangeLog:
* gcc.target/aarch64/fmv_priority.in: Update for new features.
* gcc.target/aarch64/fmv_priority1.c: Ditto.
* gcc.target/aarch64/fmv_priority2.c: Ditto.
xtensa: Revise implementation of hardware FP rounding instructions
Since each element in an MD iterator can have its own condition that is
true by default, it is simpler to specify the precondition for the ROUND.S
machine instruction such way.
There are no functional changes with this patch.
gcc/ChangeLog:
* config/xtensa/xtensa.md (int_iterator ANY_ROUND):
Specify "flag_unsafe_math_optimizations" in the condition of the
UNSPEC_ROUND element.
(int_attr c_round): Remove.
(l<m_round>sfsi2, *l<m_round>sfsi2_2x, *l<m_round>sfsi2_scaled):
Remove " && <c_round>" from the conditions.
Make scalar int mode and scalar fp mode tieable, so movgr2fr and
movfr2gr can be used instead of memory access.
For example, in pattern '*movsi_internal', when matching gr->fr,
due to the constraint '*' in alt4, it will match alt5, resulting
in memory access instead of movgr2fr.
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_modes_tieable_p):
Make MODE_FLOAT and MODE_INT tieable.
* config/loongarch/loongarch.md: Adjust constraints.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/mode-tieable-opt.c: New test.
Guo Jie [Sun, 2 Nov 2025 03:31:32 +0000 (11:31 +0800)]
LoongArch: Eliminate unnecessary dependencies introduced by xvpermi.q
1. When the selector is 0x0, 0x1, 0x10, or 0x11, the result of
xvpermi.q does not depend on the output operand, thus eliminating
the dependency chain of the output operand as input, which can
reduce the number of instructions.
2. When the selector is 0x22, 0x23, 0x32, or 0x33, the result of
xvpermi.q does not depend on the second input operand, thus
eliminating the dependency chain of the second input operand,
which can also reduce the number of instructions.
gcc/ChangeLog:
* config/loongarch/lasx.md (lasx_xvpermi_q_<LASX:mode>):
Add new splitter for optimization.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vec_pack_unpack_256.c: Adjust to changed
lasx_xvpermi_q_<LASX:mode> template.
* gcc.target/loongarch/vector/lasx/lasx-builtin.c: Ditto.
* gcc.target/loongarch/lasx-xvpermi_q-opt.c: New test.
Guo Jie [Sun, 2 Nov 2025 03:30:57 +0000 (11:30 +0800)]
LoongArch: Optimize AND large immediate operation
For large immediate values in variable AND operations:
if their bit representation has two consecutive 0 sequences,
one starting from the MSB can use the bstrpick.d instruction,
and the bstrins.d instruction for the other.
For example, in the case 'var & 0x3fffffffefffffff':
Before:
lu12i.w $r12,-65537
ori $r12,$r12,4095
lu52i.d $r12,$r12,0x3ff
and $r4,$r4,$r12
* config/loongarch/loongarch-protos.h
(loongarch_use_bstrins_bstrpick_for_and): New proto.
* config/loongarch/loongarch.cc
(loongarch_use_bstrins_bstrpick_for_and): Decide whether
to optimize.
(loongarch_rtx_costs): Adjust the cost of AND operation.
* config/loongarch/loongarch.md
(bstrins_bstrpick_for_and_imm<mode>): New insn_and_split.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/and-large-immediate-opt.c: New test.
Tamar Christina [Mon, 3 Nov 2025 08:07:13 +0000 (08:07 +0000)]
vect: Fix null dereference in boolean reductions [PR122475]
neutral_op can be null, so guard against that.
gcc/ChangeLog:
PR tree-optimization/122475
* tree-vect-loop.cc (vectorizable_reduction): Check for neutral_op.
gcc/testsuite/ChangeLog:
PR tree-optimization/122475
* gcc.dg/vect/pr122475.c: New test.
* gcc.target/aarch64/sve/vect-reduc-bool-19.c: New test.
* gcc.target/aarch64/sve/vect-reduc-bool-20.c: New test.
H.J. Lu [Mon, 20 Oct 2025 08:14:34 +0000 (16:14 +0800)]
x86-64: Inline memmove with overlapping unaligned loads and stores
Inline memmove in 64-bit since there are much less registers available
in 32-bit:
1. Load all sources into registers and store them together to avoid
possible address overlap between source and destination.
2. For known size, first try to fully unroll with 8 registers.
3. For size <= 2 * MOVE_MAX, load all sources into 2 registers first
and then store them together.
4. For size > 2 * MOVE_MAX and size <= 4 * MOVE_MAX, load all sources
into 4 registers first and then store them together.
5. For size > 4 * MOVE_MAX and size <= 8 * MOVE_MAX, load all sources
into 8 registers first and then store them together.
6. For size > 8 * MOVE_MAX,
a. If address of destination > address of source, copy backward
with a 4 * MOVE_MAX loop with unaligned loads and stores. Load
the first 4 * MOVE_MAX into 4 registers before the loop and
store them after the loop to support overlapping addresses.
b. Otherwise, copy forward with a 4 * MOVE_MAX loop with unaligned
loads and stores. Load the last 4 * MOVE_MAX into 4 registers
before the loop and store them after the loop to support
overlapping addresses.
Verified and benchmarked memmove implementations inlined with GPR, SSE2,
AVX2 and AVX512 using glibc memmove tests. It is available at
This is Shreya's work, my contribution was primarily covering the testing.
Bootstrapped and regression tested on x86 and riscv64. It's also been tested
on all the embedded targets in my tester without regression.
While this improves code generation to optimal on riscv-64, I'm electing to
keep the BZ open because we probably should have the same kind of
simplification in match.pd. Shreya is just starting to write some match.pd
patterns and I expect we'll return to write a match.pd pattern for this issue
relatively soon.
Obviously waiting for pre-commit CI to chime in before moving forward.
Jeff
--
In PR52345, we have this testcase:
int f(int a, int b)
{
int c = a != 0;
int d = (c!=0|b!=0);
return d;
}
Basically, "d" will either be 0 or 1. Depending on "a", "c" will also
either be 0 or 1. So if "a" is 0 and "b" is 0, then "d" will also be 0. Otherwise, it will be 1.
When the testcase is compiled, we get this generated assembly code:
snez a0,a0
or a0,a1,a0
snez a0,a0
RISC-V has a missed optimization here, as this can simply be done by first
computing a|b and checking if the result is equal to 0. If "a" is 0 and "b" is
0, we will get 0. Otherwise, we will get 1. Doing this removes the unnecessary
first snez instruction.
When we looked at the combine pass, it was trying:
Failed to match this instruction:
(set (reg/i:DI 10 a0)
(ne:DI (ior:DI (ne:DI (reg:DI 151 [ a ])
(const_int 0 [0]))
(reg:DI 152 [ b ]))
(const_int 0 [0])))
In simplify_relational_operation_1 of simplify-rtx.cc, we added a condition.
For cases where the outer code is a "not equal to" (NE) and the operands match
the pattern above, we simply emit an NE of an IOR of the two registers, giving
us:
or a0,a0,a1
snez a0,a0
We then generalized this to include the case where the outer code is an "equal
to" (EQ). With the logic working in the same way, we simply adjust the
recognition code to check that the outer code is either an NE or EQ and
generalize the NE we emit to match the outer code.
chenxiaolong [Wed, 29 Oct 2025 10:49:34 +0000 (18:49 +0800)]
LoongArch: Add builtin interfaces for 128 and 256 vector conversions.
gcc/ChangeLog:
* config/loongarch/lasx.md (vec_cast<mode>): New template
implemention.
(vec_insert_lo_<mode>): Dito.
(vec_insert_hi_<mode>): Dito.
* config/loongarch/lasxintrin.h (defined): Test for adding
the builtin function.
(__lasx_cast_128_s): Dito.
(__lasx_cast_128_d): Dito.
(__lasx_cast_128): Dito.
(__lasx_concat_128_s): Dito.
(__lasx_concat_128_d): Dito.
(__lasx_concat_128): Dito.
(__lasx_extract_128_lo_s): Dito.
(__lasx_extract_128_hi_s): Dito.
(__lasx_extract_128_lo_d): Dito.
(__lasx_extract_128_hi_d): Dito.
(__lasx_extract_128_lo): Dito.
(__lasx_extract_128_hi): Dito.
(__lasx_insert_128_lo_s): Dito.
(__lasx_insert_128_hi_s): Dito.
(__lasx_insert_128_lo_d): Dito.
(__lasx_insert_128_hi_d): Dito.
(__lasx_insert_128_lo): Dito.
(__lasx_insert_128_hi): Dito.
* config/loongarch/loongarch-builtins.cc
(CODE_FOR_lasx_extract_128_lo_s): Add builtins and register
icode.
(CODE_FOR_lasx_extract_128_hi_s): Dito.
(CODE_FOR_lasx_extract_128_lo_d): Dito.
(CODE_FOR_lasx_extract_128_hi_d): Dito.
(CODE_FOR_lasx_extract_128_lo): Dito.
(CODE_FOR_lasx_extract_128_hi): Dito.
(CODE_FOR_lasx_insert_128_lo_s): Dito.
(CODE_FOR_lasx_insert_128_hi_s): Dito.
(CODE_FOR_lasx_insert_128_lo_d): Dito.
(CODE_FOR_lasx_insert_128_hi_d): Dito.
(CODE_FOR_lasx_insert_128_lo): Dito.
(CODE_FOR_lasx_insert_128_hi): Dito.
(CODE_FOR_lasx_concat_128_s): Dito.
(CODE_FOR_lasx_concat_128_d): Dito.
(CODE_FOR_lasx_concat_128): Dito.
(CODE_FOR_lasx_cast_128_s): Dito.
(CODE_FOR_lasx_cast_128_d): Dito.
(CODE_FOR_lasx_cast_128): Dito.
(loongarch_expand_builtin_direct): For the newly added
insertion or extraction, construct the parallel parameter
corresponding to the operand.
* config/loongarch/loongarch-c.cc
(loongarch_update_cpp_builtins): Define
__loongarch_asx_sx_conv.
* config/loongarch/loongarch-ftypes.def: Declare the type
of the builtin function.
* doc/extend.texi: Add document description.
gcc/testsuite/ChangeLog:
* gcc.target/loongarch/vector/lasx/vect-concat-128-256-result.c: New test.
* gcc.target/loongarch/vector/lasx/vect-concat-128-256.c: New test.
* gcc.target/loongarch/vector/lasx/vect-extract-256-128-result.c: New test.
* gcc.target/loongarch/vector/lasx/vect-extract-256-128.c: New test.
* gcc.target/loongarch/vector/lasx/vect-insert-128-256-result.c: New test.
* gcc.target/loongarch/vector/lasx/vect-insert-128-256.c: New test.
Lulu Cheng [Sun, 25 May 2025 03:15:07 +0000 (11:15 +0800)]
LoongArch: Optimize normal immediate data loading.
Ensure that only one register is used when loading immediate values.
The original immediate value load is handled through virtual
registers, resulting in the following load operation
(0x1234567890abcdef):
lu12i.w $r4,-456004 # 0xfffffffffff90abc
or $r12,$r0,$r0
ori $r4,$r4,3567
lu32i.d $r12,0x45678
lu32i.d $r4,0
or $r4,$r4,$r12
lu52i.d $r4,$r4,0x123
The optimized sequence is as follows:
lu12i.w $r4,-456004 # 0xfffffffffff90abc
ori $r4,$r4,3567
lu32i.d $r4,0x45678
lu52i.d $r4,$r4,0x123
gcc/ChangeLog:
* config/loongarch/loongarch.cc (loongarch_move_integer):
No new virtual register is allocated during immediate load.
Gaius Mulley [Sun, 2 Nov 2025 21:44:03 +0000 (21:44 +0000)]
PR modula2/122499: misspelt procedure in import list causes clutter
A misspelt ident in an import list causes a sequence of clutted errors.
This bug fix filters unknowns built during import lists. It also
checks for spelling mistakes against the modules exported identifiers.
gcc/m2/ChangeLog:
PR modula2/122499
* gm2-compiler/M2StackSpell.mod (PushName): Add comment.
(GetSpellHint): Rewrite.
(GetExportedSpellHint): New procedure function.
(GetScopeSpellHint): New procedure function.
* gm2-compiler/P1Build.bnf (IdentScope): Rewrite.
(PossiblyExportIdent): Ditto.
* gm2-compiler/P1SymBuild.mod (BuildImportInnerModule): Add
parameter to AddNameToImportList.
* gm2-compiler/SymbolTable.def (GetUnknownOnImport): New
procedure function.
(GetUnknownDeclScope): Ditto.
(AddNameToScope): Add tok parameter.
(AddNameToImportList): Ditto.
* gm2-compiler/SymbolTable.mod (SymUndefined): New field
declScope.
New field onImport.
(MakeObject): Add tok parameter.
(FillInUnknownFields): Initialize declScope.
Initialize onImport.
(GetUnknownOnImport): New procedure function.
(GetUnknownDeclScope): Ditto.
(AddNameToScope): Pass tok to MakeObject.
(AddNameToImportList): Add tok parameter.
Pass tok to MakeObject.
(GetDeclaredSym): Add parameters to FillInUnknownFields.
(RequestSym): Ditto.
(FetchUnknownFromModule): Ditto.
(FetchUnknownFromDefImp): Ditto.
(FetchUnknownFrom): Ditto.
gcc/testsuite/ChangeLog:
PR modula2/122499
* gm2.dg/spell/iso/fail/badimport2.mod: New test.
* gm2.dg/spell/iso/fail/badimport3.mod: New test.
* gm2.dg/spell/iso/fail/badimport4.mod: New test.
Jeff Law [Sun, 2 Nov 2025 19:48:06 +0000 (12:48 -0700)]
[RISC-V] Expose sign extension for 32 bit rotates by constant values on rv64
Trivial improvement for 32 bit rotates on rv64 that I noticed while looking at
a PR121778. We were failing to use the _extended variant when the rotation
count was a constant on rv64 after cobbling together a prototype match.pd
pattern.
I suspect the guard was added by Jivan to avoid having to muck around in the
thead bitmanip extensions. But that's a bit of speculation on my part.
I reviewed the thead extensions and they do the expected thing for the W form
rotate. So this patch adds a pattern to thead.md that exposes the sign
extension and removes the restriction on generating that form from bitmanip.md.
I can envision this will help something, somewhere, but it's generally going to
be very much on the margins. I didn't take the time to find/construct a
testcase showing the missed optimization. There is one test that triggers the
thead W form rotate (xtheadbb-srri.c), so that's got some coverage and passes
(and I verified it's using the version with the sign extension exposed, so
that's good). PR121778 will trigger the missed optimization if we add a
suitable match.pd.
Regression tested on riscv32-elf and riscv64-elf. Bootstraps on the BPI and
Pioneer are in flight, but won't be finished for a long time.
Obviously waiting on pre-commit CI before moving forward.
* config/riscv/bitmanip.md (rotrsi3): Use the sign extended form
for 32 bit rotates on TARGET_64BIT, even for constant counts.
* config/riscv/thead.md (th_srrisi3_extended): New pattern.
(th_srri<mode>3): Adjust formatting.
Eric Botcazou [Sun, 2 Nov 2025 18:36:16 +0000 (19:36 +0100)]
Ada: Fix crash on tagged private type with unknown discriminants
This is an old issue with the extension of a tagged private type declared
with unknown discriminants in the public part of a generic child unit,
although the generic context is not a key factor (i.e. this also happens
for a nongeneric child unit). The public part of a child unit does not
have visibility on the private part of its parent, so the extension also
has unknown discriminants.
gcc/ada/
PR ada/58881
* sem_ch3.adb (Build_Derived_Private_Type): Build the underlying
full view when the derivation occurs in the public part of the
scope of the parent.
(Build_Derived_Record_Type): Propagate Has_Unknown_Discriminants
in the same circumstances.
(Constrain_Discriminated_Type): Give a specific error message for
any type with the Has_Unknown_Discriminants flag.
gcc/testsuite/
* gnat.dg/specs/unknown_discr1.ads: New test.
* gnat.dg/specs/unknown_discr1_pkg.ads: New helper.
* gnat.dg/specs/unknown_discr1_pkg-child.ads: Likewise.
* gnat.dg/specs/unknown_discr1_pkg-g.ads: Likewise.
* gnat.dg/specs/unknown_discr1_pkg-inst.ads: Likewise.
AVR: target/122527 -- Don't use __load_N to load from __flash1.
This patch fixes a case where a 3 byte or 4 byte load from __flash1
uses __load_3/4 to read the value, which is wrong.
This only occured when the device has ELPM but not ELPMx (avr31).
PR target/122527
gcc/
* config/avr/avr.cc (avr_load_libgcc_p): Return false if
the address-space is not ADDR_SPACE_FLASH.
(avr_out_lpm_no_lpmx [addr=REG]): Handle sizes of 3 and 4 bytes.
Nathaniel Shead [Sun, 26 Oct 2025 11:27:33 +0000 (22:27 +1100)]
c++/modules: Track all static class variables [PR122421]
The linker error in the PR is caused because when a static is defined
out of the class body, it doesn't yet have a definition and so
read_var_def (which would otherwise have noted it) never gets called.
This instead moves the responsibility for noting class-scope variables
to read_class_def.
PR c++/122421
gcc/cp/ChangeLog:
* module.cc (trees_in::read_var_def): Don't handle class-scope
variables anymore.
(trees_in::read_class_def): Handle them here instead.
gcc/testsuite/ChangeLog:
* g++.dg/modules/inst-6_a.C: New test.
* g++.dg/modules/inst-6_b.C: New test.
Signed-off-by: Nathaniel Shead <nathanieloshead@gmail.com> Reviewed-by: Jason Merrill <jason@redhat.com>
AVR: PR122505 - Fix bloated mulpsi3 in the wake of hacking around PR118012.
Since the PR118012 work-around patch, there is an SImode insn also for
the non-MUL case, but there is no mulpsi3. This makes the middle-end
use the mulsi3 insn for 24-bit multipications like in:
__uint24 mul24 (__uint24 a, __uint24 b)
{
return a * b;
}
The patch just allows the mulpsi3 insn for the non-MUL case, except for
AVR_TINY which passes the 2nd argument on the stack so no insn can be used.
The change might be beneficial even in the absence of PR118012 because
the __mulpsi3 footprint is leaner than a libcall.
PR tree-optimization/118012
PR tree-optimization/122505
gcc/
* config/avr/avr.md (mulpsi3): Also allow the insn condition
in the case where avropt_pr118012 && !AVR_TINY.
(*mulpsi3): Handle split for the !AVR_HAVE_MUL case.
(*mulpsi3-nomul.libgcc_split, *mulpsi3-nomul.libgcc): New insns.
Shreya Munnangi [Sat, 1 Nov 2025 22:48:54 +0000 (16:48 -0600)]
[RISC-V][SH][PR rtl-optimization/67731] Improve logical IOR of single bit bitfields
This is Shreya's work except for the SH testcase which I added after realizing
her work would also fix the testcases for that port. I bootstrapped and
regression tested this on sh4-linux-gnu, x86_64 & risc-v. It also was tested
across all the embedded targets in my tester without regressions.
--
We are extracting two single-bit bitfields from a structure and
determining whether they both have the value 0 or if at least one bit is set. This has been generating poor code:
> lw a5,0(a0)
> bexti a0,a5,1
> bexti a5,a5,2
> or a0,a0,a5
> ret
We address this as a simplification problem and optimize this using an
andi of the original value and a mask with just the desired bits set,
followed by a snez. This results in a 1 if any of those bits are set or 0 if none.
For cases where we want to extract three or more single-bit bitfields, we build
on the previous case. We take the result of the 2-bitfield case, extract the
mask, update it to include the new single-bit bitfield, and again perform an
andi + snez.
In our new testfile, we scan to ensure we do not see a bexti or an or
instruction, and that we have the correct assembly for both two and three single-bit bitfield cases: lw + andi + snez + ret.
PR target/67731
gcc/
* simplify-rtx.cc (simplify_context::simplify_binary_operation_1):
Handle IOR of single bit bitfields from the same object.
gcc/testsuite/
* gcc.target/riscv/pr67731.c: New test.
* gcc.target/sh/pr67731.c: New test.
Jeff Law [Sat, 1 Nov 2025 22:27:05 +0000 (16:27 -0600)]
[RISC-V] Reorder ready queue slightly to avoid unnecessary vsetvl instructions
As I've touched on before, particularly in the patchwork meeting, we can get a
modest reduction in the number of vsetvl instructions we emit by being somewhat
smarter in how we pull instructions out of the ready queue during scheduling.
Each insn in the scheduler's ready queue has a priority which reflects the how
that insn plays in a region's critical path. The higher the priority, the more
important it is for that instruction to issue.
When we have multiple insns with the same priority in the ready queue, we can
roughly expect that issuing any insn from that set is equally good. Yes there
are secondary sort keys that incorporate register lifetime and such, but those
are just that -- secondary concerns.
Given some set of insns with the same priority, we can select whichever one we
want, so select the insn with the same vector configuration as whatever vector
instruction was last issued from the ready queue.
This will naturally tend to group vector instructions with the same vector
configuration together, thus reducing the ping-ponging of vector configurations
that we sometimes see.
When I initially cobbled this together (about a year ago) Robin reported low
single digit improvements on the BPI for x264. A lot has changed since then
and it may not be as big a win now, but I think it still has value.
This did expose that one of the move patterns in vector.md didn't have the
proper vl_op/vtype_op attributes on it. Trivially fixed.
Tested for riscv32-elf, riscv64-elf and on the Pioneer with no regressions (of
course the Pioneer won't really exercise this code). BPI is in flight, but not
due to complete for ~24hrs. We've also been running this internally for
roughly a year 🙂
Jeff Law [Sat, 1 Nov 2025 14:30:41 +0000 (08:30 -0600)]
[PR rtl-optimization/122321][RISC-V] Bounds check another access to ira_reg_equiv array
So another case where we're indexing into the ira_reg_equiv array without
checking bounds. I sincerely hope we're not playing wack-a-mole here, but two
failures in a couple months for the same core problem is worrisome.
Bootstrapped and regression tested on x86_64 and riscv64 as well as run through
all the embedded targets in my tester without regressions.
PR rtl-optimization/122321
gcc/
* lra-constraints.cc (update_equiv): Make sure REGNO is in
ira_reg_equiv before trying to update ira_reg_equiv.
gcc/testsuite/
* gcc.target/riscv/rvv/autovec/pr122321.c: New test.
Martin Uecker [Sun, 5 Oct 2025 18:53:43 +0000 (20:53 +0200)]
c: GNU extension allowing compound literals of variable size
This patch implements a GNU extension by allowing compound literals
to be VLAs which then can be initialized with an empty initializer.
This addresses a use case where one would now need to use alloca, but
this also has limitations (e.g. allocated memory accumulates in a loop).
The error for a compound literal with variable size is changed to a
pedwarn, and a new error for static and constexpr is added.
gcc/c/ChangeLog:
* c-decl.cc (build_compound_literal): Add error.
* c-parser.cc (c_parser_braced_init): Take bool argument for
variable size instead of DECL.
(c_parser_initializer,c_parser_initval): Adapt.
(c_parser_postfix_expression_after_paren_type): Change
error to pedwarn.
* c-typeck.cc (process_init_element): Add error for
variable-size compound literal with static or constexpr.
gcc/ChangeLog:
* doc/extend.texi: Document new extension.
gcc/testsuite/ChangeLog:
* gcc.dg/gnu-compoundlit-1.c: New test.
* gcc.dg/gnu-compoundlit-2.c: New test.
* gcc.dg/pr68090.c: Adapt.
* gcc.dg/vla-init-4.c: Adapt.
* gcc.dg/vla-init-5.c: Adapt.
Martin Uecker [Fri, 31 Oct 2025 15:10:40 +0000 (16:10 +0100)]
c: Fix ICE when using va_arg with arrays [PR97986]
When array type is passed to va_arg, this is undefined behavior.
Emit a warning, and insert a run-time trap after evaluating side effects,
but return the correct type for sizeof / typeof. For C90 a VLA is an
error.
If both the source and destination are address (GP) registers, emitting
instructions that invert the MSB of the address register is two bytes
shorter if TARGET_DENSITY is enabled than emitting a NEG.S machine inst-
ruction that uses hardware FP registers with two reloads.
By the way, in configurations that do not use hardware FP register, the
RTL expansion pass will emit such insns by default.
gcc/ChangeLog:
* config/xtensa/xtensa.md (negsf2):
Add another insn pattern that is valid when TARGET_DENSITY is
enabled and both the source and destination are address registers.
Due to inconsistencies in the behavior of rounding half, making this
machine instruction available was retracted in a previous commit (5f3b5b0616fe883e86e95d9476371cf87059ca7f),
but it may be useful to have it available if strict implementation of
floating-point arithmetic is not required.
gcc/ChangeLog:
* config/xtensa/xtensa.md
(c_enum "unspec", int_iterator ANY_ROUND): Add UNSPEC_ROUND.
(int_attr m_round): Add a pair of UNSPEC_ROUND and "round".
(int_attr c_round): New integer iterator attribute, that expands
to "flag_unsafe_math_optimizations" in the case of UNSPEC_ROUND,
and to "1" otherwise.
(l<m_round>sfsi2, *l<m_round>sfsi2_2x, *l<m_round>sfsi2_scaled):
Append " && <c_round>" to the conditions.
Andrew Pinski [Sat, 1 Nov 2025 03:04:38 +0000 (20:04 -0700)]
testsuite: Fix fold-vecperm-1.c for targets that don't have vectors
This testcase is testing at optimization but with targets that don't
have vectors it will fail because there will be zero VEC_PERM_EXPR.
So instead let's check earlier in say forwprop3.
Pushed as obvious after a test on x86_64-linux-gnu with -mno-sse.
gcc/testsuite/ChangeLog:
* gcc.dg/fold-vecperm-1.c: Test at forwprop3.
Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Andrew Pinski [Fri, 31 Oct 2025 21:35:41 +0000 (14:35 -0700)]
ipa: Fix pritting of symtab_node type [PR122512]
The problem here r16-4747-g529c25ed6e0a06 changed
symtab_type to toplevel_type and then added 2 types
at the begining but didn't update symtab_type_names.
This obvious patch changes symtab_type_names to toplevel_type_names,
adds a _MAX type to toplevel_type and a comment about keeping them in sync.
Also adds an static assert to make sure if someone adds a toplevel_type
that toplevel_type_names get updated too.
Pushed as obvious after a build and test.
PR ipa/122512
gcc/ChangeLog:
* cgraph.h (enum toplevel_type): Add TOPLEVEL_MAX. Add comment
about keeping toplevel_type_names in sync.
* symtab.cc (symtab_type_names): Rename to ...
(toplevel_type_names): Add new types and add an assert about
the size.
(symtab_node::get_symtab_type_string): Use toplevel_type_names
instead of symtab_type_names.
(symtab_node::dump_base): Likewise.
Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
convert:
movi v31.4s, 0
ext v0.16b, v31.16b, v0.16b, #14
ret
We generate an ext with movi because this has same latency as a shift however
it has twice the throughput. The zero vector is zero latency as such in real
workloads this codegen is much better than using shifts.
As a reminder, BF16 -> FP32 is just shifting left 16 bits.
The expand pattern has to rely on generating multiple subregs due to a
restriction that subregs can't chang floating point size and type at the same
time.
I've tried alternative approaches like using the EXT as SF mode, but the
paradoxical subreg of BF -> SF isn't allowed and using an extend doesn't work
because extend is what we're defining.
Paul Thomas [Fri, 31 Oct 2025 12:59:23 +0000 (12:59 +0000)]
Fortran: Use specific PDT constructors from a generic list [PR122452]
2025-10-31 Paul Thomas <pault@gcc.gnu.org>
gcc/fortran
PR fortran/122452
* primary.cc (gfc_match_rvalue): Give priority to specific
procedures in a generic interface with the same name as a
PDT template. If found, use as the procedure instead of the
constructor generated from the PDT template.
gcc/testsuite/
PR fortran/122452
* gfortran.dg/pdt_65.f03: New test.
Richard Biener [Fri, 31 Oct 2025 07:57:39 +0000 (08:57 +0100)]
tree-optimization/122502 - avoid folding during imm use walk with active ranger
The following works around an unfortunate interaction with ranger
and immediate use walking. An actual solution needs more thoughts.
PR tree-optimization/122502
* tree-scalar-evolution.cc (final_value_replacement_loop):
Avoid folding from within FOR_EACH_IMM_USE_STMT due to active
ranger.
Andrew Pinski [Mon, 27 Oct 2025 23:20:40 +0000 (16:20 -0700)]
fold: Remove div_if_zero_remainder [PR122437]
While looking into something related to fold-const.cc, I noticed
that div_if_zero_remainder was unused. The last use of it was
removed in r5-3374-gf65586dcd19846 (via the removal of try_move_mult_to_index),
over 11 years ago. So it is time to remove this unused function too.
Plus this function is just a small wrapper around wi::multiple_of_p but
creating trees which can get expensive so folks should use wi::multiple_of_p
directly instead.
Bootstrapped and tested on x86_64-linux-gnu.
PR tree-optimization/122437
gcc/ChangeLog:
* fold-const.cc (div_if_zero_remainder): Remove.
Signed-off-by: Andrew Pinski <andrew.pinski@oss.qualcomm.com>
Andrew Pinski [Fri, 31 Oct 2025 00:46:54 +0000 (17:46 -0700)]
sccp: Fix ICE during folding after proping const in some cases [PR122497]
In this case we originally had:
```
# g_4.3_21 = PHI <g_4.3_12(3)>
_1 = g_4.3_21 + 2;
_2 = g_2[_1][g_4.3_21];
```
SCCP figures out g_4.3_12/g_4.3_21 is 1.
final_value_replacement_loop would remove the phi defining _12.
do the constant prop of the const 1 but that would ICE as we try
to fold the reference `g_2[_1][g_4.3_21]` but that would try to see
the range of `_1` but since `_1` refers back to _21 there would be an
ICE as the phi is already been removed.
The obvious fix is to move the constant prop until after the new statement
for _21 is created.
Lulu Cheng [Thu, 6 Mar 2025 08:28:08 +0000 (16:28 +0800)]
LoongArch: Remove the "-mlasx" compilation option from the test cases.
Because LoongArch previously lacked support for 128-bit vectors
(vec_widen_{add/sub/mult}_{hi/lo}), the following test cases
needed to be enabled for 256-bit vectors to pass.
Now that 128-bit support has been added, "-mlasx" has been removed.
Lulu Cheng [Thu, 23 Oct 2025 09:14:19 +0000 (17:14 +0800)]
LoongArch: Implement the vector dot product operation with quadruple width.
The logic for the vector dot product operation, where the destination
elements are quadruple the width of the source elements, is as
follows (Take sdot_prodv4siv16qi as an example.):
Jakub Jelinek [Thu, 30 Oct 2025 21:37:33 +0000 (22:37 +0100)]
c++: Fix up and tweak std-name-hint.gperf
When converting reflection metafunction evaluation into gperf, I had
a look at the other *.gperf files in gcc/cp/.
cfns.gperf doesn't have any hash conflicts, but std-name-hint.gperf
has 7, which I believe means that for 7 of the strings it falls back to some
slow loop over not sure how many entries.
Apparently, 2 out of the 7 conflicts are just because two lines are
identically duplicated in the file, the patch included below fixes that.
2025-10-30 Jakub Jelinek <jakub@redhat.com>
* std-name-hint.gperf: Remove duplicate entries for ispanstream
and istringstream.
* std-name-hint.h: Regenerate.
Owen Avery [Thu, 2 Oct 2025 22:21:46 +0000 (18:21 -0400)]
gccrs: Improve ErrorPropagationExpr handling
gcc/rust/ChangeLog:
* ast/rust-ast-pointer-visitor.cc (PointerVisitor::visit):
Handle the expression contained in an ErrorPropagationExpr.
* ast/rust-ast-visitor.cc (DefaultASTVisitor::visit): Likewise.
gccrs: Attempt to resolve pattern items in tuple pattern with a rest pattern
gcc/rust/ChangeLog:
* typecheck/rust-hir-type-check-pattern.cc (visit(TuplePattern)): Update HAS_REST
case to continue to attempt to resolve pattern items after emitting size error.
Ryo Yoshida [Sun, 19 Oct 2025 13:45:17 +0000 (22:45 +0900)]
gccrs: Fix ICE on enum in tuple struct pattern
When we typecheck a tuple struct pattern and the type of its path is
an enum, it may refer to the enum itself and not a variant. Emit an
E0532 error on such cases.
* typecheck/rust-hir-type-check-base.cc (parse_repr_options): Changed TOKEN_TREE
assert into error, update malformed repr attribute error message to be inline
with other attribute error messages.
Lucas Ly Ba [Wed, 15 Oct 2025 15:28:36 +0000 (15:28 +0000)]
gccrs: fix inner attr derive doesn't show error
gcc/rust/ChangeLog:
* ast/rust-ast.cc (Attribute::is_derive):
Change string derive to its definition.
* util/rust-attribute-values.h:
Add attribute definition derive.
* util/rust-attributes.cc (AttributeChecker::visit):
Add method check_inner_attributes.
(AttributeChecker::check_inner_attributes):
Check if there is a bad inner attribute.
* util/rust-attributes.h:
Add method check_inner_attributes in .h.
gcc/testsuite/ChangeLog:
* rust/compile/issue-4212.rs: New test.
Signed-off-by: Lucas Ly Ba <lucas.ly-ba@outlook.fr>
Philip Herron [Sat, 4 Oct 2025 20:53:40 +0000 (21:53 +0100)]
gccrs: Refactor TyTy::ConstType into separate types
This patch refactors the const generic type system to follow the same pattern
as regular type parameters. The monolithic ConstType is split into four
distinct types:
gccrs: Implement compilation support for HIR::TupleStructItemsHasRest
gcc/rust/ChangeLog:
* backend/rust-compile-pattern.cc: Add compilation support for TupleStructItemsHasRest
in CompilePatternCheckExpr(TupleStructPattern) & CompilePatternBindings(TupleStructPattern)
gccrs: Implement lowering of AST::TupleStructItemsHasRest
gcc/rust/ChangeLog:
* hir/rust-ast-lower-pattern.cc (ASTLoweringPattern::visit(TupleStructPattern)):
Implement lowering of AST::TupleStructItemsHasRest to HIR.
* typecheck/rust-hir-type-check-pattern.cc (TypeCheckPattern::visit(TupleStructPattern)):
Add the respective type checking for AST::TupleStructItemsHasRest
* checks/errors/rust-hir-pattern-analysis.cc (lower_tuple_pattern):
Add respective pattern for HAS_REST case.
gccrs: Fix StructPattern type checking rejecting tuple struct scrutinee
Previously, type checking of StructPattern will throw an error if it is used
to match against a tuple struct, even though it is possible to do so in rustc.
gcc/rust/ChangeLog:
* typecheck/rust-hir-type-check-pattern.cc (visit(StructPattern)): Add type check
support for StructPatterns matching against a TUPLE type ADT.
* backend/rust-compile-pattern.cc(CompilePatternBindings::visit(StructPattern)):
Update assert to allow TUPLE type ADTs.
* hir/tree/rust-hir.cc (StructPatternField::as_string()): Improve info dumped.
* backend/rust-compile-extern.h: Add includes.
(CompileExternItem::visit): Use get_link_name.
(CompileExternItem::get_link_name): New static member function.
* util/rust-attribute-values.h (Attributes::LINK_NAME): New
static constexpr member variable.
* util/rust-attributes.cc (__definitions): New entry for
LINK_NAME.
* util/rust-ggc.cc: Include "rust-ast.h".
(Ident::Ident): Add overload for Rust::Identifier.
* util/rust-ggc.h (class Identifier): Forward declare.
(Ident::Ident): Add overload for Rust::Identifier.
* expand/rust-macro-expand.cc: Forward invocation tree locus to
substitution context.
* expand/rust-macro-substitute-ctx.cc: Use origin location for expanded
tokens.
* expand/rust-macro-substitute-ctx.h (class SubstituteCtx): Save
invocation location.
Builtin metavars are not in the fragment, the compiler should not emit
an error message.
gcc/rust/ChangeLog:
* expand/rust-macro-substitute-ctx.cc (is_builtin_metavariable): Add
function to check builtin metavars knowledge.
(SubstituteCtx::check_repetition_amount): Do not process missing
fragment.
Philip Herron [Mon, 22 Sep 2025 10:09:56 +0000 (11:09 +0100)]
gccrs: Add error diag for self params on plain functions
self params dont have a type unless used within impl blocks. Rustc as far as I
can tell in this senario generics a synthetic param of type Self in this senario
so that it keeps consistent error diagnostic for number of parameters but the
logic for what the parameter typpe should be seems unclear.
Philip Herron [Wed, 3 Sep 2025 09:21:06 +0000 (10:21 +0100)]
gccrs: Remove old hack from resolve operator overload
This was an old chunk of code to try and sort out the Self type on resolving
methods for impl blocks. But this is not required when our unify code works
properly.
gcc/rust/ChangeLog:
* typecheck/rust-hir-type-check-expr.cc: remove old hack
Signed-off-by: Philip Herron <herron.philip@googlemail.com>
This commit imports stdarch 1.49.0 into libgrust/rustc-lib/stdarch. This
is necessary for compiling libcore, as libcore attempts to reuse some
files from stdarch.
libgrust/ChangeLog:
* rustc-lib/stdarch/.cirrus.yml: New file.
* rustc-lib/stdarch/.github/workflows/main.yml: New file.
* rustc-lib/stdarch/.gitignore: New file.
* rustc-lib/stdarch/CONTRIBUTING.md: New file.
* rustc-lib/stdarch/Cargo.toml: New file.
* rustc-lib/stdarch/LICENSE-APACHE: New file.
* rustc-lib/stdarch/LICENSE-MIT: New file.
* rustc-lib/stdarch/README.md: New file.
* rustc-lib/stdarch/ci/android-install-ndk.sh: New file.
* rustc-lib/stdarch/ci/android-install-sdk.sh: New file.
* rustc-lib/stdarch/ci/android-sysimage.sh: New file.
* rustc-lib/stdarch/ci/docker/aarch64-linux-android/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/aarch64-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/arm-linux-androideabi/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/arm-unknown-linux-gnueabihf/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/armv7-unknown-linux-gnueabihf/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/i586-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/i686-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/mips-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/mips64-unknown-linux-gnuabi64/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/mips64el-unknown-linux-gnuabi64/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/mipsel-unknown-linux-musl/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/nvptx64-nvidia-cuda/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/powerpc-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/powerpc64-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/powerpc64le-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/s390x-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/wasm32-wasi/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/x86_64-linux-android/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu-emulated/Dockerfile: New file.
* rustc-lib/stdarch/ci/docker/x86_64-unknown-linux-gnu/Dockerfile: New file.
* rustc-lib/stdarch/ci/dox.sh: New file.
* rustc-lib/stdarch/ci/gba.json: New file.
* rustc-lib/stdarch/ci/run-docker.sh: New file.
* rustc-lib/stdarch/ci/run.sh: New file.
* rustc-lib/stdarch/ci/runtest-android.rs: New file.
* rustc-lib/stdarch/ci/style.sh: New file.
* rustc-lib/stdarch/crates/assert-instr-macro/Cargo.toml: New file.
* rustc-lib/stdarch/crates/assert-instr-macro/build.rs: New file.
* rustc-lib/stdarch/crates/assert-instr-macro/src/lib.rs: New file.
* rustc-lib/stdarch/crates/core_arch/Cargo.toml: New file.
* rustc-lib/stdarch/crates/core_arch/LICENSE-APACHE: New file.
* rustc-lib/stdarch/crates/core_arch/LICENSE-MIT: New file.
* rustc-lib/stdarch/crates/core_arch/README.md: New file.
* rustc-lib/stdarch/crates/core_arch/avx512f.md: New file.
* rustc-lib/stdarch/crates/core_arch/build.rs: New file.
* rustc-lib/stdarch/crates/core_arch/rustfmt.toml: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/crc.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/crypto.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/mod.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/generated.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/neon/mod.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/prefetch.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/test_support.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/tme.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/aarch64/v8.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/common.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/cp15.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/mod.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/not_mclass.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/barrier/v8.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/dsp.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/ex.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/hints.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/mod.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/registers/aarch32.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/registers/mod.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/registers/v6m.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/registers/v7m.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/sat.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/acle/simd32.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/arm/armclang.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/arm/crc.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/arm/mod.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/arm/neon/generated.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/arm/neon/mod.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/arm/neon/table_lookup_tests.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/arm/test_support.rs: New file.
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* rustc-lib/stdarch/crates/core_arch/src/mod.rs: New file.
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* rustc-lib/stdarch/crates/core_arch/src/x86/avx512ifma.rs: New file.
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* rustc-lib/stdarch/crates/core_arch/src/x86/ssse3.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86/tbm.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86/test.rs: New file.
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* rustc-lib/stdarch/crates/core_arch/src/x86_64/abm.rs: New file.
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* rustc-lib/stdarch/crates/core_arch/src/x86_64/avx.rs: New file.
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* rustc-lib/stdarch/crates/core_arch/src/x86_64/avx512f.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/bmi2.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/bswap.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/bt.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/cmpxchg16b.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/fxsr.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/mod.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/rdrand.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/sse.rs: New file.
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* rustc-lib/stdarch/crates/core_arch/src/x86_64/sse41.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/sse42.rs: New file.
* rustc-lib/stdarch/crates/core_arch/src/x86_64/xsave.rs: New file.
* rustc-lib/stdarch/crates/core_arch/tests/cpu-detection.rs: New file.
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* rustc-lib/stdarch/crates/std_detect/src/detect/arch/aarch64.rs: New file.
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* rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/arch/mips64.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/arch/powerpc64.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/arch/x86.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/bit.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/cache.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/error_macros.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/macros.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/mod.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/aarch64.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/aarch64.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/arm.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/auxvec.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/mod.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/freebsd/powerpc.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/aarch64.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/arm.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/auxvec.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/cpuinfo.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mips.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/mod.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/linux/powerpc.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/other.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/windows/aarch64.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/os/x86.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/detect/test_data/linux-rpi3.auxv: New file.
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* rustc-lib/stdarch/crates/std_detect/src/detect/test_data/macos-virtualbox-linux-x86-4850HQ.auxv:
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* rustc-lib/stdarch/crates/std_detect/src/lib.rs: New file.
* rustc-lib/stdarch/crates/std_detect/src/mod.rs: New file.
* rustc-lib/stdarch/crates/std_detect/tests/cpu-detection.rs: New file.
* rustc-lib/stdarch/crates/std_detect/tests/macro_trailing_commas.rs: New file.
* rustc-lib/stdarch/crates/std_detect/tests/x86-specific.rs: New file.
* rustc-lib/stdarch/crates/stdarch-gen/Cargo.toml: New file.
* rustc-lib/stdarch/crates/stdarch-gen/README.md: New file.
* rustc-lib/stdarch/crates/stdarch-gen/neon.spec: New file.
* rustc-lib/stdarch/crates/stdarch-gen/src/main.rs: New file.
* rustc-lib/stdarch/crates/stdarch-test/Cargo.toml: New file.
* rustc-lib/stdarch/crates/stdarch-test/src/disassembly.rs: New file.
* rustc-lib/stdarch/crates/stdarch-test/src/lib.rs: New file.
* rustc-lib/stdarch/crates/stdarch-test/src/wasm.rs: New file.
* rustc-lib/stdarch/crates/stdarch-verify/.gitattributes: New file.
* rustc-lib/stdarch/crates/stdarch-verify/Cargo.toml: New file.
* rustc-lib/stdarch/crates/stdarch-verify/arm-intrinsics.html: New file.
* rustc-lib/stdarch/crates/stdarch-verify/build.rs: New file.
* rustc-lib/stdarch/crates/stdarch-verify/mips-msa.h: New file.
* rustc-lib/stdarch/crates/stdarch-verify/src/lib.rs: New file.
* rustc-lib/stdarch/crates/stdarch-verify/tests/arm.rs: New file.
* rustc-lib/stdarch/crates/stdarch-verify/tests/mips.rs: New file.
* rustc-lib/stdarch/crates/stdarch-verify/tests/x86-intel.rs: New file.
* rustc-lib/stdarch/crates/stdarch-verify/x86-intel.xml: New file.
* rustc-lib/stdarch/examples/Cargo.toml: New file.
* rustc-lib/stdarch/examples/hex.rs: New file.
* rustc-lib/stdarch/examples/wasm.rs: New file.
* rustc-lib/stdarch/triagebot.toml: New file.
* rustc-lib/stdarch/vendor.yml: New file.
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