Arnd Bergmann [Thu, 5 May 2022 14:00:19 +0000 (16:00 +0200)]
Merge tag 'scmi-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers
Arm SCMI firmware driver updates/fixes for v5.19
The main theme for most of the changes this time is around the addition
of the support for SCMI v3.1 specification changes. Though one of the main
addition in the specification is the powercap protocol, that is still
work in progress and this set includes all other changes bit and pieces
scattered all around the different parts of the specification. There are
few bugs discovered during the process and associated fixes and some
refactoring to simplify the addition of v3.1 support. It mainly includes
the support for extended names, few newly added notifications and async
command support.
Apart from v3.1 SCMI changes, OPTEE transport gets support for dynamic
shared memory.
* tag 'scmi-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (24 commits)
firmware: arm_scmi: Fix late checks on pointer dereference
firmware: arm_scmi: Support optee shared memory in the optee transport
firmware: arm_scmi: Add SCMI v3.1 VOLTAGE_LEVEL_SET_COMPLETE
firmware: arm_scmi: Add SCMI v3.1 clock notifications
firmware: arm_scmi: Add checks for min/max limits in PERFORMANCE_LIMITS_SET
firmware: arm_scmi: Add SCMI v3.1 perf power-cost in microwatts
firmware: arm_scmi: Use common iterators in the perf protocol
firmware: arm_scmi: Use common iterators in the voltage protocol
firmware: arm_scmi: Use common iterators in the clock protocol
firmware: arm_scmi: Add SCMI v3.1 SENSOR_AXIS_NAME_GET support
firmware: arm_scmi: Use common iterators in the sensor protocol
firmware: arm_scmi: Add iterators for multi-part commands
firmware: arm_scmi: Parse clock_enable_latency conditionally
firmware: arm_scmi: Set clock latency to U32_MAX if it is not supported
firmware: arm_scmi: Add SCMI v3.1 protocol extended names support
firmware: arm_scmi: Introduce a common SCMI v3.1 .extended_name_get helper
firmware: arm_scmi: Split protocol specific definitions in a dedicated header
firmware: arm_scmi: Remove unneeded NULL termination of clk name
firmware: arm_scmi: Check CLOCK_RATE_SET_COMPLETE async response
firmware: arm_scmi: Make name_get operations return a const
...
Nicholas Piggin [Wed, 30 Mar 2022 14:07:19 +0000 (19:37 +0530)]
powerpc/64: remove system call instruction emulation
emulate_step() instruction emulation including sc instruction emulation
initially appeared in xmon. It was then moved into sstep.c where kprobes
could use it too, and later hw_breakpoint and uprobes started to use it.
Until uprobes, the only instruction emulation users were for kernel
mode instructions.
- xmon only steps / breaks on kernel addresses.
- kprobes is kernel only.
- hw_breakpoint only emulates kernel instructions, single steps user.
At one point, there was support for the kernel to execute sc
instructions, although that is long removed and it's not clear whether
there were any in-tree users. So system call emulation is not required
by the above users.
uprobes uses emulate_step and it appears possible to emulate sc
instruction in userspace. Userspace system call emulation is broken and
it's not clear it ever worked well.
The big complication is that userspace takes an interrupt to the kernel
to emulate the instruction. The user->kernel interrupt sets up registers
and interrupt stack frame expecting to return to userspace, then system
call instruction emulation re-directs that stack frame to the kernel,
early in the system call interrupt handler. This means the interrupt
return code takes the kernel->kernel restore path, which does not
restore everything as the system call interrupt handler would expect
coming from userspace. regs->iamr appears to get lost for example,
because the kernel->kernel return does not restore the user iamr.
Accounting such as irqflags tracing and CPU accounting does not get
flipped back to user mode as the system call handler expects, so those
appear to enter the kernel twice without returning to userspace.
These things may be individually fixable with various complication, but
it is a big complexity for unclear real benefit.
Furthermore, it is not possible to single step a system call instruction
since it causes an interrupt. As such, a separate patch disables probing
on system call instructions.
This patch removes system call emulation and disables stepping system
calls.
Naveen N. Rao [Wed, 30 Mar 2022 14:07:18 +0000 (19:37 +0530)]
powerpc: Reject probes on instructions that can't be single stepped
Per the ISA, a Trace interrupt is not generated for:
- [h|u]rfi[d]
- rfscv
- sc, scv, and Trap instructions that trap
- Power-Saving Mode instructions
- other instructions that cause interrupts (other than Trace interrupts)
- the first instructions of any interrupt handler (applies to Branch and Single Step tracing;
CIABR matches may still occur)
- instructions that are emulated by software
Add a helper to check for instructions belonging to the first four
categories above and to reject kprobes, uprobes and xmon breakpoints on
such instructions. We reject probing on instructions belonging to these
categories across all ISA versions and across both BookS and BookE.
For trap instructions, we can't know in advance if they can cause a
trap, and there is no good reason to allow probing on those. Also,
uprobes already refuses to probe trap instructions and kprobes does not
allow probes on trap instructions used for kernel warnings and bugs. As
such, stop allowing any type of probes/breakpoints on trap instruction
across uprobes, kprobes and xmon.
For some of the fp/altivec instructions that can generate an interrupt
and which we emulate in the kernel (altivec assist, for example), we
check and turn off single stepping in emulate_single_step().
Instructions generating a DSI are restarted and single stepping normally
completes once the instruction is completed.
In uprobes, if a single stepped instruction results in a non-fatal
signal to be delivered to the task, such signals are "delayed" until
after the instruction completes. For fatal signals, single stepping is
cancelled and the instruction restarted in-place so that core dump
captures proper addresses.
In kprobes, we do not allow probes on instructions having an extable
entry and we also do not allow probing interrupt vectors.
Arnd Bergmann [Thu, 5 May 2022 13:59:27 +0000 (15:59 +0200)]
Merge tag 'ffa-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers
Arm FF-A firmware driver updates/fixes for v5.19
Couple of fixes to handle fragmented memory descriptors and incorrect
UUID parameter passed to ffa_partition_probe. Another fix deals with
the incorrect use of ffa_device's driver_data by the core driver.
Apart from these fixes, there is an addition of ffa_dev_get_drvdata helper
function and its use in optee driver.
* tag 'ffa-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
tee: optee: Use ffa_dev_get_drvdata to fetch driver_data
firmware: arm_ffa: Add ffa_dev_get_drvdata helper function
firmware: arm_ffa: Remove incorrect assignment of driver_data
firmware: arm_ffa: Fix uuid parameter to ffa_partition_probe
firmware: arm_ffa: Fix handling of fragmented memory descriptors
Arnd Bergmann [Thu, 5 May 2022 13:21:00 +0000 (15:21 +0200)]
Merge tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux into arm/drivers
Reset controller updates for v5.19
Add Meson-S4 SoC reset controller support to reset-meson, AST2600 LPC
reset controller support to reset-simple, and R9A07G054 USBPHY reset
controller support to reset-rzg2l-usbphy-ctrl. Add ACPI _RST support to
device_reset(), simplify the uniphier-glue reset driver using bulk API
and devres and clean up its dt-bindings docs. Convert most dt-bindings
docs from txt to yaml.
* tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux:
dt-bindings: reset: st,sti-powerdown: Convert to yaml
dt-bindings: reset: st,sti-picophyreset: Convert to yaml
dt-bindings: reset: socfpga: Convert to yaml
dt-bindings: reset: snps,axs10x-reset: Convert to yaml
dt-bindings: reset: nuvoton,npcm-reset: Convert to yaml
dt-bindings: reset: lantiq,reset: Convert to yaml
dt-bindings: reset: bitmain,bm1880-reset: Convert to yaml
dt-bindings: reset: berlin: Convert to yaml
dt-bindings: reset: ath79: Convert to yaml
dt-bindings: reset: amlogic,meson-axg-audio-arb: Convert to yaml
dt-bindings: reset: uniphier-glue: Clean up clocks, resets, and their names using compatible string
reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L
reset: ACPI reset support
reset: simple: Add AST2600 compatible
reset: reset-meson: add support for the Meson-S4 SoC Reset Controller
dt-bindings: reset: add bindings for the Meson-S4 SoC Reset Controller
dt-bindings: reset: Add compatible for Meson-S4 Reset Controller
reset: uniphier-glue: Use devm_add_action_or_reset()
reset: uniphier-glue: Use reset_control_bulk API
Jon Hunter [Wed, 4 May 2022 14:44:06 +0000 (15:44 +0100)]
gpio: max77620: Make the irqchip immutable
Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips. Following this change the following warning is
now observed for the max77620 gpio driver ...
WARNING KERN gpio gpiochip0: (max77620-gpio): not an immutable chip,
please consider fixing it!
Fix the above warning by making the max77620 gpio driver immutable.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com> Reviewed-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
The fwnode of GPIO IRQ must be set to its own fwnode, not the fwnode of the
parent IRQ. Therefore, this sets own fwnode instead of the parent IRQ fwnode to
GPIO IRQ's.
gpio: max732x: Drop unused support for irq and setup code via platform data
The only user of max732x_platform_data is arch/arm/mach-pxa/littleton.c
and it only uses .gpio_base. So drop the other members from the data struct
and simplify the driver accordingly.
The motivating side effect of this change is that the .remove() callback
cannot return a nonzero error code any more which prepares making i2c
remove callbacks return void.
Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com> Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com> Signed-off-by: Jai Luthra <j-luthra@ti.com> Link: https://lore.kernel.org/r/20220505111226.29217-1-j-luthra@ti.com Signed-off-by: Mark Brown <broonie@kernel.org>
Peter Ujfalusi [Thu, 5 May 2022 09:48:17 +0000 (12:48 +0300)]
ASoC: SOF: Add initial header file for ipc4
The header file contains essential structure definitions, description of
bit fields and bits in the ipc4 header and an internally used ipc4 message
container definition.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/20220505094818.10346-3-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
Peter Ujfalusi [Thu, 5 May 2022 09:48:16 +0000 (12:48 +0300)]
ASoC: SOF: Add rx_data pointer to snd_sof_ipc_msg struct
The rx_data pointer can be used by IPC implementations to pass the received
message (or part of the message, like the header) from platform code to
generic, high level IPC code.
IPC4 is going to be the first user of this as its implementation on Intel
platforms detaches the header and payload and the rx cannot be handled in
a similar way as it is implemented for ipc3.
If the rx_data is dynamically allocated, it is up to the platform code to
free it up.
After the message reception handling (rx_msg ops) returned, the pointer via
the msg->rx_data should be considered as invalid.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com> Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com> Reviewed-by: Rander Wang <rander.wang@intel.com> Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com> Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com> Link: https://lore.kernel.org/r/20220505094818.10346-2-peter.ujfalusi@linux.intel.com Signed-off-by: Mark Brown <broonie@kernel.org>
Marek Vasut [Sat, 30 Apr 2022 02:51:44 +0000 (04:51 +0200)]
regmap: Add bulk read/write callbacks into regmap_config
Currently the regmap_config structure only allows the user to implement
single element register read/write using .reg_read/.reg_write callbacks.
The regmap_bus already implements bulk counterparts of both, and is being
misused as a workaround for the missing bulk read/write callbacks in
regmap_config by a couple of drivers. To stop this misuse, add the bulk
read/write callbacks to regmap_config and call them from the regmap core
code.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Jagan Teki <jagan@amarulasolutions.com> Cc: Mark Brown <broonie@kernel.org> Cc: Maxime Ripard <maxime@cerno.tech> Cc: Robert Foss <robert.foss@linaro.org> Cc: Sam Ravnborg <sam@ravnborg.org> Cc: Thomas Zimmermann <tzimmermann@suse.de>
To: dri-devel@lists.freedesktop.org Link: https://lore.kernel.org/r/20220430025145.640305-1-marex@denx.de Signed-off-by: Mark Brown <broonie@kernel.org>
Douglas Anderson [Fri, 29 Apr 2022 23:43:47 +0000 (16:43 -0700)]
device property: Fix recent breakage of fwnode_get_next_parent_dev()
Due to a subtle typo, instead of commit 87ffea09470d ("device
property: Introduce fwnode_for_each_parent_node()") being a no-op
change, it ended up causing the display on my sc7180-trogdor-lazor
device from coming up unless I added "fw_devlink=off" to my kernel
command line. Fix the typo.
Fixes: 87ffea09470d ("device property: Introduce fwnode_for_each_parent_node()") Signed-off-by: Douglas Anderson <dianders@chromium.org> Reviewed-by: Saravana Kannan <saravanak@google.com> Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
So far the RELACOUNT tag from the ELF header was containing the exact
number of R_PPC_RELATIVE/R_PPC64_RELATIVE relocations. However the LLVM's
recent change [1] make it equal-or-less than the actual number which
makes it useless.
This replaces RELACOUNT in zImage loader with a pair of RELASZ and RELAENT.
The vmlinux relocation code is fixed in commit d79976918852
("powerpc/64: Add UADDR64 relocation support").
To make it more future proof, this walks through the entire .rela.dyn
section instead of assuming that the section is sorter by a relocation
type. Unlike d79976918852, this does not add unaligned UADDR/UADDR64
relocations as we are likely not to see those in practice - the zImage
is small and very arch specific so there is a smaller chance that some
generic feature (such as PRINK_INDEX) triggers unaligned relocations.
powerpc/mm: Convert to default topdown mmap layout
Select CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT and
remove arch/powerpc/mm/mmap.c
This change reuses the generic framework added by
commit 67f3977f805b ("arm64, mm: move generic mmap layout
functions to mm") without any functional change.
Comparison between powerpc implementation and the generic one:
- mmap_is_legacy() is identical.
- arch_mmap_rnd() does exactly the same allthough it's written
slightly differently.
- MIN_GAP and MAX_GAP are identical.
- mmap_base() does the same but uses STACK_RND_MASK which provides
the same values as stack_maxrandom_size().
- arch_pick_mmap_layout() is identical.
powerpc/mm: Enable full randomisation of memory mappings
Do like most other architectures and provide randomisation also to
"legacy" memory mappings, by adding the random factor to
mm->mmap_base in arch_pick_mmap_layout().
See commit 8b8addf891de ("x86/mm/32: Enable full randomization on
i386 and X86_32") for all explanations and benefits of that mmap
randomisation.
At the moment, slice_find_area_bottomup() doesn't use mm->mmap_base
but uses the fixed TASK_UNMAPPED_BASE instead.
slice_find_area_bottomup() being used as a fallback to
slice_find_area_topdown(), it can't use mm->mmap_base
directly.
Instead of always using TASK_UNMAPPED_BASE as base address, leave
it to the caller. When called from slice_find_area_topdown()
TASK_UNMAPPED_BASE is used. Otherwise mm->mmap_base is used.
powerpc/mm: Move get_unmapped_area functions to slice.c
hugetlb_get_unmapped_area() is now identical to the
generic version if only RADIX is enabled, so move it
to slice.c and let it fallback on the generic one
when HASH MMU is not compiled in.
Do the same with arch_get_unmapped_area() and
arch_get_unmapped_area_topdown().
powerpc/mm: Use generic_get_unmapped_area() and call it from arch_get_unmapped_area()
Use the generic version of arch_get_unmapped_area() which
is now available at all time instead of its copy
radix__arch_get_unmapped_area()
To allow that for PPC64, add arch_get_mmap_base() and
arch_get_mmap_end() macros.
Instead of setting mm->get_unmapped_area() to either
arch_get_unmapped_area() or generic_get_unmapped_area(),
always set it to arch_get_unmapped_area() and call
generic_get_unmapped_area() from there when radix is enabled.
Do the same with radix__arch_get_unmapped_area_topdown()
mm, hugetlbfs: Allow an arch to always use generic versions of get_unmapped_area functions
Unlike most architectures, powerpc can only define at runtime
if it is going to use the generic arch_get_unmapped_area() or not.
Today, powerpc has a copy of the generic arch_get_unmapped_area()
because when selection HAVE_ARCH_UNMAPPED_AREA the generic
arch_get_unmapped_area() is not available.
Rename it generic_get_unmapped_area() and make it independent of
HAVE_ARCH_UNMAPPED_AREA.
Do the same for arch_get_unmapped_area_topdown() versus
HAVE_ARCH_UNMAPPED_AREA_TOPDOWN.
Do the same for hugetlb_get_unmapped_area() versus
HAVE_ARCH_HUGETLB_UNMAPPED_AREA.
mm: Allow arch specific arch_randomize_brk() with CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
Commit e7142bf5d231 ("arm64, mm: make randomization selected by
generic topdown mmap layout") introduced a default version of
arch_randomize_brk() provided when
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT is selected.
powerpc could select CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
but needs to provide its own arch_randomize_brk().
In order to allow that, define generic version of arch_randomize_brk()
as a __weak symbol.
Merge master into next, to bring in commit 5f24d5a579d1 ("mm, hugetlb:
allow for "high" userspace addresses"), which is needed as a
prerequisite for the series converting powerpc to the generic mmap
logic.
Sven Schwermer [Mon, 25 Apr 2022 14:34:50 +0000 (16:34 +0200)]
USB: serial: option: add Fibocom MA510 modem
The MA510 modem has 3 USB configurations that are configurable via the AT
command AT+GTUSBMODE={30,31,32} which make the modem enumerate with the
following interfaces, respectively:
Sven Schwermer [Mon, 25 Apr 2022 14:34:49 +0000 (16:34 +0200)]
USB: serial: option: add Fibocom L610 modem
The L610 modem has 3 USB configurations that are configurable via the AT
command AT+GTUSBMODE={31,32,33} which make the modem enumerate with the
following interfaces, respectively:
31: Modem + NV + MOS + Diag + LOG + AT + AT
32: ECM + Modem + NV + MOS + Diag + LOG + AT + AT
33: RNDIS + Modem + NV + MOS + Diag + LOG + AT + AT
A detailed description of the USB configuration for each mode follows:
Phil Edworthy [Tue, 3 May 2022 11:55:54 +0000 (12:55 +0100)]
clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
single bit per module.
Phil Edworthy [Tue, 3 May 2022 11:55:52 +0000 (12:55 +0100)]
clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
All of the muxes and dividers that can be modified require the HIWORD
flags, so make the macros set them. It won't affect read only muxes and
dividers.
This will make the clock tables a little easier to read, particularly for
new SoCs coming.
Phil Edworthy [Tue, 3 May 2022 11:55:50 +0000 (12:55 +0100)]
clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
We only ever use ARRAY_SIZE() to populate the number of parents, so
move this into the macro to always detect it automatically. This
also makes the tables of clocks a little simpler.
Similarly for the DEF_SD_MUX macro.
Biju Das [Sat, 30 Apr 2022 11:41:48 +0000 (12:41 +0100)]
clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
from DSI divider which is connected to PLL5_4 MUX.
This patch adds support for generating FOUTPOSTDIV clk.
pinctrl: renesas: checker: Add reserved field checks
Add checks for discovering registers with reserved fields that could
benefit from being described using variable-width reserved field
shorthands, reducing kernel size.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.
Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.