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4 years agoMerge tag 'scmi-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep...
Arnd Bergmann [Thu, 5 May 2022 14:00:19 +0000 (16:00 +0200)] 
Merge tag 'scmi-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers

Arm SCMI firmware driver updates/fixes for v5.19

The main theme for most of the changes this time is around the addition
of the support for SCMI v3.1 specification changes. Though one of the main
addition in the specification is the powercap protocol, that is still
work in progress and this set includes all other changes bit and pieces
scattered all around the different parts of the specification. There are
few bugs discovered during the process and associated fixes and some
refactoring to simplify the addition of v3.1 support. It mainly includes
the support for extended names, few newly added notifications and async
command support.

Apart from v3.1 SCMI changes, OPTEE transport gets support for dynamic
shared memory.

* tag 'scmi-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux: (24 commits)
  firmware: arm_scmi: Fix late checks on pointer dereference
  firmware: arm_scmi: Support optee shared memory in the optee transport
  firmware: arm_scmi: Add SCMI v3.1 VOLTAGE_LEVEL_SET_COMPLETE
  firmware: arm_scmi: Add SCMI v3.1 clock notifications
  firmware: arm_scmi: Add checks for min/max limits in PERFORMANCE_LIMITS_SET
  firmware: arm_scmi: Add SCMI v3.1 perf power-cost in microwatts
  firmware: arm_scmi: Use common iterators in the perf protocol
  firmware: arm_scmi: Use common iterators in the voltage protocol
  firmware: arm_scmi: Use common iterators in the clock protocol
  firmware: arm_scmi: Add SCMI v3.1 SENSOR_AXIS_NAME_GET support
  firmware: arm_scmi: Use common iterators in the sensor protocol
  firmware: arm_scmi: Add iterators for multi-part commands
  firmware: arm_scmi: Parse clock_enable_latency conditionally
  firmware: arm_scmi: Set clock latency to U32_MAX if it is not supported
  firmware: arm_scmi: Add SCMI v3.1 protocol extended names support
  firmware: arm_scmi: Introduce a common SCMI v3.1 .extended_name_get helper
  firmware: arm_scmi: Split protocol specific definitions in a dedicated header
  firmware: arm_scmi: Remove unneeded NULL termination of clk name
  firmware: arm_scmi: Check CLOCK_RATE_SET_COMPLETE async response
  firmware: arm_scmi: Make name_get operations return a const
  ...

Link: https://lore.kernel.org/r/20220504112906.3491985-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
4 years agopowerpc: Include asm/reg.h in asm/svm.h
Christophe Leroy [Tue, 8 Mar 2022 19:20:22 +0000 (20:20 +0100)] 
powerpc: Include asm/reg.h in asm/svm.h

is_secure_guest() uses mfmsr().

Don't rely on users to include asm/reg.h, include
it in asm/svm.h

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/482c82c8a29d5fb3ea279b34f107e0e775001344.1646767214.git.christophe.leroy@csgroup.eu
4 years agopowerpc: Don't include asm/prom.h in asm/parport.h
Christophe Leroy [Tue, 8 Mar 2022 19:20:21 +0000 (20:20 +0100)] 
powerpc: Don't include asm/prom.h in asm/parport.h

parport.h needs only of_irq.h, no need to go via asm/prom.h

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/ec796ee56cf61f16ba24e62a9d3525d11931538c.1646767214.git.christophe.leroy@csgroup.eu
4 years agopowerpc/64: Move pci_device_from_OF_node() out of asm/pci-bridge.h
Christophe Leroy [Tue, 8 Mar 2022 19:20:20 +0000 (20:20 +0100)] 
powerpc/64: Move pci_device_from_OF_node() out of asm/pci-bridge.h

Move pci_device_from_OF_node() in pci64.c because it needs definition
of struct device_node and is not worth inlining.

ppc32.c already has it in pci32.c.

That way pci-bridge.h doesn't need linux/of.h (Brought by asm/prom.h
via asm/pci.h)

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/3c88286b55413730d7784133993a46ef4a3607ce.1646767214.git.christophe.leroy@csgroup.eu
4 years agopowerpc: Reduce csum_add() complexity for PPC64
Christophe Leroy [Sat, 12 Feb 2022 07:36:17 +0000 (08:36 +0100)] 
powerpc: Reduce csum_add() complexity for PPC64

PPC64 does everything in C, gcc is able to skip calculation
when one of the operands in zero.

Move the constant folding in PPC32 part.

This helps GCC and reduces ppc64_defconfig by 170 bytes.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/a4ca63dd4c4b09e1906d08fb814af5a41d0f3fcb.1644651363.git.christophe.leroy@csgroup.eu
4 years agopowerpc/64: remove system call instruction emulation
Nicholas Piggin [Wed, 30 Mar 2022 14:07:19 +0000 (19:37 +0530)] 
powerpc/64: remove system call instruction emulation

emulate_step() instruction emulation including sc instruction emulation
initially appeared in xmon. It was then moved into sstep.c where kprobes
could use it too, and later hw_breakpoint and uprobes started to use it.

Until uprobes, the only instruction emulation users were for kernel
mode instructions.

- xmon only steps / breaks on kernel addresses.
- kprobes is kernel only.
- hw_breakpoint only emulates kernel instructions, single steps user.

At one point, there was support for the kernel to execute sc
instructions, although that is long removed and it's not clear whether
there were any in-tree users. So system call emulation is not required
by the above users.

uprobes uses emulate_step and it appears possible to emulate sc
instruction in userspace. Userspace system call emulation is broken and
it's not clear it ever worked well.

The big complication is that userspace takes an interrupt to the kernel
to emulate the instruction. The user->kernel interrupt sets up registers
and interrupt stack frame expecting to return to userspace, then system
call instruction emulation re-directs that stack frame to the kernel,
early in the system call interrupt handler. This means the interrupt
return code takes the kernel->kernel restore path, which does not
restore everything as the system call interrupt handler would expect
coming from userspace. regs->iamr appears to get lost for example,
because the kernel->kernel return does not restore the user iamr.
Accounting such as irqflags tracing and CPU accounting does not get
flipped back to user mode as the system call handler expects, so those
appear to enter the kernel twice without returning to userspace.

These things may be individually fixable with various complication, but
it is a big complexity for unclear real benefit.

Furthermore, it is not possible to single step a system call instruction
since it causes an interrupt. As such, a separate patch disables probing
on system call instructions.

This patch removes system call emulation and disables stepping system
calls.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
[minor commit log edit, and also get rid of '#ifdef CONFIG_PPC64']
Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/a412e3b3791ed83de18704c8d90f492e7a0049c0.1648648712.git.naveen.n.rao@linux.vnet.ibm.com
4 years agopowerpc: Reject probes on instructions that can't be single stepped
Naveen N. Rao [Wed, 30 Mar 2022 14:07:18 +0000 (19:37 +0530)] 
powerpc: Reject probes on instructions that can't be single stepped

Per the ISA, a Trace interrupt is not generated for:
- [h|u]rfi[d]
- rfscv
- sc, scv, and Trap instructions that trap
- Power-Saving Mode instructions
- other instructions that cause interrupts (other than Trace interrupts)
- the first instructions of any interrupt handler (applies to Branch and Single Step tracing;
CIABR matches may still occur)
- instructions that are emulated by software

Add a helper to check for instructions belonging to the first four
categories above and to reject kprobes, uprobes and xmon breakpoints on
such instructions. We reject probing on instructions belonging to these
categories across all ISA versions and across both BookS and BookE.

For trap instructions, we can't know in advance if they can cause a
trap, and there is no good reason to allow probing on those. Also,
uprobes already refuses to probe trap instructions and kprobes does not
allow probes on trap instructions used for kernel warnings and bugs. As
such, stop allowing any type of probes/breakpoints on trap instruction
across uprobes, kprobes and xmon.

For some of the fp/altivec instructions that can generate an interrupt
and which we emulate in the kernel (altivec assist, for example), we
check and turn off single stepping in emulate_single_step().

Instructions generating a DSI are restarted and single stepping normally
completes once the instruction is completed.

In uprobes, if a single stepped instruction results in a non-fatal
signal to be delivered to the task, such signals are "delayed" until
after the instruction completes. For fatal signals, single stepping is
cancelled and the instruction restarted in-place so that core dump
captures proper addresses.

In kprobes, we do not allow probes on instructions having an extable
entry and we also do not allow probing interrupt vectors.

Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/f56ee979d50b8711fae350fc97870f3ca34acd75.1648648712.git.naveen.n.rao@linux.vnet.ibm.com
4 years agopowerpc: Sort and de-dup primary opcodes in ppc-opcode.h
Naveen N. Rao [Wed, 30 Mar 2022 14:07:17 +0000 (19:37 +0530)] 
powerpc: Sort and de-dup primary opcodes in ppc-opcode.h

Some of the primary opcodes are duplicated. Remove those, and sort the
rest of the primary opcodes to make it easy to read.

Signed-off-by: Naveen N. Rao <naveen.n.rao@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/a05edf638a2638d708fc2db0272f6317837b5eab.1648648712.git.naveen.n.rao@linux.vnet.ibm.com
4 years agoMerge tag 'ffa-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep...
Arnd Bergmann [Thu, 5 May 2022 13:59:27 +0000 (15:59 +0200)] 
Merge tag 'ffa-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into arm/drivers

Arm FF-A firmware driver updates/fixes for v5.19

Couple of fixes to handle fragmented memory descriptors and incorrect
UUID parameter passed to ffa_partition_probe. Another fix deals with
the incorrect use of ffa_device's driver_data by the core driver.
Apart from these fixes, there is an addition of ffa_dev_get_drvdata helper
function and its use in optee driver.

* tag 'ffa-updates-5.19' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  tee: optee: Use ffa_dev_get_drvdata to fetch driver_data
  firmware: arm_ffa: Add ffa_dev_get_drvdata helper function
  firmware: arm_ffa: Remove incorrect assignment of driver_data
  firmware: arm_ffa: Fix uuid parameter to ffa_partition_probe
  firmware: arm_ffa: Fix handling of fragmented memory descriptors

Link: https://lore.kernel.org/r/20220504112853.3491961-1-sudeep.holla@arm.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
4 years agoMerge tag 'tee-shm-vmalloc-for-v5.19' of https://git.linaro.org/people/jens.wiklander...
Arnd Bergmann [Thu, 5 May 2022 13:56:54 +0000 (15:56 +0200)] 
Merge tag 'tee-shm-vmalloc-for-v5.19' of https://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers

TEE accept vmalloc()ed buffers for tee_shm_register_kernel_buf()

* tag 'tee-shm-vmalloc-for-v5.19' of https://git.linaro.org/people/jens.wiklander/linux-tee:
  tee: make tee_shm_register_kernel_buf vmalloc supported

Link: https://lore.kernel.org/r/20220503192916.GA3288817@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
4 years agoMerge tag 'tee-menu-for-v5.19' of https://git.linaro.org/people/jens.wiklander/linux...
Arnd Bergmann [Thu, 5 May 2022 13:48:31 +0000 (15:48 +0200)] 
Merge tag 'tee-menu-for-v5.19' of https://git.linaro.org/people/jens.wiklander/linux-tee into arm/drivers

Combine TEE config and menu in one line

* tag 'tee-menu-for-v5.19' of https://git.linaro.org/people/jens.wiklander/linux-tee:
  tee: combine "config" and "menu" for TEE's menuconfig

Link: https://lore.kernel.org/r/20220503191626.GA3278203@jade
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
4 years agoMerge tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux into arm/drivers
Arnd Bergmann [Thu, 5 May 2022 13:21:00 +0000 (15:21 +0200)] 
Merge tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux into arm/drivers

Reset controller updates for v5.19

Add Meson-S4 SoC reset controller support to reset-meson, AST2600 LPC
reset controller support to reset-simple, and R9A07G054 USBPHY reset
controller support to reset-rzg2l-usbphy-ctrl. Add ACPI _RST support to
device_reset(), simplify the uniphier-glue reset driver using bulk API
and devres and clean up its dt-bindings docs. Convert most dt-bindings
docs from txt to yaml.

* tag 'reset-for-v5.19' of git://git.pengutronix.de/pza/linux:
  dt-bindings: reset: st,sti-powerdown: Convert to yaml
  dt-bindings: reset: st,sti-picophyreset: Convert to yaml
  dt-bindings: reset: socfpga: Convert to yaml
  dt-bindings: reset: snps,axs10x-reset: Convert to yaml
  dt-bindings: reset: nuvoton,npcm-reset: Convert to yaml
  dt-bindings: reset: lantiq,reset: Convert to yaml
  dt-bindings: reset: bitmain,bm1880-reset: Convert to yaml
  dt-bindings: reset: berlin: Convert to yaml
  dt-bindings: reset: ath79: Convert to yaml
  dt-bindings: reset: amlogic,meson-axg-audio-arb: Convert to yaml
  dt-bindings: reset: uniphier-glue: Clean up clocks, resets, and their names using compatible string
  reset: Kconfig: Make RESET_RZG2L_USBPHY_CTRL depend on ARCH_RZG2L
  reset: ACPI reset support
  reset: simple: Add AST2600 compatible
  reset: reset-meson: add support for the Meson-S4 SoC Reset Controller
  dt-bindings: reset: add bindings for the Meson-S4 SoC Reset Controller
  dt-bindings: reset: Add compatible for Meson-S4 Reset Controller
  reset: uniphier-glue: Use devm_add_action_or_reset()
  reset: uniphier-glue: Use reset_control_bulk API

Link: https://lore.kernel.org/r/20220503160057.46625-1-p.zabel@pengutronix.de
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
4 years agoUSB: serial: qcserial: add support for Sierra Wireless EM7590
Ethan Yang [Mon, 25 Apr 2022 05:58:40 +0000 (13:58 +0800)] 
USB: serial: qcserial: add support for Sierra Wireless EM7590

Add support for Sierra Wireless EM7590 0xc080/0xc081 compositions.

Signed-off-by: Ethan Yang <etyang@sierrawireless.com>
Link: https://lore.kernel.org/r/20220425055840.5693-1-etyang@sierrawireless.com
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
4 years agonet: sparx5: Add handling of host MDB entries
Casper Andersson [Tue, 3 May 2022 09:39:22 +0000 (11:39 +0200)] 
net: sparx5: Add handling of host MDB entries

Handle adding and removing MDB entries for host

Signed-off-by: Casper Andersson <casper.casan@gmail.com>
Link: https://lore.kernel.org/r/20220503093922.1630804-1-casper.casan@gmail.com
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
4 years agoMerge branch 'irq/gpio-immutable' of git://git.kernel.org/pub/scm/linux/kernel/git...
Bartosz Golaszewski [Thu, 5 May 2022 13:03:29 +0000 (15:03 +0200)] 
Merge branch 'irq/gpio-immutable' of git://git.kernel.org/pub/scm/linux/kernel/git/maz/arm-platforms into gpio/for-next

This pulls in changes improving the handling of immutable irqchips in core
gpiolib and several drivers.

4 years agogpio: max77620: Make the irqchip immutable
Jon Hunter [Wed, 4 May 2022 14:44:06 +0000 (15:44 +0100)] 
gpio: max77620: Make the irqchip immutable

Commit 6c846d026d49 ("gpio: Don't fiddle with irqchips marked as
immutable") added a warning to indicate if the gpiolib is altering the
internals of irqchips. Following this change the following warning is
now observed for the max77620 gpio driver ...

 WARNING KERN gpio gpiochip0: (max77620-gpio): not an immutable chip,
  please consider fixing it!

Fix the above warning by making the max77620 gpio driver immutable.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
4 years agoARM: dts: imx7d-smegw01: Add support for i.MX7D SMEGW01 board
Fabio Estevam [Thu, 5 May 2022 11:19:05 +0000 (08:19 -0300)] 
ARM: dts: imx7d-smegw01: Add support for i.MX7D SMEGW01 board

Add support for the i.MX7D SMEGW01 board.

This is a gateway board that supports the following peripherals:

- eMMC / SD card
- RTC
- USB modem
- Wifi via SDIO
- Dual Ethernet
- CAN
- Serial SRAM

Signed-off-by: Fabio Estevam <festevam@denx.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agodt-bindings: arm: fsl: Add Storopack i.MX7D SMEGW01 board
Fabio Estevam [Thu, 5 May 2022 11:19:04 +0000 (08:19 -0300)] 
dt-bindings: arm: fsl: Add Storopack i.MX7D SMEGW01 board

Add DT compatible string for Storopack i.MX7D SMEGW01 board.

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agodt-bindings: vendor-prefixes: Add prefix for Storopack
Fabio Estevam [Thu, 5 May 2022 11:19:03 +0000 (08:19 -0300)] 
dt-bindings: vendor-prefixes: Add prefix for Storopack

Add a vendor prefix entry for Storopack (https://www.storopack.com).

Signed-off-by: Fabio Estevam <festevam@denx.de>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agodt-bindings: gpio: pca95xx: add entry for pca6408
Justin Chen [Wed, 4 May 2022 22:29:17 +0000 (15:29 -0700)] 
dt-bindings: gpio: pca95xx: add entry for pca6408

The NXP PCA5608 is the 8-bit version of PCA5616.

Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
4 years agogpio: pca953xx: Add support for pca6408
Justin Chen [Wed, 4 May 2022 22:29:16 +0000 (15:29 -0700)] 
gpio: pca953xx: Add support for pca6408

Add support for pca6408 which is the 8-bit version of the pca6416.

https://www.nxp.com/docs/en/data-sheet/PCA6408A.pdf

Signed-off-by: Justin Chen <justinpopo6@gmail.com>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
4 years agosoc: imx: fix semicolon.cocci warnings
kernel test robot [Thu, 5 May 2022 11:29:01 +0000 (19:29 +0800)] 
soc: imx: fix semicolon.cocci warnings

drivers/soc/imx/imx8mp-blk-ctrl.c:227:61-62: Unneeded semicolon
drivers/soc/imx/imx8mp-blk-ctrl.c:192:61-62: Unneeded semicolon

 Remove unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

Fixes: 556f5cf9568a ("soc: imx: add i.MX8MP HSIO blk-ctrl")
CC: Lucas Stach <l.stach@pengutronix.de>
Reported-by: kernel test robot <lkp@intel.com>
Signed-off-by: kernel test robot <lkp@intel.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agogpio: visconti: Fix fwnode of GPIO IRQ
Nobuhiro Iwamatsu [Thu, 21 Apr 2022 09:42:28 +0000 (18:42 +0900)] 
gpio: visconti: Fix fwnode of GPIO IRQ

The fwnode of GPIO IRQ must be set to its own fwnode, not the fwnode of the
parent IRQ. Therefore, this sets own fwnode instead of the parent IRQ fwnode to
GPIO IRQ's.

Fixes: 2ad74f40dacc ("gpio: visconti: Add Toshiba Visconti GPIO support")
Signed-off-by: Nobuhiro Iwamatsu <nobuhiro1.iwamatsu@toshiba.co.jp>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
4 years agogpio: max732x: Drop unused support for irq and setup code via platform data
Uwe Kleine-König [Mon, 2 May 2022 17:08:27 +0000 (19:08 +0200)] 
gpio: max732x: Drop unused support for irq and setup code via platform data

The only user of max732x_platform_data is arch/arm/mach-pxa/littleton.c
and it only uses .gpio_base. So drop the other members from the data struct
and simplify the driver accordingly.

The motivating side effect of this change is that the .remove() callback
cannot return a nonzero error code any more which prepares making i2c
remove callbacks return void.

Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
4 years agoMerge back earlier int340x thermal driver changes for 5.19.
Rafael J. Wysocki [Thu, 5 May 2022 12:25:13 +0000 (14:25 +0200)] 
Merge back earlier int340x thermal driver changes for 5.19.

4 years agoASoC: cs43130: Re-use generic struct u16_fract
Andy Shevchenko [Mon, 2 May 2022 12:04:55 +0000 (15:04 +0300)] 
ASoC: cs43130: Re-use generic struct u16_fract

Instead of custom data type re-use generic struct u16_fract.
No changes intended.

Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Link: https://lore.kernel.org/r/20220502120455.84386-1-andriy.shevchenko@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
4 years agoASoC: fsl_micfil: fix the naming style for mask definition
Shengjiu Wang [Thu, 5 May 2022 07:34:07 +0000 (15:34 +0800)] 
ASoC: fsl_micfil: fix the naming style for mask definition

Remove the _SHIFT for the mask definition.

Fixes: 17f2142bae4b ("ASoC: fsl_micfil: use GENMASK to define register bit fields")
Signed-off-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Link: https://lore.kernel.org/r/1651736047-28809-1-git-send-email-shengjiu.wang@nxp.com
Signed-off-by: Mark Brown <broonie@kernel.org>
4 years agoASoC: ti: davinci-mcasp: Add dma-type for bcdma
Jayesh Choudhary [Thu, 5 May 2022 11:12:26 +0000 (16:42 +0530)] 
ASoC: ti: davinci-mcasp: Add dma-type for bcdma

Set DMA type for ti-bcdma controller for AM62-SK.

Acked-by: Peter Ujfalusi <peter.ujfalusi@gmail.com>
Signed-off-by: Jayesh Choudhary <j-choudhary@ti.com>
Signed-off-by: Jai Luthra <j-luthra@ti.com>
Link: https://lore.kernel.org/r/20220505111226.29217-1-j-luthra@ti.com
Signed-off-by: Mark Brown <broonie@kernel.org>
4 years agoASoC: SOF: ipc4: Add support for mandatory message handling functionality
Peter Ujfalusi [Thu, 5 May 2022 09:48:18 +0000 (12:48 +0300)] 
ASoC: SOF: ipc4: Add support for mandatory message handling functionality

Introduce the initial and mandatory IPC ops support for IPC4 to enable
IPC communication with this new IPC protocol.

This patch implements the following ops:
tx_msg, rx_msg, set_get_data and get_reply.

Co-developed-by: Rander Wang <rander.wang@intel.com>
Signed-off-by: Rander Wang <rander.wang@intel.com>
Co-developed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220505094818.10346-4-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
4 years agoASoC: SOF: Add initial header file for ipc4
Peter Ujfalusi [Thu, 5 May 2022 09:48:17 +0000 (12:48 +0300)] 
ASoC: SOF: Add initial header file for ipc4

The header file contains essential structure definitions, description of
bit fields and bits in the ipc4 header and an internally used ipc4 message
container definition.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220505094818.10346-3-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
4 years agoASoC: SOF: Add rx_data pointer to snd_sof_ipc_msg struct
Peter Ujfalusi [Thu, 5 May 2022 09:48:16 +0000 (12:48 +0300)] 
ASoC: SOF: Add rx_data pointer to snd_sof_ipc_msg struct

The rx_data pointer can be used by IPC implementations to pass the received
message (or part of the message, like the header) from platform code to
generic, high level IPC code.

IPC4 is going to be the first user of this as its implementation on Intel
platforms detaches the header and payload and the rx cannot be handled in
a similar way as it is implemented for ipc3.

If the rx_data is dynamically allocated, it is up to the platform code to
free it up.
After the message reception handling (rx_msg ops) returned, the pointer via
the msg->rx_data should be considered as invalid.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@linux.intel.com>
Reviewed-by: Bard Liao <yung-chuan.liao@linux.intel.com>
Reviewed-by: Rander Wang <rander.wang@intel.com>
Reviewed-by: Pierre-Louis Bossart <pierre-louis.bossart@linux.intel.com>
Reviewed-by: Ranjani Sridharan <ranjani.sridharan@linux.intel.com>
Link: https://lore.kernel.org/r/20220505094818.10346-2-peter.ujfalusi@linux.intel.com
Signed-off-by: Mark Brown <broonie@kernel.org>
4 years agoregmap: Add bulk read/write callbacks into regmap_config
Marek Vasut [Sat, 30 Apr 2022 02:51:44 +0000 (04:51 +0200)] 
regmap: Add bulk read/write callbacks into regmap_config

Currently the regmap_config structure only allows the user to implement
single element register read/write using .reg_read/.reg_write callbacks.
The regmap_bus already implements bulk counterparts of both, and is being
misused as a workaround for the missing bulk read/write callbacks in
regmap_config by a couple of drivers. To stop this misuse, add the bulk
read/write callbacks to regmap_config and call them from the regmap core
code.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Jagan Teki <jagan@amarulasolutions.com>
Cc: Mark Brown <broonie@kernel.org>
Cc: Maxime Ripard <maxime@cerno.tech>
Cc: Robert Foss <robert.foss@linaro.org>
Cc: Sam Ravnborg <sam@ravnborg.org>
Cc: Thomas Zimmermann <tzimmermann@suse.de>
To: dri-devel@lists.freedesktop.org
Link: https://lore.kernel.org/r/20220430025145.640305-1-marex@denx.de
Signed-off-by: Mark Brown <broonie@kernel.org>
4 years agoMerge back earlier cpufreq changes for 5.19.
Rafael J. Wysocki [Thu, 5 May 2022 12:22:23 +0000 (14:22 +0200)] 
Merge back earlier cpufreq changes for 5.19.

4 years agodevice property: Fix recent breakage of fwnode_get_next_parent_dev()
Douglas Anderson [Fri, 29 Apr 2022 23:43:47 +0000 (16:43 -0700)] 
device property: Fix recent breakage of fwnode_get_next_parent_dev()

Due to a subtle typo, instead of commit 87ffea09470d ("device
property: Introduce fwnode_for_each_parent_node()") being a no-op
change, it ended up causing the display on my sc7180-trogdor-lazor
device from coming up unless I added "fw_devlink=off" to my kernel
command line. Fix the typo.

Fixes: 87ffea09470d ("device property: Introduce fwnode_for_each_parent_node()")
Signed-off-by: Douglas Anderson <dianders@chromium.org>
Reviewed-by: Saravana Kannan <saravanak@google.com>
Reviewed-by: Sakari Ailus <sakari.ailus@linux.intel.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
4 years agopowerpc: fix typos in comments
Julia Lawall [Sat, 30 Apr 2022 18:56:54 +0000 (20:56 +0200)] 
powerpc: fix typos in comments

Various spelling mistakes in comments.
Detected with the help of Coccinelle.

Signed-off-by: Julia Lawall <Julia.Lawall@inria.fr>
Reviewed-by: Joel Stanley <joel@jms.id.au>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220430185654.5855-1-Julia.Lawall@inria.fr
4 years agopowerpc/boot: Stop using RELACOUNT
Alexey Kardashevskiy [Wed, 6 Apr 2022 07:00:38 +0000 (17:00 +1000)] 
powerpc/boot: Stop using RELACOUNT

So far the RELACOUNT tag from the ELF header was containing the exact
number of R_PPC_RELATIVE/R_PPC64_RELATIVE relocations. However the LLVM's
recent change [1] make it equal-or-less than the actual number which
makes it useless.

This replaces RELACOUNT in zImage loader with a pair of RELASZ and RELAENT.
The vmlinux relocation code is fixed in commit d79976918852
("powerpc/64: Add UADDR64 relocation support").

To make it more future proof, this walks through the entire .rela.dyn
section instead of assuming that the section is sorter by a relocation
type. Unlike d79976918852, this does not add unaligned UADDR/UADDR64
relocations as we are likely not to see those in practice - the zImage
is small and very arch specific so there is a smaller chance that some
generic feature (such as PRINK_INDEX) triggers unaligned relocations.

[1] https://github.com/llvm/llvm-project/commit/da0e5b885b25cf4

Signed-off-by: Alexey Kardashevskiy <aik@ozlabs.ru>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/20220406070038.3704604-1-aik@ozlabs.ru
4 years agopowerpc: Simplify and move arch_randomize_brk()
Christophe Leroy [Sat, 9 Apr 2022 17:17:37 +0000 (19:17 +0200)] 
powerpc: Simplify and move arch_randomize_brk()

arch_randomize_brk() is only needed for hash on book3s/64, for other
platforms the one provided by the default mmap layout is good enough.

Move it to hash_utils.c and use randomize_page() like the generic one.

And properly opt out the radix case instead of making an assumption
on mmu_highuser_ssize.

Also change to a 32M range like most other architectures instead of 8M.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/eafa4d18ec8ac7b98dd02b40181e61643707cc7c.1649523076.git.christophe.leroy@csgroup.eu
4 years agopowerpc/mm: Convert to default topdown mmap layout
Christophe Leroy [Sat, 9 Apr 2022 17:17:36 +0000 (19:17 +0200)] 
powerpc/mm: Convert to default topdown mmap layout

Select CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT and
remove arch/powerpc/mm/mmap.c

This change reuses the generic framework added by
commit 67f3977f805b ("arm64, mm: move generic mmap layout
functions to mm") without any functional change.

Comparison between powerpc implementation and the generic one:
- mmap_is_legacy() is identical.
- arch_mmap_rnd() does exactly the same allthough it's written
slightly differently.
- MIN_GAP and MAX_GAP are identical.
- mmap_base() does the same but uses STACK_RND_MASK which provides
the same values as stack_maxrandom_size().
- arch_pick_mmap_layout() is identical.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/518f9def87d3c889d5958103e7463cf45a2f673d.1649523076.git.christophe.leroy@csgroup.eu
4 years agopowerpc/mm: Enable full randomisation of memory mappings
Christophe Leroy [Sat, 9 Apr 2022 17:17:35 +0000 (19:17 +0200)] 
powerpc/mm: Enable full randomisation of memory mappings

Do like most other architectures and provide randomisation also to
"legacy" memory mappings, by adding the random factor to
mm->mmap_base in arch_pick_mmap_layout().

See commit 8b8addf891de ("x86/mm/32: Enable full randomization on
i386 and X86_32") for all explanations and benefits of that mmap
randomisation.

At the moment, slice_find_area_bottomup() doesn't use mm->mmap_base
but uses the fixed TASK_UNMAPPED_BASE instead.
slice_find_area_bottomup() being used as a fallback to
slice_find_area_topdown(), it can't use mm->mmap_base
directly.

Instead of always using TASK_UNMAPPED_BASE as base address, leave
it to the caller. When called from slice_find_area_topdown()
TASK_UNMAPPED_BASE is used. Otherwise mm->mmap_base is used.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/417fb10dde828534c73a03138b49621d74f4e5be.1649523076.git.christophe.leroy@csgroup.eu
4 years agopowerpc/mm: Move get_unmapped_area functions to slice.c
Christophe Leroy [Sat, 9 Apr 2022 17:17:34 +0000 (19:17 +0200)] 
powerpc/mm: Move get_unmapped_area functions to slice.c

hugetlb_get_unmapped_area() is now identical to the
generic version if only RADIX is enabled, so move it
to slice.c and let it fallback on the generic one
when HASH MMU is not compiled in.

Do the same with arch_get_unmapped_area() and
arch_get_unmapped_area_topdown().

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b5d9c124e82889e0cb115c150915a0c0d84eb960.1649523076.git.christophe.leroy@csgroup.eu
4 years agopowerpc/mm: Use generic_hugetlb_get_unmapped_area()
Christophe Leroy [Sat, 9 Apr 2022 17:17:33 +0000 (19:17 +0200)] 
powerpc/mm: Use generic_hugetlb_get_unmapped_area()

Use the generic version of arch_hugetlb_get_unmapped_area()
which is now available at all time.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/05f77014c619061638ecc52a0a4136eb04cc2799.1649523076.git.christophe.leroy@csgroup.eu
4 years agopowerpc/mm: Use generic_get_unmapped_area() and call it from arch_get_unmapped_area()
Christophe Leroy [Sat, 9 Apr 2022 17:17:32 +0000 (19:17 +0200)] 
powerpc/mm: Use generic_get_unmapped_area() and call it from arch_get_unmapped_area()

Use the generic version of arch_get_unmapped_area() which
is now available at all time instead of its copy
radix__arch_get_unmapped_area()

To allow that for PPC64, add arch_get_mmap_base() and
arch_get_mmap_end() macros.

Instead of setting mm->get_unmapped_area() to either
arch_get_unmapped_area() or generic_get_unmapped_area(),
always set it to arch_get_unmapped_area() and call
generic_get_unmapped_area() from there when radix is enabled.

Do the same with radix__arch_get_unmapped_area_topdown()

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/393be1fa386446443682fdb74544d733f68ef3bb.1649523076.git.christophe.leroy@csgroup.eu
4 years agopowerpc/mm: Remove CONFIG_PPC_MM_SLICES
Christophe Leroy [Sat, 9 Apr 2022 17:17:31 +0000 (19:17 +0200)] 
powerpc/mm: Remove CONFIG_PPC_MM_SLICES

CONFIG_PPC_MM_SLICES is always selected by hash book3s/64.
CONFIG_PPC_MM_SLICES is never selected by other platforms.

Remove it.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/dc2cdc204de8978574bf7c02329b6cfc4db0bce7.1649523076.git.christophe.leroy@csgroup.eu
4 years agopowerpc/mm: Make slice specific to book3s/64
Christophe Leroy [Sat, 9 Apr 2022 17:17:30 +0000 (19:17 +0200)] 
powerpc/mm: Make slice specific to book3s/64

Since commit 555904d07eef ("powerpc/8xx: MM_SLICE is not needed
anymore") only book3s/64 selects CONFIG_PPC_MM_SLICES.

Move slice.c into mm/book3s64/

Move necessary stuff in asm/book3s/64/slice.h and
remove asm/slice.h

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/4a0d74ef1966a5902b5fd4ac4b513a760a6d675a.1649523076.git.christophe.leroy@csgroup.eu
4 years agopowerpc/mm: Move vma_mmu_pagesize()
Christophe Leroy [Sat, 9 Apr 2022 17:17:29 +0000 (19:17 +0200)] 
powerpc/mm: Move vma_mmu_pagesize()

vma_mmu_pagesize() is only required for slices,
otherwise there is a generic weak version doing the
exact same thing.

Move it to slice.c

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/1302e000d529c93d07208f1fae90f938e7a551b4.1649523076.git.christophe.leroy@csgroup.eu
4 years agomm: Add len and flags parameters to arch_get_mmap_end()
Christophe Leroy [Sat, 9 Apr 2022 17:17:28 +0000 (19:17 +0200)] 
mm: Add len and flags parameters to arch_get_mmap_end()

Powerpc needs flags and len to make decision on arch_get_mmap_end().

So add them as parameters to arch_get_mmap_end().

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b556daabe7d2bdb2361c4d6130280da7c1ba2c14.1649523076.git.christophe.leroy@csgroup.eu
4 years agomm, hugetlbfs: Allow an arch to always use generic versions of get_unmapped_area...
Christophe Leroy [Sat, 9 Apr 2022 17:17:27 +0000 (19:17 +0200)] 
mm, hugetlbfs: Allow an arch to always use generic versions of get_unmapped_area functions

Unlike most architectures, powerpc can only define at runtime
if it is going to use the generic arch_get_unmapped_area() or not.

Today, powerpc has a copy of the generic arch_get_unmapped_area()
because when selection HAVE_ARCH_UNMAPPED_AREA the generic
arch_get_unmapped_area() is not available.

Rename it generic_get_unmapped_area() and make it independent of
HAVE_ARCH_UNMAPPED_AREA.

Do the same for arch_get_unmapped_area_topdown() versus
HAVE_ARCH_UNMAPPED_AREA_TOPDOWN.

Do the same for hugetlb_get_unmapped_area() versus
HAVE_ARCH_HUGETLB_UNMAPPED_AREA.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Reviewed-by: Nicholas Piggin <npiggin@gmail.com>
Acked-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/77f9d3e592f1c8511df9381aa1c4e754651da4d1.1649523076.git.christophe.leroy@csgroup.eu
4 years agomm: Allow arch specific arch_randomize_brk() with CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MM...
Christophe Leroy [Sat, 9 Apr 2022 17:17:26 +0000 (19:17 +0200)] 
mm: Allow arch specific arch_randomize_brk() with CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT

Commit e7142bf5d231 ("arm64, mm: make randomization selected by
generic topdown mmap layout") introduced a default version of
arch_randomize_brk() provided when
CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT is selected.

powerpc could select CONFIG_ARCH_WANT_DEFAULT_TOPDOWN_MMAP_LAYOUT
but needs to provide its own arch_randomize_brk().

In order to allow that, define generic version of arch_randomize_brk()
as a __weak symbol.

Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu>
Acked-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
Link: https://lore.kernel.org/r/b222f1ca06c850daf1b2f26afdb46c6dd97d21ba.1649523076.git.christophe.leroy@csgroup.eu
4 years agoMerge tag 'v5.18-rc4' into next
Michael Ellerman [Thu, 5 May 2022 12:09:35 +0000 (22:09 +1000)] 
Merge tag 'v5.18-rc4' into next

Merge master into next, to bring in commit 5f24d5a579d1 ("mm, hugetlb:
allow for "high" userspace addresses"), which is needed as a
prerequisite for the series converting powerpc to the generic mmap
logic.

4 years agoUSB: serial: ftdi_sio: clean up printk format specifier
Daniels Umanovskis [Tue, 26 Apr 2022 12:37:35 +0000 (12:37 +0000)] 
USB: serial: ftdi_sio: clean up printk format specifier

The latency is an unsigned int and should be printed as such (even if it
only holds values in the range 0..255).

Signed-off-by: Daniels Umanovskis <du@axentia.se>
Link: https://lore.kernel.org/r/20220426123714.2000-1-du@axentia.se
[ johan: amend commit message ]
Signed-off-by: Johan Hovold <johan@kernel.org>
4 years agoUSB: serial: option: add Fibocom MA510 modem
Sven Schwermer [Mon, 25 Apr 2022 14:34:50 +0000 (16:34 +0200)] 
USB: serial: option: add Fibocom MA510 modem

The MA510 modem has 3 USB configurations that are configurable via the AT
command AT+GTUSBMODE={30,31,32} which make the modem enumerate with the
following interfaces, respectively:

30: Diag + QDSS + Modem + RMNET
31: Diag + Modem + AT + ECM
32: Modem + AT + ECM

The first configuration (30) reuses u-blox R410M's VID/PID with
identical interface configuration.

A detailed description of the USB configuration for each mode follows:

+GTUSBMODE: 30
--------------
T:  Bus=03 Lev=01 Prnt=01 Port=06 Cnt=04 Dev#= 19 Spd=480  MxCh= 0
D:  Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs=  1
P:  Vendor=05c6 ProdID=90b2 Rev= 0.00
S:  Manufacturer=Fibocom MA510 Modem
S:  Product=Fibocom MA510 Modem
S:  SerialNumber=55e2695b
C:* #Ifs= 4 Cfg#= 1 Atr=e0 MxPwr=500mA
I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 1 Alt= 0 #EPs= 1 Cls=ff(vend.) Sub=ff Prot=ff Driver=(none)
E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option
E:  Ad=83(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 3 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=qmi_wwan
E:  Ad=85(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

+GTUSBMODE: 31
--------------
T:  Bus=03 Lev=01 Prnt=01 Port=06 Cnt=04 Dev#= 99 Spd=480  MxCh= 0
D:  Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=2cb7 ProdID=0106 Rev= 0.00
S:  Manufacturer=Fibocom MA510 Modem
S:  Product=Fibocom MA510 Modem
S:  SerialNumber=55e2695b
C:* #Ifs= 5 Cfg#= 1 Atr=e0 MxPwr=500mA
A:  FirstIf#= 3 IfCount= 2 Cls=02(comm.) Sub=00 Prot=00
I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=ff Prot=ff Driver=option
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option
E:  Ad=82(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
E:  Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=fe Prot=ff Driver=option
E:  Ad=84(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
E:  Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 3 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver=cdc_ether
E:  Ad=86(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
I:  If#= 4 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
I:* If#= 4 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
E:  Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

+GTUSBMODE: 32
--------------
T:  Bus=03 Lev=01 Prnt=01 Port=06 Cnt=04 Dev#=100 Spd=480  MxCh= 0
D:  Ver= 2.00 Cls=ef(misc ) Sub=02 Prot=01 MxPS=64 #Cfgs=  1
P:  Vendor=2cb7 ProdID=010a Rev= 0.00
S:  Manufacturer=Fibocom MA510 Modem
S:  Product=Fibocom MA510 Modem
S:  SerialNumber=55e2695b
C:* #Ifs= 4 Cfg#= 1 Atr=e0 MxPwr=500mA
A:  FirstIf#= 2 IfCount= 2 Cls=02(comm.) Sub=00 Prot=00
I:* If#= 0 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=ff Prot=ff Driver=option
E:  Ad=81(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 1 Alt= 0 #EPs= 3 Cls=ff(vend.) Sub=fe Prot=ff Driver=option
E:  Ad=83(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver=cdc_ether
E:  Ad=85(I) Atr=03(Int.) MxPS=  64 Ivl=2ms
I:  If#= 3 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
I:* If#= 3 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

Signed-off-by: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
4 years agoUSB: serial: option: add Fibocom L610 modem
Sven Schwermer [Mon, 25 Apr 2022 14:34:49 +0000 (16:34 +0200)] 
USB: serial: option: add Fibocom L610 modem

The L610 modem has 3 USB configurations that are configurable via the AT
command AT+GTUSBMODE={31,32,33} which make the modem enumerate with the
following interfaces, respectively:

31: Modem + NV + MOS + Diag + LOG + AT + AT
32: ECM + Modem + NV + MOS + Diag + LOG + AT + AT
33: RNDIS + Modem + NV + MOS + Diag + LOG + AT + AT

A detailed description of the USB configuration for each mode follows:

+GTUSBMODE: 31
--------------
T:  Bus=03 Lev=01 Prnt=01 Port=06 Cnt=04 Dev#=124 Spd=480  MxCh= 0
D:  Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs=  1
P:  Vendor=1782 ProdID=4d10 Rev= 0.00
S:  Manufacturer=FIBOCOM
S:  Product=L610
C:* #Ifs= 7 Cfg#= 1 Atr=e0 MxPwr=400mA
I:* If#= 0 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 1 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=07(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

+GTUSBMODE: 32
--------------
T:  Bus=03 Lev=01 Prnt=01 Port=06 Cnt=04 Dev#=122 Spd=480  MxCh= 0
D:  Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs=  1
P:  Vendor=1782 ProdID=4d11 Rev= 0.00
S:  Manufacturer=FIBOCOM
S:  Product=L610
C:* #Ifs= 9 Cfg#= 1 Atr=e0 MxPwr=400mA
A:  FirstIf#= 0 IfCount= 2 Cls=02(comm.) Sub=06 Prot=00
I:* If#= 0 Alt= 0 #EPs= 1 Cls=02(comm.) Sub=06 Prot=00 Driver=cdc_ether
E:  Ad=81(I) Atr=03(Int.) MxPS=  16 Ivl=32ms
I:  If#= 1 Alt= 0 #EPs= 0 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
I:* If#= 1 Alt= 1 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=cdc_ether
E:  Ad=82(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 7 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=07(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 8 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=89(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=08(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

+GTUSBMODE: 33
--------------
T:  Bus=03 Lev=01 Prnt=01 Port=06 Cnt=04 Dev#=126 Spd=480  MxCh= 0
D:  Ver= 2.00 Cls=00(>ifc ) Sub=00 Prot=00 MxPS=64 #Cfgs=  1
P:  Vendor=1782 ProdID=4d11 Rev= 0.00
S:  Manufacturer=FIBOCOM
S:  Product=L610
C:* #Ifs= 9 Cfg#= 1 Atr=e0 MxPwr=400mA
A:  FirstIf#= 0 IfCount= 2 Cls=e0(wlcon) Sub=01 Prot=03
I:* If#= 0 Alt= 0 #EPs= 1 Cls=e0(wlcon) Sub=01 Prot=03 Driver=rndis_host
E:  Ad=82(I) Atr=03(Int.) MxPS=   8 Ivl=4096ms
I:* If#= 1 Alt= 0 #EPs= 2 Cls=0a(data ) Sub=00 Prot=00 Driver=rndis_host
E:  Ad=81(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=01(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 2 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=83(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=02(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 3 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=84(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=03(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 4 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=85(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=04(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 5 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=86(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=05(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 6 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=87(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=06(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 7 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=88(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=07(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms
I:* If#= 8 Alt= 0 #EPs= 2 Cls=ff(vend.) Sub=00 Prot=00 Driver=option
E:  Ad=89(I) Atr=02(Bulk) MxPS= 512 Ivl=0ms
E:  Ad=08(O) Atr=02(Bulk) MxPS= 512 Ivl=0ms

Signed-off-by: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
4 years agoUSB: serial: pl2303: add device id for HP LM930 Display
Scott Chen [Mon, 25 Apr 2022 09:00:20 +0000 (17:00 +0800)] 
USB: serial: pl2303: add device id for HP LM930 Display

Add the device id for the HPLM930Display which is a PL2303GC based
device.

Signed-off-by: Scott Chen <scott@labau.com.tw>
Cc: stable@vger.kernel.org
Signed-off-by: Johan Hovold <johan@kernel.org>
4 years agoDocumentation: KVM: Fix title level for PSCI_SUSPEND
Stephen Rothwell [Thu, 5 May 2022 10:06:34 +0000 (20:06 +1000)] 
Documentation: KVM: Fix title level for PSCI_SUSPEND

The htmldoc build breaks in a funny way with:

<quote>
Sphinx parallel build error:
docutils.utils.SystemMessage: /home/sfr/next/next/Documentation/virt/kvm/api.rst:6175: (SEVERE/4) Title level inconsistent:

For arm/arm64:
^^^^^^^^^^^^^^
</quote>

Swap the ^^s for a bunch of --s...

Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
[maz: commit message]
Signed-off-by: Marc Zyngier <maz@kernel.org>
4 years agoARM: shmobile: rcar-gen2: Drop comma after OF match table sentinel
Geert Uytterhoeven [Thu, 3 Mar 2022 12:51:14 +0000 (13:51 +0100)] 
ARM: shmobile: rcar-gen2: Drop comma after OF match table sentinel

It does not make sense to have a comma after a sentinel, as any new
elements must be added before the sentinel.

Add a comment to clarify the purpose of the empty element.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/baaa4df6284401eb126573eb1c8ea5a88705cc37.1646311858.git.geert+renesas@glider.be
4 years agoARM: shmobile: Drop commas after dt_compat sentinels
Geert Uytterhoeven [Thu, 3 Mar 2022 12:50:54 +0000 (13:50 +0100)] 
ARM: shmobile: Drop commas after dt_compat sentinels

It does not make sense to have a comma after a sentinel, as any new
elements must be added before the sentinel.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ab4acc22eebb96a0747eb301c878b24b1200736a.1646311825.git.geert+renesas@glider.be
4 years agosoc: renesas: R-Car V3U is R-Car Gen4
Geert Uytterhoeven [Mon, 2 May 2022 13:35:24 +0000 (15:35 +0200)] 
soc: renesas: R-Car V3U is R-Car Gen4

Despite the name, R-Car V3U is the first member of the R-Car Gen4
family.  Hence reflect this in the SoC Family field.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Link: https://lore.kernel.org/r/2bbecad7b6c24c0d5c1797b3f7f0733d5ba33842.1651497066.git.geert+renesas@glider.be
4 years agodrm/qxl: add drm_gem_plane_helper_prepare_fb
Christian König [Fri, 29 Apr 2022 13:29:08 +0000 (15:29 +0200)] 
drm/qxl: add drm_gem_plane_helper_prepare_fb

We could need to wait for the pin to complete here.

Signed-off-by: Christian König <christian.koenig@amd.com>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Gerd Hoffmann <kraxel@redhat.com>
Cc: virtualization@lists.linux-foundation.org
Cc: spice-devel@lists.freedesktop.org
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20220429134230.24334-4-christian.koenig@amd.com
4 years agoclk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg
Phil Edworthy [Tue, 3 May 2022 11:55:54 +0000 (12:55 +0100)] 
clk: renesas: rzg2l: Add support for RZ/V2M reset monitor reg

The RZ/V2M doesn't have a matching set of reset monitor regs for each reset
reg like the RZ/G2L. Instead, it has a single CPG_RST_MON reg which has a
single bit per module.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-10-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: rzg2l: Make use of CLK_MON registers optional
Phil Edworthy [Tue, 3 May 2022 11:55:53 +0000 (12:55 +0100)] 
clk: renesas: rzg2l: Make use of CLK_MON registers optional

The RZ/V2M SoC doesn't use CLK_MON registers, so make them optional.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-9-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: rzg2l: Set HIWORD mask for all mux and dividers
Phil Edworthy [Tue, 3 May 2022 11:55:52 +0000 (12:55 +0100)] 
clk: renesas: rzg2l: Set HIWORD mask for all mux and dividers

All of the muxes and dividers that can be modified require the HIWORD
flags, so make the macros set them. It won't affect read only muxes and
dividers.
This will make the clock tables a little easier to read, particularly for
new SoCs coming.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-8-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: rzg2l: Add read only versions of the clk macros
Phil Edworthy [Tue, 3 May 2022 11:55:51 +0000 (12:55 +0100)] 
clk: renesas: rzg2l: Add read only versions of the clk macros

This just makes the clk tables easier to read.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-7-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro
Phil Edworthy [Tue, 3 May 2022 11:55:50 +0000 (12:55 +0100)] 
clk: renesas: rzg2l: Move the DEF_MUX array size calc into the macro

We only ever use ARRAY_SIZE() to populate the number of parents, so
move this into the macro to always detect it automatically. This
also makes the tables of clocks a little simpler.
Similarly for the DEF_SD_MUX macro.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-6-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agodt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC
Phil Edworthy [Tue, 3 May 2022 11:55:48 +0000 (12:55 +0100)] 
dt-bindings: clock: renesas,rzg2l: Document RZ/V2M SoC

Document the device tree binding for the Renesas RZ/V2M (r9a09g011) SoC.

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Link: https://lore.kernel.org/r/20220503115557.53370-4-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoMerge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19
Geert Uytterhoeven [Thu, 5 May 2022 10:10:49 +0000 (12:10 +0200)] 
Merge tag 'renesas-r9a09g011-dt-binding-defs-tag' into renesas-clk-for-v5.19

Renesas RZ/V2M DT Binding Definitions

Clock definitions for the Renesas RZ/V2M (R9A09G011) SoC, shared by
driver and DT source files.

4 years agoclk: renesas: r9a07g044: Fix OSTM1 module clock name
Geert Uytterhoeven [Mon, 2 May 2022 12:35:02 +0000 (14:35 +0200)] 
clk: renesas: r9a07g044: Fix OSTM1 module clock name

Fix a typo in the name of the "ostm1_pclk" clock.
This change has no run-time impact.

Fixes: 161450134ae9bab3 ("clk: renesas: r9a07g044: Add OSTM clock and reset entries")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e0eff1f57378ec29d0d3f1a7bdd7e380583f736b.1651494871.git.geert+renesas@glider.be
4 years agoclk: renesas: r9a07g043: Add clock and reset entries for ADC
Biju Das [Sun, 1 May 2022 08:34:50 +0000 (09:34 +0100)] 
clk: renesas: r9a07g043: Add clock and reset entries for ADC

Add clock and reset entries for ADC block in CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g043: Add TSU clock and reset entry
Biju Das [Sun, 1 May 2022 08:34:49 +0000 (09:34 +0100)] 
clk: renesas: r9a07g043: Add TSU clock and reset entry

Add TSU clock and reset entry to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g043: Add RSPI clock and reset entries
Biju Das [Sun, 1 May 2022 08:34:48 +0000 (09:34 +0100)] 
clk: renesas: r9a07g043: Add RSPI clock and reset entries

Add RSPI{0,1,2} clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller
Biju Das [Sun, 1 May 2022 08:34:47 +0000 (09:34 +0100)] 
clk: renesas: r9a07g043: Add clock and reset entries for SPI Multi I/O Bus Controller

Add clock and reset entries for SPI Multi I/O Bus Controller.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220501083450.26541-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g044: Add DSI clock and reset entries
Biju Das [Sat, 30 Apr 2022 11:41:56 +0000 (12:41 +0100)] 
clk: renesas: r9a07g044: Add DSI clock and reset entries

Add DSI clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-10-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g044: Add LCDC clock and reset entries
Biju Das [Sat, 30 Apr 2022 11:41:55 +0000 (12:41 +0100)] 
clk: renesas: r9a07g044: Add LCDC clock and reset entries

Add LCDC clock and reset entries to CPG driver.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-9-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g044: Add M4 Clock support
Biju Das [Sat, 30 Apr 2022 11:41:54 +0000 (12:41 +0100)] 
clk: renesas: r9a07g044: Add M4 Clock support

Add support for M4 clock which is sourced from pll2_533_div2.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-8-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g044: Add M3 Clock support
Biju Das [Sat, 30 Apr 2022 11:41:53 +0000 (12:41 +0100)] 
clk: renesas: r9a07g044: Add M3 Clock support

Add support for M3 clock which is sourced from DSI divider connected
to PLL5_4 mux.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-7-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
Biju Das [Sat, 30 Apr 2022 11:41:52 +0000 (12:41 +0100)] 
clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support

Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-6-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: r9a07g044: Add M1 clock support
Biju Das [Sat, 30 Apr 2022 11:41:51 +0000 (12:41 +0100)] 
clk: renesas: r9a07g044: Add M1 clock support

Add support for M1 clock which is sourced from FOUTPOSTDIV.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-5-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: rzg2l: Add DSI divider clk support
Biju Das [Sat, 30 Apr 2022 11:41:50 +0000 (12:41 +0100)] 
clk: renesas: rzg2l: Add DSI divider clk support

M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)

This patch add support for DSI divider clk by combining
DSIDIVA and DSIDIVB.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-4-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: rzg2l: Add PLL5_4 clk mux support
Biju Das [Sat, 30 Apr 2022 11:41:49 +0000 (12:41 +0100)] 
clk: renesas: rzg2l: Add PLL5_4 clk mux support

Add PLL5_4 clk mux support to select clock from clock
sources FOUTPOSTDIV and FOUT1PH0.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-3-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agoclk: renesas: rzg2l: Add FOUTPOSTDIV clk support
Biju Das [Sat, 30 Apr 2022 11:41:48 +0000 (12:41 +0100)] 
clk: renesas: rzg2l: Add FOUTPOSTDIV clk support

PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
from DSI divider which is connected to PLL5_4 MUX.

This patch adds support for generating FOUTPOSTDIV clk.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220430114156.6260-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agodt-bindings: clock: Add r9a09g011 CPG Clock Definitions
Phil Edworthy [Tue, 3 May 2022 11:55:47 +0000 (12:55 +0100)] 
dt-bindings: clock: Add r9a09g011 CPG Clock Definitions

Define RZ/V2M (R9A09G011) Clock Pulse Generator module clock outputs
(CPG_CLK_ON* registers), and reset definitions (CPG_RST_* registers)
in Section 48.5 ("Register Description") of the RZ/V2M Hardware User's
Manual (Rev. 1.10, Sep. 2021).

Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Link: https://lore.kernel.org/r/20220503115557.53370-3-phil.edworthy@renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agopinctrl: renesas: checker: Add reserved field checks
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:12 +0000 (19:24 +0200)] 
pinctrl: renesas: checker: Add reserved field checks

Add checks for discovering registers with reserved fields that could
benefit from being described using variable-width reserved field
shorthands, reducing kernel size.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f5a5159ba7b396e6f09dd3f23c864a74ed8e342d.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7786: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:11 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7786: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 79 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/22487451ff7d8cce0182354c9553f3b171cc34d9.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7785: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:10 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7785: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 150 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/07a238f13f80674d86719a5e869c65a2e0b8c1c1.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7757: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:09 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7757: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 115 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/05c69ca8710134bb96ec8f7d18bafe42418f3510.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7734: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:08 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7734: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 161 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/18e476c0a9f0af5b5d511d1c4922c6e299d1847a.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7724: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:07 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7724: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 8 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/696dcad42a8b8395276301eb5dd5c5a895826f35.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7723: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:06 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7723: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 105 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/5d7ef2fa02c2137d2d243fc183d18220c9aaf7b8.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7722: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:05 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7722: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 396 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c3965b6f9ea603b185924136f859c6eca7d5d6f4.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7720: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:04 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7720: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 128 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/4b290f93a7edb1f91c97da90e67b7f6f3df62951.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh73a0: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:03 +0000 (19:24 +0200)] 
pinctrl: renesas: sh73a0: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 154 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e74738b403cc15b3407e7568d323fdae8e7b30dd.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7269: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:02 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7269: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 406 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/feb1e865c2b6abbc0db24243143ea09ad143f6df.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7264: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:01 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7264: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 572 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/434c274f626b2eab3539fe2ab80c6eda164e07fa.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7203: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:24:00 +0000 (19:24 +0200)] 
pinctrl: renesas: sh7203: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 281 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c625b4eee298b88c2ee47ed80b0dea5d02ed56d1.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a779f0: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:59 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a779f0: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 183 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/e50f9c8ef1261b7ceb6b1be637d4019fe7312250.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a779a0: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:58 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a779a0: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 556 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7db3751ecf96fcc469bd14eeb02d69e565956151.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77995: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:57 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77995: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 422 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d74af80fdb7b6d78b10634238a88e55a139e5c22.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77990: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:56 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77990: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 226 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/924ba4505e33180e078ca72a1db8db13c193cbea.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77980: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:55 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77980: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 198 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0bf6b069a794b3c56c0c9311ac4b2ada577a9cb7.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77970: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:54 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77970: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 268 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/33dd9bc41df888f132e2e6921d2ff38225b68105.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7796: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:53 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7796: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/81f3586749bb1117c5636e9a9663d25e77cbe158.1649865241.git.geert+renesas@glider.be