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4 years agopinctrl: renesas: r8a77965: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:52 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77965: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2aff2f4c1ed6d834370ce6dd9379c8c93bfc0a92.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77951: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:51 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77951: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 496 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cd59cc2e0f55f0dcede1356f73a9e69fe09bf5eb.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77950: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:50 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77950: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 473 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a1617d24af2b9b3224ce84c0ada535565009fdda.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7792: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:49 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7792: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 257 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/0f211d493a0cfbcd96d84a709d21bea51c7385ae.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7779: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:48 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7779: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 81 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/ecc7377d2992694226dcf055bed0b617701a3d71.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77470: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:47 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77470: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 70 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c5183fcb3dd417d57ced0f60d091e2c7d37e1c8c.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7740: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:46 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7740: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 230 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/a18fb98a4eefe648a1b1c5b5913dbeee092674c4.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a73a4: Optimize fixed-width reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:45 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a73a4: Optimize fixed-width reserved fields

Describe registers with fixed-width register fields and many reserved
fields using the PINMUX_CFG_REG_VAR() macro, as the latter supports a
shorthand not requiring dummy values.

This reduces kernel size by 126 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f835c2ff5bb07e541f6377b16f0a32c5aad2a47f.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: sh7734: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:44 +0000 (19:23 +0200)] 
pinctrl: renesas: sh7734: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 174 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/3ab96d28494b8c5a2d427ba25f31a04ca0cc7305.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a779f0: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:43 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a779f0: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 164 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c98e577996a71ae96145ee6da94aa18fd9ea85b9.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a779a0: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:42 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a779a0: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 140 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/807b2a7e02be2fac50c280961a4841813ab13cd8.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77995: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:41 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77995: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 246 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/7098704f89bb702c28036c567d3222521ff60f86.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77990: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:40 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77990: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 40 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c032fce3fff6a6a63dc90f9ab8dfe1f4f3cf6ad6.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77980: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:39 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77980: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 168 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/c81b26815dff2e191b8c415624a20aa3b4725d23.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77970: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:38 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77970: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 164 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f2dda82454bb1b0c97f842de2c9fa68da05ef3e6.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77965: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:37 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77965: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 148 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1cf52b1f93e8af593a60f65d8a848d1ebb24cac6.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7796: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:36 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7796: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 148 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/433f5ddcc2dba7352825cba007b99b8e654d4c61.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77951: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:35 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77951: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 152 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/35d0ff4881335889002718540101bcdb8e7f5b5a.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77950: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:34 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77950: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 232 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1866c399e94408439a469c12dc53557b55a00f3a.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7794: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:33 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7794: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 201 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/2fa43bd38c5cf260e89ae1da38d1a217ab762589.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7792: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:32 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7792: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 784 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/d39a52cf972a450ef5a0989ba7e448115a8147ba.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7791: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:31 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7791: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 349 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/972808be595fd742afc6b7fc89751ca4788d6f62.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7790: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:30 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7790: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 445 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/842d8060422a9b67dfac4af6d9325d0d99cf50dc.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7779: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:29 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7779: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 197 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/4b468118e0da681c860ed750976a990a0930dcba.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a7778: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:28 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a7778: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 142 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1af5225c81ac871a461f7d824619275e2e0ed8df.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77470: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:27 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77470: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 114 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/bc8f9647bbf677ac67cbdb34cf0c8fbaf62fb7fc.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: emev2: Use shorthands for reserved fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:26 +0000 (19:23 +0200)] 
pinctrl: renesas: emev2: Use shorthands for reserved fields

Replace the full descriptions of reserved register fields by shorthands
with a negative field width, and merge adjacent reserved fields.

This reduces kernel size by 769 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/616afe67d3b4d2cbf5f43876f9aa7b258862ceaa.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: rmobile: Mark unused PORTCR bits reserved
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:25 +0000 (19:23 +0200)] 
pinctrl: renesas: rmobile: Mark unused PORTCR bits reserved

The PULMD bits and the SEC bit in the PORTCR register descriptions on
SH/R-Mobile SoCs are either unused or unsupported.  Describe them as
reserved bits using a negative field width value, and drop the
corresponding dummy enum IDs.

This reduces kernel size by 2832 (R-Mobile APE6), 2544 (R-Mobile A1),
and/or 3228 (SH-Mobile AG5) bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/1b123d8f04c2314d5a7a87004971868ba2176499.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: Add shorthand for reserved register fields
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:24 +0000 (19:23 +0200)] 
pinctrl: renesas: Add shorthand for reserved register fields

Currently, reserved register fields must be fully described using dummy
enum IDs (zeroes), one for each possible state (2^bits states).

Add support for describing reserved fields using negative field width
values as shorthands, thus removing the need for dummy values.  Apart
from the obvious size reduction due to the removal of the dummy values,
this will also enable merging adjacent reserved fields into a single
field, reducing the number of fields to describe, and thus kernel size.

Update the checker accordingly.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/cad7c92ef039d9a4d039807efc15886a7aa862be.1649865241.git.geert+renesas@glider.be
4 years agopinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs
Geert Uytterhoeven [Wed, 13 Apr 2022 17:23:23 +0000 (19:23 +0200)] 
pinctrl: renesas: r8a77470: Use fixed-width description for IPSR regs

All fields in the IPSR registers on RZ/G1C have the same width, but the
driver describes them using the PINMUX_CFG_REG_VAR() macro, which
is intended for fields with different widths.  Convert the description
to use the PINMUX_CFG_REG() macro for fixed-width fields instead.

This reduces kernel size by 162 bytes.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/f6f26a0dfd16050ead83daf2b9fabeb8b26821a6.1649865241.git.geert+renesas@glider.be
4 years agodt-bindings: soc: renesas: Move renesas,rzg2l-sysc from arm to soc
Geert Uytterhoeven [Mon, 2 May 2022 12:40:58 +0000 (14:40 +0200)] 
dt-bindings: soc: renesas: Move renesas,rzg2l-sysc from arm to soc

The Renesas RZ/{G2L,V2L} System Controller (SYSC) DT binding is not
really a power-related DT binding, hence it does not belong under
Documentation/devicetree/bindings/power/.
Move it to Documentation/devicetree/bindings/soc/renesas/.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/a47015888f99476a5206a556dce93503494d9a73.1651495078.git.geert+renesas@glider.be
4 years agodt-bindings: memory: renesas,rpc-if: Document RZ/G2UL SoC
Biju Das [Sun, 1 May 2022 08:25:08 +0000 (09:25 +0100)] 
dt-bindings: memory: renesas,rpc-if: Document RZ/G2UL SoC

Document RZ/G2UL RPC-IF bindings. RZ/G2UL RPC-IF is identical to one found
on the RZ/G2L SoC. No driver changes are required as generic compatible
string "renesas,rzg2l-rpc-if" will be used as a fallback.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220501082508.25511-1-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
4 years agogenirq: Synchronize interrupt thread startup
Thomas Pfaff [Mon, 2 May 2022 11:28:29 +0000 (13:28 +0200)] 
genirq: Synchronize interrupt thread startup

A kernel hang can be observed when running setserial in a loop on a kernel
with force threaded interrupts. The sequence of events is:

   setserial
     open("/dev/ttyXXX")
       request_irq()
     do_stuff()
      -> serial interrupt
         -> wake(irq_thread)
      desc->threads_active++;
     close()
       free_irq()
         kthread_stop(irq_thread)
     synchronize_irq() <- hangs because desc->threads_active != 0

The thread is created in request_irq() and woken up, but does not get on a
CPU to reach the actual thread function, which would handle the pending
wake-up. kthread_stop() sets the should stop condition which makes the
thread immediately exit, which in turn leaves the stale threads_active
count around.

This problem was introduced with commit 519cc8652b3a, which addressed a
interrupt sharing issue in the PCIe code.

Before that commit free_irq() invoked synchronize_irq(), which waits for
the hard interrupt handler and also for associated threads to complete.

To address the PCIe issue synchronize_irq() was replaced with
__synchronize_hardirq(), which only waits for the hard interrupt handler to
complete, but not for threaded handlers.

This was done under the assumption, that the interrupt thread already
reached the thread function and waits for a wake-up, which is guaranteed to
be handled before acting on the stop condition. The problematic case, that
the thread would not reach the thread function, was obviously overlooked.

Make sure that the interrupt thread is really started and reaches
thread_fn() before returning from __setup_irq().

This utilizes the existing wait queue in the interrupt descriptor. The
wait queue is unused for non-shared interrupts. For shared interrupts the
usage might cause a spurious wake-up of a waiter in synchronize_irq() or the
completion of a threaded handler might cause a spurious wake-up of the
waiter for the ready flag. Both are harmless and have no functional impact.

[ tglx: Amended changelog ]

Fixes: 519cc8652b3a ("genirq: Synchronize only with single thread on free_irq()")
Signed-off-by: Thomas Pfaff <tpfaff@pcs.com>
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Marc Zyngier <maz@kernel.org>
Cc: stable@vger.kernel.org
Link: https://lore.kernel.org/r/552fe7b4-9224-b183-bb87-a8f36d335690@pcs.com
4 years agoMAINTAINERS: update the GPIO git tree entry
Bartosz Golaszewski [Mon, 2 May 2022 09:34:16 +0000 (11:34 +0200)] 
MAINTAINERS: update the GPIO git tree entry

My git tree has become the de facto main GPIO tree. Update the
MAINTAINERS file to reflect that.

Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
Reported-by: Baruch Siach <baruch@tkos.co.il>
Reviewed-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
4 years agoNFC: netlink: fix sleep in atomic bug when firmware download timeout
Duoming Zhou [Wed, 4 May 2022 05:58:47 +0000 (13:58 +0800)] 
NFC: netlink: fix sleep in atomic bug when firmware download timeout

There are sleep in atomic bug that could cause kernel panic during
firmware download process. The root cause is that nlmsg_new with
GFP_KERNEL parameter is called in fw_dnld_timeout which is a timer
handler. The call trace is shown below:

BUG: sleeping function called from invalid context at include/linux/sched/mm.h:265
Call Trace:
kmem_cache_alloc_node
__alloc_skb
nfc_genl_fw_download_done
call_timer_fn
__run_timers.part.0
run_timer_softirq
__do_softirq
...

The nlmsg_new with GFP_KERNEL parameter may sleep during memory
allocation process, and the timer handler is run as the result of
a "software interrupt" that should not call any other function
that could sleep.

This patch changes allocation mode of netlink message from GFP_KERNEL
to GFP_ATOMIC in order to prevent sleep in atomic bug. The GFP_ATOMIC
flag makes memory allocation operation could be used in atomic context.

Fixes: 9674da8759df ("NFC: Add firmware upload netlink command")
Fixes: 9ea7187c53f6 ("NFC: netlink: Rename CMD_FW_UPLOAD to CMD_FW_DOWNLOAD")
Signed-off-by: Duoming Zhou <duoming@zju.edu.cn>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504055847.38026-1-duoming@zju.edu.cn
Signed-off-by: Paolo Abeni <pabeni@redhat.com>
4 years agodrm/todo: Add entry for using kunit in the subsystem
Javier Martinez Canillas [Wed, 4 May 2022 08:02:12 +0000 (10:02 +0200)] 
drm/todo: Add entry for using kunit in the subsystem

The Kernel Unit Testing (KUnit) framework provides a common framework for
unit tests within the Linux kernel. Having a test suite would allow to
identify regressions earlier.

Signed-off-by: Javier Martinez Canillas <javierm@redhat.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Maxime Ripard <maxime@cerno.tech>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220504080212.713275-1-javierm@redhat.com
4 years agoleds: Add PWM multicolor driver
Sven Schwermer [Thu, 7 Apr 2022 07:32:25 +0000 (09:32 +0200)] 
leds: Add PWM multicolor driver

By allowing to group multiple monochrome PWM LEDs into multicolor LEDs,
all involved LEDs can be controlled in-sync. This enables using effects
using triggers, etc.

Signed-off-by: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
4 years agodt-bindings: leds: Add multicolor PWM LED bindings
Sven Schwermer [Thu, 7 Apr 2022 07:32:24 +0000 (09:32 +0200)] 
dt-bindings: leds: Add multicolor PWM LED bindings

This allows to group multiple PWM-connected monochrome LEDs into
multicolor LEDs, e.g. RGB LEDs.

Signed-off-by: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
4 years agodt-bindings: leds: Optional multi-led unit address
Sven Schwermer [Thu, 7 Apr 2022 07:32:23 +0000 (09:32 +0200)] 
dt-bindings: leds: Optional multi-led unit address

The unit address does not make sense in all cases the multi-led node is
used, e.g. for the upcoming PWM multi-color LED driver.

Signed-off-by: Sven Schwermer <sven.schwermer@disruptive-technologies.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
4 years agoleds: regulator: Make probeable from device tree
Linus Walleij [Mon, 4 Apr 2022 20:35:22 +0000 (22:35 +0200)] 
leds: regulator: Make probeable from device tree

The regulator LED can easily be adapted to probe from the
device tree.

We switch led_classdev_register() to led_classdev_register_ext()
passing some struct led_init_data init_data that we leave NULL
save the fwnode if platform data isn't present so that it will be
populated from the device tree.

If we have platform data we set up the name from the platform
data but using init_data instead.

Cc: Antonio Ospite <ao2@ao2.it>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
4 years agoleds: regulator: Add dev helper variable
Linus Walleij [Mon, 4 Apr 2022 20:35:21 +0000 (22:35 +0200)] 
leds: regulator: Add dev helper variable

Instead of repeating the hard to read &pdev->dev just create a
local struct device *dev in probe().

Cc: Antonio Ospite <ao2@ao2.it>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
4 years agodt-bindings: leds: Add regulator-led binding
Linus Walleij [Mon, 4 Apr 2022 20:35:20 +0000 (22:35 +0200)] 
dt-bindings: leds: Add regulator-led binding

The regulator is a LED connected directly to a regulator and with
its brightness controlled by the voltage of the regulator.

Cc: devicetree@vger.kernel.org
Cc: Antonio Ospite <ao2@ao2.it>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Pavel Machek <pavel@ucw.cz>
4 years agoarm64: mm: Cleanup useless parameters in zone_sizes_init()
Kefeng Wang [Mon, 11 Apr 2022 09:24:55 +0000 (17:24 +0800)] 
arm64: mm: Cleanup useless parameters in zone_sizes_init()

Directly use max_pfn for max and no one use min, kill them.

Reviewed-by: Vijay Balakrishna <vijayb@linux.microsoft.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Link: https://lore.kernel.org/r/20220411092455.1461-4-wangkefeng.wang@huawei.com
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
4 years agoarm64: dt: imx8mp: support pwm polarity inversion
Markus Niebel [Mon, 2 May 2022 09:49:01 +0000 (11:49 +0200)] 
arm64: dt: imx8mp: support pwm polarity inversion

The i.MX8M Plus has the same PWM IP as i.MX6 / i.MX7. This IP
and the driver supporting pwm polarity inversion. Switch CPU
device tree fragment to use 3 pwm-cells.

Tested on MBa8MPxL mainboard.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dt: imx8mn: support pwm polarity inversion
Markus Niebel [Mon, 2 May 2022 09:49:00 +0000 (11:49 +0200)] 
arm64: dt: imx8mn: support pwm polarity inversion

The i.MX8M Nano has the same PWM IP as i.MX6 / i.MX7. This IP
and the driver supporting pwm polarity inversion. Switch CPU
device tree fragment to use 3 pwm-cells.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dt: imx8mm: support pwm polarity inversion
Markus Niebel [Mon, 2 May 2022 09:48:59 +0000 (11:48 +0200)] 
arm64: dt: imx8mm: support pwm polarity inversion

The i.MX8M Mini has the same PWM IP as i.MX6 / i.MX7. This IP
and the driver supporting pwm polarity inversion. Switch CPU
device tree fragment to use 3 pwm-cells and correct board
device trees.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dt: imx8mq: support pwm polarity inversion
Markus Niebel [Mon, 2 May 2022 09:48:58 +0000 (11:48 +0200)] 
arm64: dt: imx8mq: support pwm polarity inversion

The i.MX8MQ has the same PWM IP as i.MX6 / i.MX7. This IP and the driver
supporting pwm polarity inversion. Switch CPU device tree fragment to
use 3 pwm-cells and correct board device trees.

Signed-off-by: Markus Niebel <Markus.Niebel@ew.tq-group.com>
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dts: imx8mm-venice-gw7901: remove unnecessary cpu temp override
Tim Harvey [Fri, 29 Apr 2022 16:20:30 +0000 (09:20 -0700)] 
arm64: dts: imx8mm-venice-gw7901: remove unnecessary cpu temp override

Remove the unnecessary cpu_alert0 and cpu_crit0 TMU node overrides as
these are added dynamically by boot firmware based on CPU temperature
grade.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dts: imx8mm-venice-gw7902: add vdd_5p0 ADC channel
Tim Harvey [Fri, 29 Apr 2022 16:19:44 +0000 (09:19 -0700)] 
arm64: dts: imx8mm-venice-gw7902: add vdd_5p0 ADC channel

Add missing vdd_5p0 ADC channel for the GW7902 boards.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dts: imx8m*venice: add missing clock-names to pcie_phy
Tim Harvey [Fri, 29 Apr 2022 16:16:29 +0000 (09:16 -0700)] 
arm64: dts: imx8m*venice: add missing clock-names to pcie_phy

Define the missing clock-names property for the pcie_phy required by
the fsl,imx8-pcie-phy dt bindings.

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agodrm: simplify the return expression of ast_drm_resume()
Minghao Chi [Thu, 5 May 2022 02:22:08 +0000 (02:22 +0000)] 
drm: simplify the return expression of ast_drm_resume()

Simplify the return expression.

Reported-by: Zeal Robot <zealci@zte.com.cn>
Signed-off-by: Minghao Chi <chi.minghao@zte.com.cn>
Acked-by: Thomas Zimmermann <tzimmermann@suse.de>
Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Link: https://patchwork.freedesktop.org/patch/msgid/20220505022208.57157-1-chi.minghao@zte.com.cn
4 years agodrm/mgag200: Protect concurrent access to I/O registers with lock
Thomas Zimmermann [Mon, 2 May 2022 14:25:14 +0000 (16:25 +0200)] 
drm/mgag200: Protect concurrent access to I/O registers with lock

Add a mutex lock to protect concurrent access to I/O registers
against each other. This happens between invocation of commit-
tail functions and get-mode operations. Both with use the CRTC
index registers MGA1064_GEN_IO_DATA and MGA1064_GEN_IO_CTL.
Concurrent access can lead to failed mode-setting operations.

v2:
* fix typo in commit description (Jocelyn)
* add comment to explain rmmio_lock

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20220502142514.2174-4-tzimmermann@suse.de
4 years agodrm/ast: Protect concurrent access to I/O registers with lock
Thomas Zimmermann [Mon, 2 May 2022 14:25:13 +0000 (16:25 +0200)] 
drm/ast: Protect concurrent access to I/O registers with lock

Add a mutex lock to protect concurrent access to I/O registers
against each other. This happens between invocation of commit-
tail functions and get-mode operations. Both with use the CRTC
index register AST_IO_CRTC_PORT. Concurrent access can lead to
failed mode-setting operations.

v2:
* fix typo in commit description (Jocelyn)

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Reported-by: KuoHsiang Chou <kuohsiang_chou@aspeedtech.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220502142514.2174-3-tzimmermann@suse.de
4 years agoarm64: dts: exynos: switch UFS clock node in ExynosAutov9
Chanho Park [Wed, 4 May 2022 07:51:54 +0000 (16:51 +0900)] 
arm64: dts: exynos: switch UFS clock node in ExynosAutov9

Use cmu_fsys's clock node instead of dummy UFS clock node.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-13-chanho61.park@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
4 years agoarm64: dts: exynos: switch USI clocks in ExynosAutov9
Chanho Park [Wed, 4 May 2022 07:51:53 +0000 (16:51 +0900)] 
arm64: dts: exynos: switch USI clocks in ExynosAutov9

Use CMU clock nodes instead of dummy fixed-rate-clock.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-12-chanho61.park@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
4 years agoarm64: dts: exynos: add initial CMU clock nodes in ExynosAutov9
Chanho Park [Wed, 4 May 2022 07:51:52 +0000 (16:51 +0900)] 
arm64: dts: exynos: add initial CMU clock nodes in ExynosAutov9

Add cmu_top, cmu_busmc, cmu_core, cmu_fsys and peric0/c1/s clock nodes.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-11-chanho61.park@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
4 years agodrm: Add DRM-managed mutex_init()
Thomas Zimmermann [Mon, 2 May 2022 14:25:12 +0000 (16:25 +0200)] 
drm: Add DRM-managed mutex_init()

Add drmm_mutex_init(), a helper that provides managed mutex cleanup. The
mutex will be destroyed with the final reference of the DRM device.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Jocelyn Falempe <jfalempe@redhat.com>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20220502142514.2174-2-tzimmermann@suse.de
4 years agoMerge tag 'samsung-dt-bindings-clk-exynosautov9-5.19' into next/dt64
Krzysztof Kozlowski [Thu, 5 May 2022 07:03:42 +0000 (09:03 +0200)] 
Merge tag 'samsung-dt-bindings-clk-exynosautov9-5.19' into next/dt64

dt-bindings for Samsung ExynosAutov9 clock controllers for v5.19

The Devicetree bindings for Samsung ExynosAutov9 clock controllers.

4 years agoarm64: dts: imx8mm-venice-gw7902: fix pcie bindings
Tim Harvey [Fri, 29 Apr 2022 16:13:47 +0000 (09:13 -0700)] 
arm64: dts: imx8mm-venice-gw7902: fix pcie bindings

Update the pcie bindings to the correct dt bindings:
 pcie_phy:
  - use pcie0_refclk
  - add required clock-names
 pcie:
  - remove pcie_phy clock as it comes from phy driver

Signed-off-by: Tim Harvey <tharvey@gateworks.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agodt-bindings: clock: add Exynos Auto v9 SoC CMU bindings
Chanho Park [Wed, 4 May 2022 07:51:44 +0000 (16:51 +0900)] 
dt-bindings: clock: add Exynos Auto v9 SoC CMU bindings

Add dt-schema for Exynos Auto v9 SoC clock controller.

Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Link: https://lore.kernel.org/r/20220504075154.58819-3-chanho61.park@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
4 years agodt-bindings: clock: add clock binding definitions for Exynos Auto v9
Chanho Park [Wed, 4 May 2022 07:51:43 +0000 (16:51 +0900)] 
dt-bindings: clock: add clock binding definitions for Exynos Auto v9

Add device tree clock binding definitions for below CMU blocks.

- CMU_TOP
- CMU_BUSMC
- CMU_CORE
- CMU_FYS2
- CMU_PERIC0 / C1
- CMU_PERIS

Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Chanho Park <chanho61.park@samsung.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
Link: https://lore.kernel.org/r/20220504075154.58819-2-chanho61.park@samsung.com
Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
4 years agodrm/format-helper: Share implementation among conversion helpers
Thomas Zimmermann [Wed, 27 Apr 2022 14:14:09 +0000 (16:14 +0200)] 
drm/format-helper: Share implementation among conversion helpers

Provide format-independent conversion helpers for system and I/O
memory. Implement most existing helpers on top of it. The source and
destination formats of each conversion is handled by a per-line
helper that is given to the generic implementation.

v2:
* remove a blank line

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220427141409.22842-5-tzimmermann@suse.de
4 years agodrm/format-helper: Unify the parameters of all per-line conversion helpers
Thomas Zimmermann [Wed, 27 Apr 2022 14:14:08 +0000 (16:14 +0200)] 
drm/format-helper: Unify the parameters of all per-line conversion helpers

Give each per-line conversion helper pointers of type void and the
number of pixels in the line. Remove the unused swab parameters.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220427141409.22842-4-tzimmermann@suse.de
4 years agodrm/format-helper: Remove optional byte-swap from line convertion
Thomas Zimmermann [Wed, 27 Apr 2022 14:14:07 +0000 (16:14 +0200)] 
drm/format-helper: Remove optional byte-swap from line convertion

Implement per-pixel byte swapping in a separate conversion helper
for the single function that requires it. Select the correct helper
for each conversion.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220427141409.22842-3-tzimmermann@suse.de
4 years agodrm/format-helper: Implement drm_fb_swab() with per-line helpers
Thomas Zimmermann [Wed, 27 Apr 2022 14:14:06 +0000 (16:14 +0200)] 
drm/format-helper: Implement drm_fb_swab() with per-line helpers

Replace the inner loop of drm_fb_swab() with helper functions that
swap the bytes in each pixel. This will allow to share the outer
loop with other conversion helpers.

Signed-off-by: Thomas Zimmermann <tzimmermann@suse.de>
Reviewed-by: Javier Martinez Canillas <javierm@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20220427141409.22842-2-tzimmermann@suse.de
4 years agothunderbolt: Add support for XDomain lane bonding
Mika Westerberg [Sun, 13 Feb 2022 14:44:45 +0000 (16:44 +0200)] 
thunderbolt: Add support for XDomain lane bonding

The USB4 Inter-Domain Service specification defines a protocol that can
be used to establish lane bonding between two USB4 domains (hosts). So
far we have not implemented it because the host controller DMA was not
fast enough to be able to go over 20 Gbits/s even if lanes were bonded.
However, starting from Intel Alder Lake CPUs the DMA can go over
20 Gbits/s so now it makes more sense to add this support to the driver.

Because both ends need to negotiate the bonding we add a simple state
machine that tracks the connection state and does the necessary steps
described by the USB4 Inter-Domain Service specification. We only
establish lane bonding when both sides of the link support it. Otherwise
we default to use the single lane. Also this is only done when software
connection manager is used. On systems with firmware based connection
manager, it handles the high-speed tunneling so bonding lanes is
specific to the implementation (Intel firmware based connection manager
does not support lane bonding).

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
4 years agothunderbolt: Ignore port locked error in tb_port_wait_for_link_width()
Mika Westerberg [Sun, 13 Feb 2022 15:16:24 +0000 (17:16 +0200)] 
thunderbolt: Ignore port locked error in tb_port_wait_for_link_width()

Sometimes when polling for the port after target link width is changed
we get back port locked notification (because the link actually was
reset and then re-trained). Instead of bailing out we can ignore these
when polling for the width change as this is expected.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
4 years agothunderbolt: Split setting link width and lane bonding into own functions
Mika Westerberg [Sun, 13 Feb 2022 09:54:15 +0000 (11:54 +0200)] 
thunderbolt: Split setting link width and lane bonding into own functions

When bonding lanes over XDomain the host that has "higher" UUID triggers
link re-train for bonding, and the host that has "lower" UUID just waits
for this to happen. To support this split setting the link width and
triggering the actual bonding a separate functions that can be called as
needed.

While there remove duplicated empty line in the kernel-doc comment of
tb_port_lane_bonding_disable().

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
4 years agothunderbolt: Move tb_port_state() prototype to correct place
Mika Westerberg [Sun, 13 Feb 2022 09:45:39 +0000 (11:45 +0200)] 
thunderbolt: Move tb_port_state() prototype to correct place

This should be before tb_wait_for_port() following how the functions in
switch.c are organized.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
4 years agothunderbolt: Add debug logging when lane is enabled/disabled
Mika Westerberg [Sun, 13 Feb 2022 09:42:23 +0000 (11:42 +0200)] 
thunderbolt: Add debug logging when lane is enabled/disabled

This is useful when debugging possible issues.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
4 years agoARM: dts: imx6qdl-udoo: Disable USB host to work around boot issues
Mark Brown [Sun, 1 May 2022 17:47:13 +0000 (18:47 +0100)] 
ARM: dts: imx6qdl-udoo: Disable USB host to work around boot issues

Attempting to boot my Udoo Dual and Quad with mainline hangs during boot
after printing:

[    3.270471] imx_usb 2184000.usb: No over current polarity defined
[    3.922502] mxs_phy 20c9000.usbphy: Data pin can't make good contact.
[    3.940097] imx_usb 2184200.usb: No over current polarity defined

where imx_usb 2184200.usb is usbh1 in the DT. Adding debug prints to the
code seems to show that we lock up at the first read in usbmisc_imx6q_init()
which in combination with the above logging about the USB controllers
suggests that we lock up on the first read in usbmisc_imx6q_init(). Looking
at some of the other i.MX6 boards and the warning messages that are being
printed suggests that there is bitrot in the DTS for the device so disable
it for now, with it disabled the board boots successfully.  Clearly this is
not a real fix, but it does allow some use of the board with mainline.

Similar behaviour is seen all the way back as far as v4.19, I tried going
back to when the board was added but had toolchain issues. Vendor provided
binaries seem fine on the boards so it seems likely that the hardware is
fine and the issue is with some combination of the DT and kernel.  This
should obviously be resolved properly but for now this at least allows
the kernel to boot with reduced functionality on these systems.

Signed-off-by: Mark Brown <broonie@kernel.org>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoARM: dts: imx27: use new 'dma-channels' property
Krzysztof Kozlowski [Wed, 27 Apr 2022 16:15:33 +0000 (18:15 +0200)] 
ARM: dts: imx27: use new 'dma-channels' property

The '#dma-channels' property was deprecated in favor of one defined by
generic dma-common DT bindings.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agodt-bindings: dmaengine: fsl-imx: deprecate '#dma-channels' and '#dma-requests'
Krzysztof Kozlowski [Wed, 27 Apr 2022 16:15:32 +0000 (18:15 +0200)] 
dt-bindings: dmaengine: fsl-imx: deprecate '#dma-channels' and '#dma-requests'

The generic properties, used in most of the drivers and defined in
generic dma-common DT bindings, are 'dma-channels' and 'dma-requests'.

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoARM: dts: imx6qdl-phytec: Add LED labels
Alexander Shiyan [Wed, 27 Apr 2022 09:42:05 +0000 (12:42 +0300)] 
ARM: dts: imx6qdl-phytec: Add LED labels

This allows boards the option of adding properties or disabling the
LEDs entirely.

Signed-off-by: Alexander Shiyan <eagle.alexander923@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agomm/readahead: Fix readahead with large folios
Matthew Wilcox (Oracle) [Wed, 27 Apr 2022 21:01:28 +0000 (17:01 -0400)] 
mm/readahead: Fix readahead with large folios

Reading 100KB chunks from a big file (eg dd bs=100K) leads to poor
readahead behaviour.  Studying the traces in detail, I noticed two
problems.

The first is that we were setting the readahead flag on the folio which
contains the last byte read from the block.  This is wrong because we
will trigger readahead at the end of the read without waiting to see
if a subsequent read is going to use the pages we just read.  Instead,
we need to set the readahead flag on the first folio _after_ the one
which contains the last byte that we're reading.

The second is that we were looking for the index of the folio with the
readahead flag set to exactly match the start + size - async_size.
If we've rounded this, either down (as previously) or up (as now),
we'll think we hit a folio marked as readahead by a different read,
and try to read the wrong pages.  So round the expected index to the
order of the folio we hit.

Reported-by: Guo Xuenan <guoxuenan@huawei.com>
Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
4 years agoblock: Do not call folio_next() on an unreferenced folio
Matthew Wilcox (Oracle) [Tue, 3 May 2022 04:09:31 +0000 (00:09 -0400)] 
block: Do not call folio_next() on an unreferenced folio

It is unsafe to call folio_next() on a folio unless you hold a reference
on it that prevents it from being split or freed.  After returning
from the iterator, iomap calls folio_end_writeback() which may drop
the last reference to the page, or allow the page to be split.  If that
happens, the iterator will not advance far enough through the bio_vec,
leading to assertion failures like the BUG() in folio_end_writeback()
that checks we're not trying to end writeback on a page not currently
under writeback.  Other assertion failures were also seen, but they're
all explained by this one bug.

Fix the bug by remembering where the next folio starts before returning
from the iterator.  There are other ways of fixing this bug, but this
seems the simplest.

Reported-by: Darrick J. Wong <djwong@kernel.org>
Tested-by: Darrick J. Wong <djwong@kernel.org>
Reported-by: Brian Foster <bfoster@redhat.com>
Tested-by: Brian Foster <bfoster@redhat.com>
Signed-off-by: Matthew Wilcox (Oracle) <willy@infradead.org>
4 years agoarm64: dts: freescale: reduce the interrup-map-mask
Michael Walle [Wed, 27 Apr 2022 07:53:36 +0000 (09:53 +0200)] 
arm64: dts: freescale: reduce the interrup-map-mask

Reduce the interrupt-map-mask of the external interrupt controller to
0xf to align with the devicetree schema.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoARM: dts: ls1021a: reduce the interrupt-map-mask
Michael Walle [Wed, 27 Apr 2022 07:53:35 +0000 (09:53 +0200)] 
ARM: dts: ls1021a: reduce the interrupt-map-mask

Reduce the interrupt-map-mask of the external interrupt controller to
7 to align with the devicetree schema.

Signed-off-by: Michael Walle <michael@walle.cc>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3
Adam Ford [Tue, 26 Apr 2022 20:51:44 +0000 (15:51 -0500)] 
arm64: dts: imx8mn-beacon: Enable RTS-CTS on UART3

There is a header for a DB9 serial port, but any attempts to use
hardware handshaking fail.  Enable RTS and CTS pin muxing and enable
handshaking in the uart node.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3
Adam Ford [Tue, 26 Apr 2022 20:51:43 +0000 (15:51 -0500)] 
arm64: dts: imx8mm-beacon: Enable RTS-CTS on UART3

There is a header for a DB9 serial port, but any attempts to use
hardware handshaking fail.  Enable RTS and CTS pin muxing and enable
handshaking in the uart node.

Signed-off-by: Adam Ford <aford173@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dts: imx8mm: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC
Marek Vasut [Tue, 26 Apr 2022 20:03:29 +0000 (22:03 +0200)] 
arm64: dts: imx8mm: Use 100 kHz I2C2 on Data Modul i.MX8M Mini eDM SBC

The I2C2 has SMBus device SMSC USB2514Bi connected to it, the device is
capable of up to 100 kHz operation. Reduce the bus frequency to 100 kHz
to guarantee this I2C device can work correctly.

Fixes: 583f24ae42a07 ("arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dts: imx8mm: Disable USB2 OC on Data Modul i.MX8M Mini eDM SBC
Marek Vasut [Tue, 26 Apr 2022 20:02:47 +0000 (22:02 +0200)] 
arm64: dts: imx8mm: Disable USB2 OC on Data Modul i.MX8M Mini eDM SBC

The USB2 port has USB Hub permanently connected to it, disable OC
to avoid getting false OC indication.

Fixes: 583f24ae42a07 ("arm64: dts: imx8mm: Add support for Data Modul i.MX8M Mini eDM SBC")
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
To: linux-arm-kernel@lists.infradead.org
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoarm64: dts: imx8mm: Add CPLD on MX8Menlo board
Marek Vasut [Tue, 26 Apr 2022 19:59:01 +0000 (21:59 +0200)] 
arm64: dts: imx8mm: Add CPLD on MX8Menlo board

The CPLD on MX8Menlo board is used to operate custom hardware,
the CPLD content is compatible with previous M53Menlo CPLD,
add the bindings.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@denx.de>
Cc: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Cc: NXP Linux Team <linux-imx@nxp.com>
Cc: devicetree@vger.kernel.org
To: linux-arm-kernel@lists.infradead.org
Reviewed-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoMerge branch 'ocelot-vcap-cleanups'
Jakub Kicinski [Thu, 5 May 2022 03:42:17 +0000 (20:42 -0700)] 
Merge branch 'ocelot-vcap-cleanups'

Vladimir Oltean says:

====================
Ocelot VCAP cleanups

This is a series of minor code cleanups brought to the Ocelot switch
driver logic for VCAP filters.

- don't use list_for_each_safe() in ocelot_vcap_filter_add_to_block
- don't use magic numbers for OCELOT_POLICER_DISCARD
====================

Link: https://lore.kernel.org/r/20220503120150.837233-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agonet: mscc: ocelot: don't use magic numbers for OCELOT_POLICER_DISCARD
Vladimir Oltean [Tue, 3 May 2022 12:01:50 +0000 (15:01 +0300)] 
net: mscc: ocelot: don't use magic numbers for OCELOT_POLICER_DISCARD

OCELOT_POLICER_DISCARD helps "kill dropped packets dead" since a
PERMIT/DENY mask mode with a port mask of 0 isn't enough to stop the CPU
port from receiving packets removed from the forwarding path.

The hardcoded initialization done for it in ocelot_vcap_init() is
confusing. All we need from it is to have a rate and a burst size of 0.

Reuse qos_policer_conf_set() for that purpose.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agonet: mscc: ocelot: drop port argument from qos_policer_conf_set
Vladimir Oltean [Tue, 3 May 2022 12:01:49 +0000 (15:01 +0300)] 
net: mscc: ocelot: drop port argument from qos_policer_conf_set

The "port" argument is used for nothing else except printing on the
error path. Print errors on behalf of the policer index, which is less
confusing anyway.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agonet: mscc: ocelot: use list_for_each_entry in ocelot_vcap_filter_add_to_block
Vladimir Oltean [Tue, 3 May 2022 12:01:48 +0000 (15:01 +0300)] 
net: mscc: ocelot: use list_for_each_entry in ocelot_vcap_filter_add_to_block

Unify the code paths for adding to an empty list and to a list with
elements by keeping a "pos" list_head element that indicates where to
insert. Initialize "pos" with the list head itself in case
list_for_each_entry() doesn't iterate over any element.

Note that list_for_each_safe() isn't needed because no element is
removed from the list while iterating.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agonet: mscc: ocelot: add to tail of empty list in ocelot_vcap_filter_add_to_block
Vladimir Oltean [Tue, 3 May 2022 12:01:47 +0000 (15:01 +0300)] 
net: mscc: ocelot: add to tail of empty list in ocelot_vcap_filter_add_to_block

This makes no functional difference but helps in minimizing the delta
for a future change.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agonet: mscc: ocelot: use list_add_tail in ocelot_vcap_filter_add_to_block()
Vladimir Oltean [Tue, 3 May 2022 12:01:46 +0000 (15:01 +0300)] 
net: mscc: ocelot: use list_add_tail in ocelot_vcap_filter_add_to_block()

list_add(..., pos->prev) and list_add_tail(..., pos) are equivalent, use
the later form to unify with the case where the list is empty later.

Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agodt-bindings: net: lan966x: fix example
Michael Walle [Tue, 3 May 2022 13:20:38 +0000 (15:20 +0200)] 
dt-bindings: net: lan966x: fix example

In commit 4fdabd509df3 ("dt-bindings: net: lan966x: remove PHY reset")
the PHY reset was removed, but I failed to remove it from the example.
Fix it.

Fixes: 4fdabd509df3 ("dt-bindings: net: lan966x: remove PHY reset")
Reported-by: Rob Herring <robh@kernel.org>
Signed-off-by: Michael Walle <michael@walle.cc>
Acked-by: Rob Herring <robh@kernel.org>
Link: https://lore.kernel.org/r/20220503132038.2714128-1-michael@walle.cc
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agoselftests: ocelot: tc_flower_chains: specify conform-exceed action for policer
Vladimir Oltean [Tue, 3 May 2022 12:14:28 +0000 (15:14 +0300)] 
selftests: ocelot: tc_flower_chains: specify conform-exceed action for policer

As discussed here with Ido Schimmel:
https://patchwork.kernel.org/project/netdevbpf/patch/20220224102908.5255-2-jianbol@nvidia.com/

the default conform-exceed action is "reclassify", for a reason we don't
really understand.

The point is that hardware can't offload that police action, so not
specifying "conform-exceed" was always wrong, even though the command
used to work in hardware (but not in software) until the kernel started
adding validation for it.

Fix the command used by the selftest by making the policer drop on
exceed, and pass the packet to the next action (goto) on conform.

Fixes: 8cd6b020b644 ("selftests: ocelot: add some example VCAP IS1, IS2 and ES0 tc offloads")
Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com>
Reviewed-by: Ido Schimmel <idosch@nvidia.com>
Link: https://lore.kernel.org/r/20220503121428.842906-1-vladimir.oltean@nxp.com
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agodt-bindings: arm: fsl: add toradex,colibri-imx6ull
Denys Drozdov [Mon, 25 Apr 2022 16:23:50 +0000 (18:23 +0200)] 
dt-bindings: arm: fsl: add toradex,colibri-imx6ull

Add toradex,colibri-imx6ull for carrier board dts,
including aster, iris and iris-v2 device tree,
wifi and nonwifi variants for NAND and eMMC modules.

Signed-off-by: Denys Drozdov <denys.drozdov@toradex.com>
Signed-off-by: Marcel Ziswiler <marcel.ziswiler@toradex.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoARM: dts: imx6sl: Add a label for the cpu node
Fabio Estevam [Fri, 22 Apr 2022 19:55:37 +0000 (16:55 -0300)] 
ARM: dts: imx6sl: Add a label for the cpu node

Add a label for the cpu node, so that board devicetree files can
reference to the CPU node.

This is useful for describing a PMIC voltage that supplies the CPU
voltage.

For example:

&cpu0 {
cpu-supply = <&sw1_reg>;

Signed-off-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
4 years agoMerge branch 'insufficient-tcp-source-port-randomness'
Jakub Kicinski [Thu, 5 May 2022 02:22:34 +0000 (19:22 -0700)] 
Merge branch 'insufficient-tcp-source-port-randomness'

Willy Tarreau says:

====================
insufficient TCP source port randomness

In a not-yet published paper, Moshe Kol, Amit Klein, and Yossi Gilad
report being able to accurately identify a client by forcing it to emit
only 40 times more connections than the number of entries in the
table_perturb[] table, which is indexed by hashing the connection tuple.
The current 2^8 setting allows them to perform that attack with only 10k
connections, which is not hard to achieve in a few seconds.

Eric, Amit and I have been working on this for a few weeks now imagining,
testing and eliminating a number of approaches that Amit and his team were
still able to break or that were found to be too risky or too expensive,
and ended up with the simple improvements in this series that resists to
the attack, doesn't degrade the performance, and preserves a reliable port
selection algorithm to avoid connection failures, including the odd/even
port selection preference that allows bind() to always find a port quickly
even under strong connect() stress.

The approach relies on several factors:
  - resalting the hash secret that's used to choose the table_perturb[]
    entry every 10 seconds to eliminate slow attacks and force the
    attacker to forget everything that was learned after this delay.
    This already eliminates most of the problem because if a client
    stays silent for more than 10 seconds there's no link between the
    previous and the next patterns, and 10s isn't yet frequent enough
    to cause too frequent repetition of a same port that may induce a
    connection failure ;

  - adding small random increments to the source port. Previously, a
    random 0 or 1 was added every 16 ports. Now a random 0 to 7 is
    added after each port. This means that with the default 32768-60999
    range, a worst case rollover happens after 1764 connections, and
    an average of 3137. This doesn't stop statistical attacks but
    requires significantly more iterations of the same attack to
    confirm a guess.

  - increasing the table_perturb[] size from 2^8 to 2^16, which Amit
    says will require 2.6 million connections to be attacked with the
    changes above, making it pointless to get a fingerprint that will
    only last 10 seconds. Due to the size, the table was made dynamic.

  - a few minor improvements on the bits used from the hash, to eliminate
    some unfortunate correlations that may possibly have been exploited
    to design future attack models.

These changes were tested under the most extreme conditions, up to
1.1 million connections per second to one and a few targets, showing no
performance regression, and only 2 connection failures within 13 billion,
which is less than 2^-32 and perfectly within usual values.

The series is split into small reviewable changes and was already reviewed
by Amit and Eric.
====================

Link: https://lore.kernel.org/r/20220502084614.24123-1-w@1wt.eu
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agotcp: drop the hash_32() part from the index calculation
Willy Tarreau [Mon, 2 May 2022 08:46:14 +0000 (10:46 +0200)] 
tcp: drop the hash_32() part from the index calculation

In commit 190cc82489f4 ("tcp: change source port randomizarion at
connect() time"), the table_perturb[] array was introduced and an
index was taken from the port_offset via hash_32(). But it turns
out that hash_32() performs a multiplication while the input here
comes from the output of SipHash in secure_seq, that is well
distributed enough to avoid the need for yet another hash.

Suggested-by: Amit Klein <aksecurity@gmail.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agotcp: increase source port perturb table to 2^16
Willy Tarreau [Mon, 2 May 2022 08:46:13 +0000 (10:46 +0200)] 
tcp: increase source port perturb table to 2^16

Moshe Kol, Amit Klein, and Yossi Gilad reported being able to accurately
identify a client by forcing it to emit only 40 times more connections
than there are entries in the table_perturb[] table. The previous two
improvements consisting in resalting the secret every 10s and adding
randomness to each port selection only slightly improved the situation,
and the current value of 2^8 was too small as it's not very difficult
to make a client emit 10k connections in less than 10 seconds.

Thus we're increasing the perturb table from 2^8 to 2^16 so that the
same precision now requires 2.6M connections, which is more difficult in
this time frame and harder to hide as a background activity. The impact
is that the table now uses 256 kB instead of 1 kB, which could mostly
affect devices making frequent outgoing connections. However such
components usually target a small set of destinations (load balancers,
database clients, perf assessment tools), and in practice only a few
entries will be visited, like before.

A live test at 1 million connections per second showed no performance
difference from the previous value.

Reported-by: Moshe Kol <moshe.kol@mail.huji.ac.il>
Reported-by: Yossi Gilad <yossi.gilad@mail.huji.ac.il>
Reported-by: Amit Klein <aksecurity@gmail.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agotcp: dynamically allocate the perturb table used by source ports
Willy Tarreau [Mon, 2 May 2022 08:46:12 +0000 (10:46 +0200)] 
tcp: dynamically allocate the perturb table used by source ports

We'll need to further increase the size of this table and it's likely
that at some point its size will not be suitable anymore for a static
table. Let's allocate it on boot from inet_hashinfo2_init(), which is
called from tcp_init().

Cc: Moshe Kol <moshe.kol@mail.huji.ac.il>
Cc: Yossi Gilad <yossi.gilad@mail.huji.ac.il>
Cc: Amit Klein <aksecurity@gmail.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agotcp: add small random increments to the source port
Willy Tarreau [Mon, 2 May 2022 08:46:11 +0000 (10:46 +0200)] 
tcp: add small random increments to the source port

Here we're randomly adding between 0 and 7 random increments to the
selected source port in order to add some noise in the source port
selection that will make the next port less predictable.

With the default port range of 32768-60999 this means a worst case
reuse scenario of 14116/8=1764 connections between two consecutive
uses of the same port, with an average of 14116/4.5=3137. This code
was stressed at more than 800000 connections per second to a fixed
target with all connections closed by the client using RSTs (worst
condition) and only 2 connections failed among 13 billion, despite
the hash being reseeded every 10 seconds, indicating a perfectly
safe situation.

Cc: Moshe Kol <moshe.kol@mail.huji.ac.il>
Cc: Yossi Gilad <yossi.gilad@mail.huji.ac.il>
Cc: Amit Klein <aksecurity@gmail.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agotcp: resalt the secret every 10 seconds
Eric Dumazet [Mon, 2 May 2022 08:46:10 +0000 (10:46 +0200)] 
tcp: resalt the secret every 10 seconds

In order to limit the ability for an observer to recognize the source
ports sequence used to contact a set of destinations, we should
periodically shuffle the secret. 10 seconds looks effective enough
without causing particular issues.

Cc: Moshe Kol <moshe.kol@mail.huji.ac.il>
Cc: Yossi Gilad <yossi.gilad@mail.huji.ac.il>
Cc: Amit Klein <aksecurity@gmail.com>
Cc: Jason A. Donenfeld <Jason@zx2c4.com>
Tested-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>
4 years agotcp: use different parts of the port_offset for index and offset
Willy Tarreau [Mon, 2 May 2022 08:46:09 +0000 (10:46 +0200)] 
tcp: use different parts of the port_offset for index and offset

Amit Klein suggests that we use different parts of port_offset for the
table's index and the port offset so that there is no direct relation
between them.

Cc: Jason A. Donenfeld <Jason@zx2c4.com>
Cc: Moshe Kol <moshe.kol@mail.huji.ac.il>
Cc: Yossi Gilad <yossi.gilad@mail.huji.ac.il>
Cc: Amit Klein <aksecurity@gmail.com>
Reviewed-by: Eric Dumazet <edumazet@google.com>
Signed-off-by: Willy Tarreau <w@1wt.eu>
Signed-off-by: Jakub Kicinski <kuba@kernel.org>