Edward Chow [Wed, 11 Mar 2026 08:19:26 +0000 (16:19 +0800)]
mac80211: ath9k: patch hw.c for gpio mask from dt
"qca,gpio-mask" used to be read between ath9k_hw_init() and
ath9k_init_queues(). After 12913c3c5658992985e13f4395dee86e5450154d
it is read in ath9k_of_init(), but it gets overwritten by
ath9k_gpio_cap_init() during the call of ath9k_hw_init(), and causes
https://github.com/openwrt/openwrt/issues/22340
If keeping the most of 12913c3c5658992985e13f4395dee86e5450154d,
ath9k_gpio_cap_init() could be patched to keep the existing non-zero
gpio mask (coming from device tree).
Fabrice Fontaine [Sat, 14 Mar 2026 19:55:40 +0000 (20:55 +0100)]
tools/erofs-utils: assign PKG_CPE_ID
cpe:/a:erofs-utils_project:erofs-utils is the correct CPE ID for erofs-utils:
https://nvd.nist.gov/products/cpe/search/results?keyword=cpe:2.3:a:erofs-utils_project:erofs-utils
Rustam Adilov [Wed, 18 Feb 2026 15:26:42 +0000 (20:26 +0500)]
realtek: clk: add rtl9607 clock support
This commit adds support for RTL9607C/RTL8198D clocks to the existing
clk-rtl83xx driver. Setting clock rates is not supported due to
lack of knowledge on this topic at the moment. Clocks for CPU1, SRAM
and SPI can also be calculated but not included in this commit.
Since the registers, calculations are widely different to RTL83XX it
was decide to have different clk_ops for RTL960X.
The code was partly based on naseef's work with some changes to
integrate it into the clk-rtl83xx driver.
Tested-by: Ahmed Naseef <naseefkm@gmail.com> Signed-off-by: Rustam Adilov <adilov@tutamail.com> Link: https://github.com/openwrt/openwrt/pull/22080 Signed-off-by: Robert Marko <robimarko@gmail.com>
If the user removes all /lib/apk/packages/*.conffiles* files to prevent
sysupgrade from preserving configuration, the glob no longer matches and
sysupgrade ends up calling cat on a non-existent path:
cat: can't open '/lib/apk/packages/*.conffiles_static': No such file or directory
Edward Chow [Thu, 17 Jul 2025 11:29:10 +0000 (19:29 +0800)]
ath79: untag to cpu ports on 2-cpu-port devices by default
Currently, devices having two cpu ports to the switch managed by swconfig,
especally those with qca955x, line tplink archer c7 v2 and linksys ea4500 v3,
use vlan on different cpu port to separate networks by default. (e.g. eth1.1
for lan, eth0.2 for wan)
However, untagging to these vlans cpu ports, and limiting vlans in the switch
on these devices could effectively offload the expense to process vlan tag from
cpu to the switch, and increase the throughput of lan <-> wan ipoe routing.
Tested on my tplink tl-wdr4900 v2, where ucidef_add_switch "switch0"
"0u@eth1" "2:lan" "3:lan" "4:lan" "5:lan" "6u@eth0" "1:wan" finally generates
on /etc/config/network:
config device
option name 'br-lan'
option type 'bridge'
list ports 'eth1'
config interface 'lan'
option device 'br-lan'
option proto 'static'
list ipaddr '192.168.1.1/24'
option ip6assign '60'
config interface 'wan'
option device 'eth0'
option proto 'dhcp'
config interface 'wan6'
option device 'eth0'
option proto 'dhcpv6'
and the throughput of lan <-> wan ipoe routing with software flow offload
increases from around
[850 Mbps](https://openwrt.org/toh/tp-link/archer-c5-c7-wdr7500#nat_performance)
to 900 Mbps.
Rosen Penev [Thu, 26 Feb 2026 04:27:50 +0000 (20:27 -0800)]
lantiq: convert ralink,mtd-eeprom to nvmem
These devices use the binding + eeprom-swap. Turns out the reason swap
is needed is because the binding wrongly swaps the data on big endian
hosts. NVMEM doesn't do this and thus just works.
Felix Fietkau [Thu, 19 Mar 2026 09:38:21 +0000 (09:38 +0000)]
hostapd: ubus: add missing token to beacon report notification
The beacon measurement token was not included in the ubus beacon-report
notification, causing consumers that need the token (e.g. for constructing
Beacon Metrics Response TLVs) to receive null.
Felix Fietkau [Wed, 18 Mar 2026 15:58:52 +0000 (15:58 +0000)]
hostapd: ubus: fix beacon request reporting detail field size
The Reporting Detail value is a 1-byte field, but was written as le16,
producing a 2-byte write that also contradicts the length field of 1
in the subelement header.
Felix Fietkau [Wed, 18 Mar 2026 15:58:37 +0000 (15:58 +0000)]
hostapd: ubus: fix beacon request buffer overflow with reporting detail
The reporting detail subelement (up to 3 bytes) was not accounted for
in the wpabuf allocation, causing a crash when reporting_detail is set
to a valid value (0, 1, or 2).
Rosen Penev [Tue, 17 Mar 2026 03:24:01 +0000 (20:24 -0700)]
ramips: cpe200: fix eeprom size
A size of 600 is incomplete in that calibration data is not included,
resulting in low TX power.
Fixes: 64dae105 ("ramips: mt76x8: add support for Yuncore CPE200") Signed-off-by: Rosen Penev <rosenp@gmail.com> Link: https://github.com/openwrt/openwrt/pull/22459 Signed-off-by: Robert Marko <robimarko@gmail.com>
Shine [Wed, 18 Mar 2026 20:08:38 +0000 (21:08 +0100)]
wifi-scripts: fix hostapd config for 160MHz
After 02e2065203c5e6c95f88e3501644d3e6ad740f89, it can happen that both,
[VHT160-80PLUS80] and [VHT160] are added to the vht_capab option in
an AP's hostapd.conf, which would cause a failure to start the AP.
Fix the logic in order to prevent such misconfiguration.
Rosen Penev [Wed, 11 Feb 2026 00:29:33 +0000 (16:29 -0800)]
ramips: dir-3040-a1: fix MAC address assignment
The dtsi used handles a bunch of non-DBDC platforms where the
assignments are correct. The 3040-a1 is different as there are 3 instead
of 2 wifi interfaces and WAN needs to be incremented by 1.
Remove userspace wifi assignmwent which was needed before per band nvmem
was supported.
Add support for Nokia Valyrian based on Airoha AN7581 SoC.
Device specification
--------------------
SoC Type: Airoha AN7581
RAM: 2x DDR4 Nanya NT5AD256M16E4-JR (1GB)
Flash: eMMC Macronix MX52LM08A11XVW (1GB)
Ethernet: 3x gigabit via AN7581, 1x 10g via AS21x1x, 1x SFP cage
Wi-Fi: MT7996 - BE19000
LEDs: 11 LED via 2x 74HC595 shift register
Button: Reset, WPS, WiFi
USB ports: 1x 2.0
Miscellaneous: 1x Power Monitor via RTQ6059, 2x FXS port
Device is unfused and is originally flashed with Airoha SDK bootloader
that require signed images.
Bootloader is username/password protected and use the leaked auth combo
that can be found online.
From the bootloadet instruction on how to flash custom bootloader are:
1. mmc erase 0 0x800
2. tftpboot 192.168.1.10:airoha/an7581/openwrt-airoha-an7581-nokia_valyrian-preloader.bin
3. mmc write $loadaddr 0x4 0xfc
4. tftpboot 192.168.1.10:airoha/an7581/openwrt-airoha-an7581-nokia_valyrian-bl31-uboot.fip
5. mmc write $loadaddr 0x100 0x700
It's also possible to use the Emergency Recovery procedure:
From powered OFF device:
1. Keep the reset button pressed (middle button)
2. Power on the device
3. Notice the "Press x" prompt
4. Press x
5. Notice the "C" char waiting for XMODEM load
6. Load the preloader binary with XMODEM protocol
7. Notice the "Press x to load BL31 + U-Boot FIP"
8. Press x
9. Notice the "C" char waiting for XMODEM load
10. Load the fip binary with XMODEM protocol
11. You are now in U-Boot loaded from serial
12. Follow normal procedure to flash bootloader
Due to BOOTROM limitation. the device can't have a standard GPT table
implementation. Because of this fixed-partitions are used to handle this.
U-Boot still doesn't have support for this (it's planned) and currently to flash
and load and image it's needed to write and read from static address in eMMC.
The GPT partition table follow Prpl guidelines with dual partition table with
kernel and rootfs split.
The address for kernel is 0xb00000 and the address for rootfs is 0x1b00000.
160e5fa3957c odhcpd: ensure zero padding on DNSSL 2a316dbfd798 odhcpd: ignore NULL in dhcpv4_free_lease() stub b960d4cbe27b ubus: fix truncated field in DHCPv6 lease query 4e26e1361335 dhcpv4: fix avl_delete on leases not in avl tree ea5af5bffa2d dhcpv4: fix segfault when disabling interface
Hauke Mehrtens [Mon, 16 Mar 2026 01:40:09 +0000 (02:40 +0100)]
lantiq: adapt gpio-stp-xway node name to get clock
The MIPS code assigns the clock node based on the device tree node name.
This name was renamed with kernel 6.12.58 and v6.6.117. Adapt our out of
tree device tree files to this rename to fix loading the STP GPIO
driver.
Without this fix the driver fails like this:
```
[ 0.320000] gpio-stp-xway 1e100bb0.stp: Failed to get clock
[ 0.330000] gpio-stp-xway 1e100bb0.stp: probe with driver gpio-stp-xway failed with error -2
```
David Bauer [Sun, 15 Mar 2026 16:47:15 +0000 (17:47 +0100)]
wifi: mt76: mt7915: set mt76 specific PS flag
mt76 tracks the PSM state of a sta internally with a wcid flag. TX to
such clients is skipped based on the presence of this flag.
This flag was not added to the PS state notify handler for MT7915 chips.
Without this flag, mt76 queues pending frames to the hardware,
accounting for airtime when a PSM notification is received while in a TX
iteration.
Set the PS flag for the STA WCID to prevent this from happening. TX gets
skipped in presence of this flag.
Kenneth Kasilag [Mon, 16 Mar 2026 09:25:53 +0000 (09:25 +0000)]
airoha: rename kmod-pwm-an7581 to kmod-pwm-airoha
Certain targets for an7581 and an7583 referred to kmod-pwm-airoha;
however in the target modules makefile the module is referred to
as kmod-pwm-an7581, causing buildbot to fail.
Change the name of kmod-pwm-an7581 to kmod-pwm-airoha to resolve this.
Andrew LaMarche [Thu, 12 Mar 2026 13:22:03 +0000 (13:22 +0000)]
airoha: an7581: fix w1700k fan script
W1700K fan script is missing the #!/bin/sh /etc/rc.common shebang and
requires execution bits set. Also, set the fallback to hwmon 3 instead
of 5, since the new RTL PHY driver was not merged.
Shiji Yang [Sun, 15 Mar 2026 13:05:08 +0000 (21:05 +0800)]
qualcommax: move EAP623 Outdoor dts to the correct folder
The device dts files were moved to the dedicated directory in commit a66e30631c87 ("qualcommax: move Device DTS to dedicated DTS directory"),
which resulted in a merge conflict.
Fixes: d755c49f7a8a ("qualcommax: ipq60xx: rename TP-Link EAP623-Outdoor HD v1 compatible") Signed-off-by: Shiji Yang <yangshiji66@outlook.com> Link: https://github.com/openwrt/openwrt/pull/22433 Signed-off-by: Robert Marko <robimarko@gmail.com>
Jan Hoffmann [Tue, 23 Dec 2025 19:40:52 +0000 (20:40 +0100)]
realtek: enable MDI swapping for RTL8226 where needed
The RTL8226 PHYs in Zyxel XGS1010-10 and XGS1210-10 rev A1 have swapped
MDI lanes. Specify this in the device tree, so the driver can configure
it. With this change, the PHYs no longer require initialization by the
bootloader.
Jan Hoffmann [Tue, 23 Dec 2025 19:38:31 +0000 (20:38 +0100)]
realtek: support MDI swapping for RTL8226 PHY
The PHY supports swapping the MDI pairs (ABCD->DCBA) to simplify board
layout. On devices making use of this, it needs to be configured in the
driver, otherwise the PHY won't work properly.
Doug Freed (1):
wg-quick@.service: add deps on wg-quick.target
Jason A. Donenfeld (8):
wg-quick: linux: use smallest mtu, not largest
syncconf: account for psks removed from config file
wg-quick: linux: deal with resolvconf migration more gracefully
wg-quick: use addconf instead of setconf
wg-quick: linux: do not unnecessarily set sysctl
config: preserve const correctness
syncconf: account for persistent keepalive removed from config file
version: bump
Robyn Kosching (1):
wg-quick: pass on # comments to {Pre,Post}{Up,Down}
The dsa irq handler works always in the same way for all SoCs.
- Read register ISR_PORT_LINK_STS_CHG to determine the ports that
triggered the irq.
- Write the read value back to the register to confirm the irq
- Read link status via MAC_LINK_STS
- Trigger dsa_port_phylink_mac_change() for each changed port
Currently each SoC has its own implementation. Drop that in
favour of a generic implementation that makes use of the existing
bit register read/write helpers.
Jan Kantert [Sat, 28 Feb 2026 23:09:19 +0000 (00:09 +0100)]
realtek: use 50kHz I2C for SFPs on Xikestor SKS8300-8X
Some 10G optics showed random "module transmit fault indicated" due to I2C
read errors on ONTi ONT-S508CL-8S/XikeStor SKS8300-8X switches. The same
modules work with the original firmware and on other Linux based devices.
There seems to be some differences in how we talk to those modules using
I2C in OpenWRT. To fix this this patch adds support for 50kHz I2C speed on
SFPs and enables that for XikeStor/Onti devices. Since SFPs only transmit
very few bytes this should not have any real downsides.
This patch configures I2C to use 50kHz clock in the DTS for the affected
devices. For it to work it requires a change in the RTL9300 I2C driver.
This can be safely merged without the kernel change (but will not work
in that case as it will fall back to 100kHz).
qualcommax: ipq60xx: unify common make rules for eap6xx
The main difference between EAP610, 623, and 625 is the device name,
support string, and the BDF package. Move the others to a common
Device/tplink_eap6xx-common in order to highlight the common aspects.
The EAP625 and EAP623 are extremely similar. The only difference in
the vendor's device tree is that EAP625 also enables USB and UART2.
Use the eap6xx dtsi instead of writing out a full devicetree.
The EAP623 uses the same RTL8211F as the 625 and 610. Since this is
a gigabit PHY, it is okay to change the ess mac mode from SGMII_PLUS
to SGMII. This is now consistent across all three devices.
Move the 'realtek,clkout-disable' and 'realtek,aldps-enable' PHY
properties to the common dtsi, as they work well on all three devices.
Reflect the remaining differences in the eap625 dts.
qualcommax: ipq60xx: eap6xx-outdoor: use yellow for LED color
As I was looking at the differences between EAP610, 623, and 625
Outdoor, I realized that the quick-start guide of all of the devices
mentions a yellow and green LED. Thus rename the "amber" led to
"yellow", and adjust its color ID accordingly.
qualcommax: ipq60xx: rename TP-Link EAP623-Outdoor HD v1 compatible
Originally, the .compatible string for EAP623-Outdoor HD tried to
shorten the "-outdoor" to "od". However, this naming was inconsistent
with the existing "eap610-outdoor". As "od" is not a common shorthand,
spell out the complete word: "eap623-outdoor-hd-v1".
Fixes: 5dbf93c8c5 ("ipq60xx: add support for TP-Link EAP623-Outdoor HD v1") Signed-off-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Link: https://github.com/openwrt/openwrt/pull/18804 Signed-off-by: Robert Marko <robimarko@gmail.com>
- Fix RTL8261N 10GbE PHY `reset-deassert-us` from 100ms to 221ms to meet datasheet minimum SMI-ready timing (t7 >= 150ms), fixing intermittent boot stalls caused by MDIO bus instability
- Add missing WLAN toggle button (GPIO 34) present in stock firmware but absent from OpenWrt DTS
- Fix memory size from 1 GB to the actual 512 MB
Fix 1: The RTL8261N 10GbE PHY's `reset-deassert-us` was set to 100ms (100000us), but the **RTL8261N datasheet (Table 108, parameter t7)** specifies a minimum **SMI-ready time of 150ms** after nRESET release before the MDIO (SMI) bus can be used.
With only 100ms, the kernel attempts MDIO bus access before the RTL8261N's SMI interface is stable. Since the RTL8261N (mdio-bus:00) and the internal MT7988 2.5GbE PHY (mdio-bus:0f) share the same MDIO bus, a not-yet-ready RTL8261N disrupts all MDIO traffic, causing the 2.5GbE PHY firmware loading (`mt798x_2p5ge_phy_config_init`) to stall.
Observed symptoms on warm reboot:
- Sometimes `mt798x_2p5ge_phy_config_init` hangs for 5+ minutes or indefinitely
- RCU CPU stalls (`rcu: INFO: rcu_sched detected stalls on CPUs`)
- mt7996e WiFi chip message timeouts cascading to `chip full reset failed`
- System appears hung with only power LED blinking slowly
UART serial log evidence (warm reboot with 100ms):
```
[ 73.041756] rcu: INFO: rcu_sched self-detected stall on CPU
[ 73.048341] rcu: 2-....: (8 ticks this GP)
[ 73.061641] pc : mt798x_2p5ge_phy_config_init+0x258/0xbb0
[ 73.061653] lr : mt798x_2p5ge_phy_config_init+0x238/0xbb0
...
[ 334.771280] MediaTek MT7988 2.5GbE PHY mdio-bus:0f: Firmware date code: 2024/10/30
```
The 2.5GbE PHY firmware loading, which normally takes ~3 seconds, took **325 seconds** due to MDIO bus instability. In the worst case, the system never recovers.
GPL DTS uses 221ms (`reset-deassert-us = <221000>`), providing 71ms of margin above the 150ms datasheet minimum. All MediaTek MT7988 reference board DTS files in the GPL use this same 221ms value.
Fix 2: Missing WLAN button (GPIO 34)
The BE450 has a physical WLAN toggle button on GPIO 34, defined in the stock TP-Link GPL DTS but missing from the OpenWrt DTS. Without this definition, the button is non-functional under OpenWrt.
The pin name for GPIO 34 in the MT7988 pinctrl is `SPI2_MISO`, confirmed by the kernel pinctrl driver (`pinctrl-mt7988.c`: `MT7988_PIN(34, "SPI2_MISO")`) and the official devicetree binding (`mediatek,mt7988-pinctrl.yaml`).
Note: GPIO 34 is also used by the BE450's First U-Boot as a recovery button (web recovery 192.168.1.1). Registering it in the DTS ensures the kernel claims the pin.
Fix 3: Incorrect memory size in DTS
The OpenWrt DTS declares 1 GB (`0x40000000`) of RAM, but the BE450 has 512 MB (`0x20000000`).
Fabrice Fontaine [Fri, 13 Mar 2026 19:57:11 +0000 (20:57 +0100)]
tools/expat: fix PKG_CPE_ID
cpe:/a:libexpat_project:libexpat is the correct CPE ID for expat:
https://nvd.nist.gov/products/cpe/search/results?keyword=cpe:2.3:a:libexpat_project:libexpat
Jonas Jelonek [Fri, 27 Feb 2026 08:59:00 +0000 (08:59 +0000)]
realtek: pcs: rtl931x: use generic CMU configuration
The current CMU setup was just copied and slightly adjusted from the
SDK, lacks functionality and logic and doesn't cover all cases we need
(same in the SDK due to multiple reasons). The existing implementation
for RTL930x covers all that and can be reused for RTL931x. Previous
patches made this generic and now we can add the remaining missing
pieces to actually use it for RTL931x. This only includes
implementations for the few variant-specific actions within the
implementation, linking them properly and calling the CMU configuration.
Drop the old CMU code for RTL931x then since it's not needed anymore.
Jonas Jelonek [Tue, 24 Feb 2026 22:00:43 +0000 (22:00 +0000)]
realtek: pcs: rtl931x: improve CMU page mapping
Improve the RTL931x mapper to infer the CMU page from the hardware mode
by replace unneeded with useful comments, returning a better error code
and dropping irrelevant parts.
Jonas Jelonek [Tue, 24 Feb 2026 21:22:05 +0000 (21:22 +0000)]
realtek: pcs: make rtl930x CMU config generic
Generalize the RTL930x CMU configuration to support RTL931x as well.
Both implementations differ only in minor details, allowing them to
share common code and avoid duplication.
Affected functions are moved up in the code to the 93xx common area and
slightly renamed. Existing variant-specific functions are adjusted too
and assigned to the previously added SerDes operation hooks.
Jonas Jelonek [Tue, 24 Feb 2026 18:22:45 +0000 (18:22 +0000)]
realtek: pcs: add CMU management SerDes ops
Add new SerDes ops for CMU management to be able to share common
behavior of CMU configuration for RTL930x and RTL931x while still
covering variant specifics.
Jonas Jelonek [Tue, 24 Feb 2026 17:05:28 +0000 (17:05 +0000)]
realtek: pcs: rtl930x: fix naming and error handling
Fix naming of several functions to better reflect what they are doing.
While at it, also improve the error handling a lot, changing the return
type from void to int and actually returning errors.
Jonas Jelonek [Tue, 24 Feb 2026 12:11:18 +0000 (12:11 +0000)]
realtek: pcs: rtl930x: move CMU reset into PLL config
Move resetting the CMU into the PLL configuration itself where the speed
is set. Since this operation is not dependent of the target SerDes and
only needs to be called if the speed changed, it fits better there.
Though the call was guarded with a 'speed_changed' before, this also
applies to actually changing the speed. This was done before anyway,
even if the speed value hasn't really changed.
Add a mapper function to infer the to-be-selected PLL speed from the
desired SerDes hardware mode. This avoids having similar logic in each
CMU implementation.
Jonas Jelonek [Tue, 24 Feb 2026 00:14:12 +0000 (00:14 +0000)]
realtek: pcs: rtl930x: split pll config
Split up PLL configuration of RTL930x in the two distinct actions of
configuring the PLL itself (aka setting its speed, etc.) and selecting
which PLL is used by a SerDes.
It was found that for both RTL930x and RTL931x, PLL configuration can be
combined while selecting the PLL a SerDes uses differs and needs to be
implemented variant-specific.
Jonas Jelonek [Mon, 23 Feb 2026 22:10:45 +0000 (22:10 +0000)]
realtek: pcs: rtl930x: use generic PLL type definition
Make use of the generic PLL type definition in the current CMU/PLL
configuration code for RTL930x. Assign explicit values to the fields of
the PLL type enum to tie these fields to the values that are used in
the register fields. This allows to simplify the code a bit.
Selecting the PLL to use for a SerDes shares some similarities between
RTL930x and RTL931x. While the location of the selector in the registers
is placed different, similar underlying bit semantics are used. This
allows to reuse the same plain values for both. RTL930x uses a force bit
and a selector bit, RTL931x at least uses the selector bit with the same
values for ring and LC PLL.
Jonas Jelonek [Mon, 23 Feb 2026 21:44:37 +0000 (21:44 +0000)]
realtek: pcs: rtl930x: use generic PLL speed definition
Make use of the generic PLL speed definition in the current CMU/PLL
configuration code for RTL930x. Assign explicit values to the field of
the PLL speed enum to tie these fields to the values that are used in
the register fields. This allows to simplify the code a bit.
Setting the actual speed selector for RTL930x was found to be similar to
RTL931x despite of different values being used since the LSB is always 1.
According to the SDK this seems to be a force bit while the other bits
are the actual value/selector that is being forced. For RTL930x,
separate the speed selection to be able to use that as common behavior
for both variants later.
Jonas Jelonek [Mon, 23 Feb 2026 21:17:51 +0000 (21:17 +0000)]
realtek: pcs: bring PLL definitions into shape
Bring the PLL definitions into a proper shape. While there was already a
definition for the PLL type, a generic PLL speed definition was missing.
Introduce such a definition and adjust the naming of the existing PLL
type definition to have a better distinction and avoid conflicts. The
definitions can and should be used to make the CMU/PLL configuration
more generic and reduce the need for variant-specific definitions.
The ethernet driver configures the SoC internal network card
on its own. There are no special serdes or other layers in
between. So there is no need for pcs handling in the driver.
Drop that.
These devices contain a single MAC address in the U-Boot environment.
Set it as eth0 and label MAC in device tree. To maintain the current
state, the 02_network script still sets individual port MAC addresses
and the bridge MAC address.
Jakub Vaněk [Tue, 3 Mar 2026 21:41:28 +0000 (22:41 +0100)]
mediatek: filogic: rename Cudy M3000 v1 to v1/v2
The Cudy M3000 v1/v2 seem to have mostly identical hardware.
The M3000 v1 OpenWrt images work on the M3000 v2 (excluding
the v2 parts with a different PHY). Cudy also distributes one
firmware image that supports both routers.
Rename the human-readable device variant to "v1/v2" to match this.
Don't change the compatible property as that hooks into the
attended sysupgrade process.
The recent flash and PHY changes don't seem to be related to the v1/v2
split. There exist M3000 v2 with the Realtek PHY, see e.g.
https://github.com/openwrt/openwrt/pull/21584#issuecomment-3864992555
Jakub Vaněk [Mon, 2 Mar 2026 20:14:28 +0000 (21:14 +0100)]
mediatek: filogic: add support for Cudy M3000 w/ YT8821 PHY
The hardware is very close the the Cudy M3000 v1 (see commit 20e4a18feb3f). However, the Motorcomm YT8821 PHY is tricky
to support because of a MDIO address collision within the router.
Specification:
- MT7981BA CPU: dual-core ARM Cortex-A53 @ 1.3 GHz
- 256 MiB RAM
- 128 MiB SPI NAND
- Ethernet:
- 1x 1GbE LAN port driven by the internal MT7981 PHY
- 1x 2.5GbE WAN port driven by the Motorcomm YT8821
- WiFi:
- MT7981BA 2.4 GHz WiFi with 2x2:2 MIMO
- MT7981BA 5 GHz WiFi with 2x3:2 MIMO
- Buttons: Reset, WPS
- LED: 1x combined red/white
How to know if you have the a router with the YT8821 PHY:
- Boot the router into the vendor's firmware. Go to Diagnostic Tools
-> System Log. Try searching for "rtl8221b".
- If there are some matches, you have the Cudy M3000 router with
the Realtek PHY and you should NOT use the device defined in this
commit. Instead, you should use the device defined in
mt7981b-cudy-m3000-v1.dts.
- If there are no matches, try searching for "yt8821". If that
matches something, you have the Cudy M3000 with the Motorcomm PHY
and you should use this device tree
(mt7981b-cudy-m3000-v2-yt8821.dts).
- If even the yt8821 string did not match anything, then something
is wrong. Rebooting the router might help (the system log would
be refreshed).
Installation via the Cudy web UI:
- Download the signed intermediary firmware from
https://drive.google.com/drive/folders/1BKVarlwlNxf7uJUtRhuMGUqeCa5KpMnj
- Flash the intermediary firmware using the Cudy web UI
- Connect a PC/laptop to the "1Gbps LAN" port
- Open http://192.168.1.1 in your browser, log in
(the password should be empty)
- Flash your desired OpenWrt firmware via LuCI
- The router should reboot into the desired firmware
How to access UART (citing from 20e4a18feb3f):
- remove rubber ring on the bottom
- remove screws
- pull up the cylinder, maybe help by push on an ethernet socket
with a screwdriver
- remove the (3) screws holding the board in the frame
- remove the board from the frame to get to the screws for the
silver, flat heat shield
- remove the (3) screws holding the heat shield
- solder UART pins to the back of the board
- make sure to have the pins point out on side with the black,
finned heat spread
- the markings for the pins are going to be below the silver heat
shield
- Vcc is not needed
- the UART parameters are 115200 baud, 8n1
Installation via UART (citing from 20e4a18feb3f):
- attach an Ethernet cable to the "1Gbps LAN" port on the router
- hold the reset button while powering the router
- press CTRL-C or wait for the timeout to get to the U-Boot prompt
- prepare a TFTP server on the network to supply ..-initramfs-kernel.bin
- use 'tftpboot 0x46000000 ..-initramfs-kernel.bin' in the U-Boot
shell to pull the image (change the file name accordingly)
- boot the image using 'bootm 0x46000000'
- push the ..-sysupgrade to the router using your preferred method
- perform the upgrade with 'sysupgrade -n'
Jakub Vaněk [Mon, 2 Mar 2026 19:36:29 +0000 (20:36 +0100)]
kernel: add patch for YT8821 address collision
This minimalistic patch should ensure that the Cudy M3000 with the
Motorcomm PHY works reliably. The patch is not upstreamable into the
mainline kernel. However, it could be sufficient as a simple stop-gap
measure until some other solution is found.
Tim Harvey [Fri, 20 Feb 2026 01:01:48 +0000 (17:01 -0800)]
imx: cortexa53: remove KSZ9477 static driver
The KSZ9477 driver was added to the cortexa53 kernel to support the
Gateworks Venice product family which has a board with this switch. Now
that the kmod-dsa-ksz9477 driver is available as a package remove the
static configuration ad add the package.
This resolves an issue caused by having the switch driver static and the
PHY driver as a module such that the PHY driver was not registered early
enough to be used causing some errata to not be worked around.
Tim Harvey [Fri, 20 Feb 2026 00:57:29 +0000 (16:57 -0800)]
kernel: netdevices: add KSZ9477 DSA switch support
This adds kernel packages for the Microchip KSZ9477 switch family.
The core package has a target specific dependency as the ksz9477
driver enables DCB which grows the kernel size and can negatively
impact other targets.
Matt Merhar [Fri, 6 Mar 2026 03:05:40 +0000 (22:05 -0500)]
mac80211: ath12k: backport thermal sensor support
This is nearly identical to what landed in ath-next for v7.1, aside from
resolving a couple conflicts. A separate patch has been added to replace
CONFIG_THERMAL with CPTCFG_ATH12K_THERMAL so the setting may be enabled
via menuconfig (as is done with ath10k and ath11k).
Note that at this stage, throttling has not been implemented upstream,
hence the slight change in wording versus existing options.
projects / thirdparty / openwrt.git / log
