hw/arm/fsl-imx8mm: Adding support for I2C emulation
This can be used to test and debug I2C device drivers.
Added I2C interrupts
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Enabled GPIO controller emulation
Also updated the GPIO IRQ lines of iMX8MM
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
This enables support for Designware PCI Express Controller emulation
It provides a controlled environment to debug the linux pci subsystem
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm/fsl-imx8mm: Adding support for USDHC storage controllers
It enables emulation of SD/MMC cards through a virtual SDHCI interface
The emulated SDHCI controller allows guest OS to use emulated storage as
a standard block device.
This will allow running the images such as those generated
by Buildroot.
Reviewed-by: Philippe Mathieu-Daude <philmd@linaro.org> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm/fsl-imx8mm: Add Clock Control Module IP to iMX8MM
Add the Clock Control Module (CCM) device to i.MX8MM SoC.
The CCM implementation is shared with i.MX8MP as the register
layout is identical between the two variants.Hence iMX8MM will
be using the source of iMX8MP CCM.
Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/arm/fsl-imx8mm: Add Analog device IP to iMX8MM SOC
Add the Analog IP to i.MX8MM SoC. iMX8MM and i.MX8MP uses
the same Analog IP so the analog ip source will be shared.
The ARM PLL divider control register (arm-pll-fdiv-ctl0) has
a different reset value on i.MX8MM (0x000fa030) compared to
i.MX8MP (0x000fa031). So iMX8MM will be overriding this property
with its own reset-value.
Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/misc/imx8mp_analog: Add property to analog device
Add configurable properties for register reset values that differ
between i.MX 8M variants (Plus, Mini, etc.). This allows the same
device implementation to be shared across multiple SoCs.
Properties added:
- arm-pll-fdiv-ctl0-reset: ARM PLL divider control reset value
Default value is set to match i.MX 8MP reset value (0x000FA031).
This can be overridden in the variant like iMX8MM with its own
reset value.
Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
And indeed, the "break" is unreachable since the previous self.fail()
always aborts immediately. Thus let's remove the "break" to make pylint
happy again.
Message-ID: <20260427080731.389061-1-thuth@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
hw/arm: Add the i.MX 8MM EVK(Evaluation Kit) board
Implemented CPUs, RAM, UARTs and Interrupt Controller
Other peripherals are represented as TYPE_UNIMPLEMENTED_DEVICE
Complete memory map of the SoC is provided.
Set default RAM size to 2GB and default CPU count to 4 to match
the real i.MX8MM EVK hardware configuration.
Documentation is shared with imx8mp-evk to avoid duplication.
Signed-off-by: Gaurav Sharma <gaurav.sharma_7@nxp.com>
[PMM: fixed over-long lines in doc] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Bernhard Beschow <shentey@gmail.com> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Alex Bennée [Tue, 21 Apr 2026 09:35:06 +0000 (10:35 +0100)]
docs/system: add FEAT_AA32 and FEAT_AA64 to emulation list
This is just a documentation tweak as we already support both.
FEAT_AA32 implies FEAT_AA32EL0. FEAT_AA64 implies FEAT_AA64EL[0123].
This is however useful if you are using emulation.rst as a source of
truth of what QEMU emulates and when cross checking with
Features.json from Arm.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20260421093506.616307-1-alex.bennee@linaro.org Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
hw/i386/fw_cfg: Use g_new() and g_new0() instead of g_malloc()
Replace g_malloc() and g_malloc0() calls that calculate the allocation
size using sizeof() with the type-safe g_new() and g_new0() macros.
This aligns the code with QEMU's coding style guidelines, improving
readability and protecting against potential integer overflow
vulnerabilities when allocating arrays.
Luc Michel [Fri, 24 Apr 2026 15:56:44 +0000 (17:56 +0200)]
hw/core/register: add register_array_get_owner
Add the register_array_get_owner function to the register API. This
function can be used to retrieve the device owning the given
RegisterInfoArray.
This was previously done inline by some devices. 5c6367bc1c8850f74812eeaaf87cff9911be58de modified the way register
blocks are created and parented to the device. Since this is an
implementation detail of the register API, it makes sense to have a
function for this.
Use it in the Versal OSPI and Versal/ZynqMP eFuse models instead of
tinkering with the API internals.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3421
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3422
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3423 Signed-off-by: Luc Michel <luc.michel@amd.com> Tested-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Fixes: 5c6367bc1c8 ("hw/core/register: add the REGISTER_ARRAY type") Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260424155646.533334-1-luc.michel@amd.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Wed, 22 Apr 2026 07:11:44 +0000 (09:11 +0200)]
tests/functional/qemu_test: Silence warnings from pylint in tesseract.py
Pylint complains:
tesseract.py:1:0: C0114: Missing module docstring (missing-module-docstring)
tesseract.py:12:0: C0116: Missing function or method docstring (missing-function-docstring)
tesseract.py:15:11: W1510: 'subprocess.run' used without explicitly defining the value for 'check'. (subprocess-run-check)
tesseract.py:12:30: W0613: Unused argument 'tesseract_args' (unused-argument)
Thus add the missing bits and remove the unused tesseract_args argument.
While we're at it, also add a SPDX identifier instead of the weird three
dots at the beginning of the file, and drop the license boilerplate text.
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260422071145.244820-1-thuth@redhat.com>
The pthread_get_name_np function is present on FreeBSD and OpenBSD
and has 'void' return not 'int'. We didn't notice this build problem
on FreeBSD since it also has pthread_getname_np which does return
int like Linux and we use the latter preferentially.
Fixes: 215235d365e49c72a85ea2940751e45419676031 Closes: https://gitlab.com/qemu-project/qemu/-/work_items/3399 Signed-off-by: Daniel P. Berrangé <berrange@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260417120531.2215549-1-berrange@redhat.com> Signed-off-by: Thomas Huth <thuth@redhat.com>
Thomas Huth [Wed, 25 Mar 2026 12:09:44 +0000 (13:09 +0100)]
target/i386/tcg/sysemu: Allow 32-bit SMM code to be used in the 64-bit binary
This is a preparation for the QEMU universal binary where we might want
to support both, the x86_64 and the i386 target, in one binary. Instead
of using #ifdef TARGET_X86_64 here, check the LM bit to select the 32-bit
or 64-bit code during runtime.
Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260325120944.29391-3-thuth@redhat.com>
However, NetBSD 10 has already been released since two years ago
(see https://www.netbsd.org/releases/formal-10/NetBSD-10.0.html),
so according to our support policy, starting with QEMU v11.0, we
don't have to take care of the previous major release of NetBSD
anymore.
Looking at the various distros that we take care of (see e.g.
https://repology.org/project/gcc/versions), and the NetBSD 10.0
3rd party package information:
... it seems like NetBSD 10 has the lowest version of GCC again,
but at least it's GCC 10.4 now. Thus bump our GCC requirement to
this version now.
Reviewed-by: Daniel P. Berrangé <berrange@redhat.com> Acked-by: Fabiano Rosas <farosas@suse.de> Signed-off-by: Thomas Huth <thuth@redhat.com>
Message-ID: <20260310155331.320066-1-thuth@redhat.com>
linux-user: Flush errors by using exit() instead of _exit() in error path
Qemu user mode does not properly flushes error messages related to bad
arguments when exiting (at least when the output is piped to a file
instead of running on a terminal).
Ensure that we always flush by using exit() instead of _exit().
Stefan Hajnoczi [Sat, 25 Apr 2026 14:22:04 +0000 (10:22 -0400)]
Merge tag 'pbouvier/pr/plugins-20260424' of https://gitlab.com/p-b-o/qemu into staging
Changes:
- [PATCH v2 0/2] contrib/plugins/uftrace_symbols.py: fix issues to (Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>) Link: https://lore.kernel.org/qemu-devel/20260424194451.1439316-1-pierrick.bouvier@oss.qualcomm.com
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# =IZwN
# -----END PGP SIGNATURE-----
# gpg: Signature made Fri 24 Apr 2026 20:31:10 EDT
# gpg: using RSA key 37C15694D8BA9764B1973FDBB44437D19C2862DF
# gpg: Good signature from "Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 37C1 5694 D8BA 9764 B197 3FDB B444 37D1 9C28 62DF
* tag 'pbouvier/pr/plugins-20260424' of https://gitlab.com/p-b-o/qemu:
contrib/plugins/uftrace_symbols.py: handle missing source line from addr2line
contrib/plugins/uftrace_symbols.py: fix symbols reading
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Sat, 25 Apr 2026 14:21:42 +0000 (10:21 -0400)]
Merge tag 'hw-misc-20260422' of https://github.com/philmd/qemu into staging
Misc HW patches
- Build hw/avr/ as common unit files
- Header cleanups around 'cpu.h', 'qemu/audio.h' or duplicated lines
- Remove obsolete TPMIfClass::ppi_enabled field
- Cleanups around load/store API
- Restrict 'compat' properties API to system emulation
- Correct TPM PPCI ACPI for Windows guests on ARM Virt machine
- Simplify physical_memory_range_includes_clean()
- Avoid including CONFIG_DEVICES in hw/arm/smmuv3
- Initialize bus frequency in PPC e500 device tree blob
- More ATI VGA fixes
- Fix fuzzing issues on AVR power controller and SH4 MCU
- MAINTAINERS updates
- Machine compat array for v11.0.0 release
- USB EHCI cleanups
* tag 'hw-misc-20260422' of https://github.com/philmd/qemu: (62 commits)
MAINTAINERS: Transfer CI maintenance to Pierrick
MAINTAINERS: Maintain MIPS Boston
MAINTAINERS: Remove PhilMD from NVMe Block Driver
MAINTAINERS: Remove my disfunctional emails
MAINTAINERS: Remove my unused git tree locations
MAINTAINERS: Cover hexloader tests under the Generic Loader section
MAINTAINERS: Merge PCIe DOE section within SPDM
hw/usb/hcd-ehci: Introduce common properties macro for sysbus and pci
hw/usb/hcd-ehci: Replace DPRINTF debug logs with trace events
hw/usb/hcd-ehci.c: Replace fprintf(stderr, ...) with qemu_log_mask(LOG_GUEST_ERROR)
hw/usb/hcd-ehci.c: Fix coding style issues reported by checkpatch
hw/usb/hcd-ehci.h: Fix coding style issues reported by checkpatch
hw/usb/hcd-ehci: Remove unused EHCIfstn structure and dead code
hw/arm/virt: Do not select Kconfig symbol PCI_EXPRESS
hw/cxl: Define cxl_fmws_get_all_sorted() stub
hw/sh4/sh7750: Remove forgotten abort() in the MM_ITLB_DATA handler
hw/misc: Fix the valid access size to the avr-power device
hw/ppc/amigaone: remove duplicate include
hw/hyperv: remove duplicate include
hw/virtio/virtio-iommu: remove duplicate include
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Sat, 25 Apr 2026 14:21:12 +0000 (10:21 -0400)]
Merge tag 'pull-hex-20260423' of https://github.com/quic/qemu into staging
Hexagon arch rev specific behavior
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# gpg: Signature made Thu 23 Apr 2026 22:35:28 EDT
# gpg: using RSA key 3D66AAE474594824C88CE0F81A54AFB8E5646C32
# gpg: Good signature from "Brian Cain (OSS Qualcomm) <brian.cain@oss.qualcomm.com>" [unknown]
# gpg: aka "Brian Cain <bcain@kernel.org>" [unknown]
# gpg: aka "Brian Cain (QuIC) <bcain@quicinc.com>" [unknown]
# gpg: aka "Brian Cain (CAF) <bcain@codeaurora.org>" [unknown]
# gpg: aka "bcain" [unknown]
# gpg: aka "Brian Cain (QUIC) <quic_bcain@quicinc.com>" [unknown]
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 6350 20F9 67A7 7164 79EF 49E0 175C 464E 541B 6D47
# Subkey fingerprint: 3D66 AAE4 7459 4824 C88C E0F8 1A54 AFB8 E564 6C32
* tag 'pull-hex-20260423' of https://github.com/quic/qemu:
target/hexagon: Change DisasContext packet type
Hexagon (target/hexagon) Remove snprint_a_pkt_debug
tests/tcg/hexagon: Add test for revision-gated instruction decoding
Hexagon (target/hexagon) Disassembly of invalid packets
Hexagon (target/hexagon) Check each opcode against current CPU definition
Hexagon (target/hexagon) Introduce tag_rev_info.c.inc
Hexagon (target/hexagon) Add Hexagon definition field to DisasContext
Hexagon (linux-user/hexagon) Identify Hexagon version in ELF file
Hexagon (target/hexagon) Properly handle Hexagon CPU version
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
Stefan Hajnoczi [Sat, 25 Apr 2026 14:20:29 +0000 (10:20 -0400)]
Merge tag 'migration-20260423-pull-request' of https://gitlab.com/farosas/qemu into staging
Migration pull request
- Cleanups to internal vmstate APIs
- Cleanups to handling of vmstate flags
- New vmstate VMS_ARRAY_OF_POINTER_AUTO_ALLOC
- Fixes to:
- functional exec test
- leaks in file migration
- mapped-ram migration input validation
- programming errors in qemu-file and multifd
- qtest leaks
- Additions to iochannel APIs:
qio_channel_pread{v,}_all{,_eof}
qio_channel_pwrite{v,}_all
- New migration qtest for capabilities validation
- Tweaks to documentation and checkpatch
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# gpg: Signature made Thu 23 Apr 2026 14:53:51 EDT
# gpg: using RSA key AA1B48B0A22326A5A4C364CFC798DC741BEC319D
# gpg: issuer "farosas@suse.de"
# gpg: Good signature from "Fabiano Rosas <farosas@suse.de>" [unknown]
# gpg: aka "Fabiano Almeida Rosas <fabiano.rosas@suse.com>" [unknown]
# gpg: WARNING: The key's User ID is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: AA1B 48B0 A223 26A5 A4C3 64CF C798 DC74 1BEC 319D
* tag 'migration-20260423-pull-request' of https://gitlab.com/farosas/qemu: (43 commits)
migration/qemu-file: drop incorrect const from qemu_get_buffer_at buf
migration/file: switch file_write_ramblock_iov to pwritev_all
migration/qemu-file: switch buffer_at functions to positioned I/O _all helpers
tests/qtest/migration: fix fd leak in ufd_version_check
tests/unit: add pread/pwrite _all tests for io channel file
migration/file: fix type mismatch and NULL deref in multifd_file_recv_data
io/channel: introduce qio_channel_pwrite{v,}_all()
io/channel: introduce qio_channel_pread{v, }_all{, _eof}()
migration: validate page_size in mapped-ram header before use
tests/unit/test-vmstate: add tests for VMS_ARRAY_OF_POINTER_AUTO_ALLOC
vmstate: Stop checking size for nullptr compression
vmstate: Implement VMS_ARRAY_OF_POINTER_AUTO_ALLOC
vmstate: Implement load of ptr marker in vmstate core
vmstate: Allow vmstate_info_nullptr to emit non-NULL markers
vmstate: Introduce vmstate_save_field_with_vmdesc()
vmstate: Rename VMS_NULLPTR_MARKER to VMS_MARKER_PTR_NULL
vmstate: Update max_elems early and check field compressable once
vmstate: Do not set size for VMS_ARRAY_OF_POINTER
vmstate: Pass in struct itself for VMSTATE_VARRAY_OF_POINTER_UINT32
vmstate: Pass in struct itself for VMSTATE_ARRAY_OF_POINTER
...
Signed-off-by: Stefan Hajnoczi <stefanha@redhat.com>
contrib/plugins/uftrace_symbols.py: handle missing source line from addr2line
Some symbols have only a file information, and no line information. In
this case, addr2line reports '?'. Replace with 0 to guarantee consistent
data for consumers.
linux-user: Use abi_int for imr_ifindex in ip_mreqn struct
Peter Hartley noticed, that in the qemu code the imr_ifindex member of
struct target_ip_mreq needs to be of type "int" instead of "long", which
is what the Linux kernel uses on all architectures.
Adjust the type accordingly, and add a QEMU_BUILD_BUG_ON() checker to
prevent such issues in the future.
This change should fix multicast issues when using hosts and guests with
different endianess or bit size.
Reported-by: Peter Hartley <peter@talesfromthearmchair.net>
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/2553 Signed-off-by: Helge Deller <deller@gmx.de>
linux-user: Fix CLONE_PARENT_SETTID when using fork-like clone
The CLONE_PARENT_SETTID option requires the implementation to store the
child thread ID at the location pointed to by parent_tid in the parent's
memory.
Fix our implementation and move the code from the client side (where
fork returned 0), to the parent side and store the return value from the
fork call (which is the client TID) in the parent_tid pointer.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3340 Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
James Hilliard [Fri, 10 Apr 2026 02:00:12 +0000 (20:00 -0600)]
linux-user/mips: sync k0 TLS for EF_MIPS_MACH_OCTEON userlands
Cavium Octeon userspace is not following a generic MIPS Linux TLS
ABI rule here. Older Octeon glibc uses the k0 register as the fast
thread pointer, while newer Octeon2 and Octeon3 glibc variants use
the normal rdhwr $29 path.
linux-user already updates CP0_UserLocal for cpu_set_tls() and
TARGET_NR_set_thread_area, but it does not keep gpr[26]
synchronized. That leaves EF_MIPS_MACH_OCTEON userlands able to
complete set_thread_area() and still reach pthread startup or
pthread_self() with a stale k0 value.
Use the existing MIPS ELF machine flags from linux-user/elfload.c and
mirror CP0_UserLocal into gpr[26] only for EF_MIPS_MACH_OCTEON.
Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Signed-off-by: Helge Deller <deller@gmx.de>
linux-user/arm/nwfpe: Replace user_registers with current_cpu
Use the thread-local variable current_cpu instead of
a global variable to access the general registers.
This also means we don't need to pass env to EmulateAll.
Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Signed-off-by: Helge Deller <deller@gmx.de>
linux-user: Don't define target_stat64 struct for loongarch64
The kernel defines 'struct stat64' only if
__BITS_PER_LONG != 64 || defined(__ARCH_WANT_STAT64).
loongarch64 doesn't set __ARCH_WANT_STAT64, and it isn't 32-bit,
so it won't get this struct.
QEMU incorrectly does define a target_stat64 struct. However this
isn't causing any guest-visible problems, because defining the
target_stat64 struct and TARGET_HAS_STRUCT_STAT64 affects these
syscalls:
TARGET_NR_stat64
TARGET_NR_lstat64
TARGET_NR_fstat64
TARGET_NR_fstatat64
TARGET_NR_newfstatat
For loongarch64 the only one of those we provide is newfstatat,
and that is actually a separate QEMU bug, because the kernel does
not provide that syscall for this architecture. No real guest
code will be using a syscall that doesn't exist in the ABI.
(Some of these syscalls are present in the loongarch64 "ABI1.0",
but that ABI was never accepted in the upstream kernel, and
QEMU does not model that ABI, only the "ABI2.0".)
Stop defining TARGET_HAS_STRUCT_STAT64 anyway, for consistency
with the kernel and to avoid confusion.
Note:
Commit message suggested by Peter Maydell <peter.maydell@linaro.org>
linux-user: fix off-by-one in host_to_target_for_each_rtattr()
host_to_target_for_each_rtattr() uses "len > sizeof(struct rtattr)"
as its loop condition. When the last rtattr in a netlink message has
exactly sizeof(struct rtattr) (4) bytes remaining, the loop exits
without byte-swapping its rta_len and rta_type. A big-endian guest
then reads rta_len in the wrong byte order and fails validation.
The companion function target_to_host_for_each_rtattr() correctly
uses ">=" (added in commit fa2229dbf8). The kernel's RTA_OK macro
also uses ">=". Fix the host_to_target direction to match.
The kernel's 64-bit signal delivery (signal_64.c) uses:
newsp = frame - __SIGNAL_FRAMESIZE
while the 32-bit path (signal_32.c) uses:
newsp = frame - (__SIGNAL_FRAMESIZE + 16)
The extra 16 bytes in the 32-bit case is to place siginfo and ucontext
at the same offsets as older kernels (see the comment in signal_32.c).
The 64-bit rt_sigframe starts with ucontext directly and does not need
this adjustment.
QEMU's setup_rt_frame() unconditionally used (SIGNAL_FRAMESIZE + 16)
for both 32-bit and 64-bit, placing the handler's SP 16 bytes too low
on ppc64. Signal delivery and return still worked because do_rt_sigreturn
had the matching wrong offset, but the vDSO DWARF unwind info encodes
the correct kernel offset. This caused any DWARF unwinder (libunwind,
libgcc, etc.) to compute a CFA that is 16 bytes off, reading garbage
register values from the signal frame.
Define RT_SIGFRAME_ADJUST (0 on ppc64, 16 on ppc32) and use it in both
setup_rt_frame and do_rt_sigreturn to match the kernel.
This was verified by A/B testing with libunwind's test suite:
ppc64le: Gtest-bt, Ltest-bt, Gtest-concurrent, Ltest-concurrent,
and Ltest-sig-context all change from FAIL to PASS.
ppc64be: Gtest-bt, Ltest-bt, and Ltest-sig-context all change
from FAIL to PASS.
Signed-off-by: Matt Turner <mattst88@gmail.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Helge Deller <deller@gmx.de> Cc: qemu-stable@nongnu.org
MAINTAINERS: Add myself as maintainer for linux-user
I'd like to step up as maintainer for linux-user. I'm actively using
linux-user to emulate a HP-PARISC (hppa) linux environment on my debian
buildd servers, so I'm very much interested that linux-user is running
good and stable.
Signed-off-by: Helge Deller <deller@gmx.de> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Pierrick Bouvier <pierrick.bouvier@oss.qualcomm.com> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Maintain the Boston board as just another MIPS board.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20260422080406.62638-4-philmd@linaro.org>
I'm not following this code anymore, no need
to be listed as reviewer.
My gratitude to Stefan for everything he taught me while
supervising this topic. I truly appreciate the time he spent
helping me in many occasions. Thank you very much Stefan!
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Hajnoczi <stefanha@redhat.com>
Message-Id: <20260422080406.62638-8-philmd@linaro.org>
With retrospective, mentioning email in authorship wasn't
really useful, more now than these addresses are dead:
- f4bug@amsat.org
- philmd@redhat.com
Simply remove them.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Acked-by: Michael S. Tsirkin <mst@redhat.com>
Message-Id: <20260422080406.62638-3-philmd@linaro.org>
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com>
Message-Id: <20260422080406.62638-2-philmd@linaro.org>
MAINTAINERS: Cover hexloader tests under the Generic Loader section
Drop the orphan 'Intel Hexadecimal Object File Loader' section
but keep the tests covered under the Generic Loader section, since
both loader.c and generic-loader.c calls load_targphys_hex_as().
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260422080406.62638-7-philmd@linaro.org>
SPDM depends on PCIe DOE, so it makes sense to cover
these files there. Cover the spdm.rst document. Add
Tao Tang who volunteered to be designated reviewer:
https://lore.kernel.org/qemu-devel/44abaece-6a6f-43c6-b29a-53d6eb08033c@phytium.com.cn/
Cc: Tao Tang <tangtao1634@phytium.com.cn> Cc: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Gustavo Romero <gustavo.romero@linaro.org> Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20260422080406.62638-6-philmd@linaro.org>
Jamin Lin [Thu, 23 Apr 2026 05:18:14 +0000 (07:18 +0200)]
hw/usb/hcd-ehci: Introduce common properties macro for sysbus and pci
EHCI properties are currently defined separately in both sysbus and
PCI implementations, leading to duplicated code for common fields
such as "maxframes".
Introduce DEFINE_EHCI_COMMON_PROPERTIES() to consolidate shared
property definitions and reuse them across both EHCISysBusState
and EHCIPCIState.
This reduces code duplication and keeps property definitions
consistent between different EHCI device variants.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260424080508.53992-8-jamin_lin@aspeedtech.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Jamin Lin [Thu, 23 Apr 2026 05:18:13 +0000 (07:18 +0200)]
hw/usb/hcd-ehci: Replace DPRINTF debug logs with trace events
Replace legacy DPRINTF() debug logging in the EHCI host controller
implementation with QEMU trace events.
The EHCI_DEBUG macro and associated DPRINTF() definitions are
removed as they are no longer needed.
Trace events are added for:
- packet submission and completion
- queue head execution state
- periodic schedule advancement
- ITD error conditions
- port state handling
- skipped microframes
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260424080508.53992-7-jamin_lin@aspeedtech.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Jamin Lin [Thu, 23 Apr 2026 05:18:11 +0000 (07:18 +0200)]
hw/usb/hcd-ehci.c: Replace fprintf(stderr, ...) with qemu_log_mask(LOG_GUEST_ERROR)
Replace direct fprintf(stderr, ...) calls with qemu_log_mask()
using LOG_GUEST_ERROR in the EHCI controller implementation.
Direct writes to stderr are discouraged in QEMU as they bypass
the logging framework and cannot be filtered or controlled at
runtime. Using qemu_log_mask() ensures that guest-visible errors
are properly categorized and can be managed via QEMU logging
options.
All affected messages correspond to guest-triggerable error
conditions, so LOG_GUEST_ERROR is used consistently.
This change improves integration with QEMU's logging infrastructure
and aligns with upstream coding guidelines.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-ID: <20260424080508.53992-6-jamin_lin@aspeedtech.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Jamin Lin [Wed, 11 Mar 2026 07:26:18 +0000 (08:26 +0100)]
hw/usb/hcd-ehci.c: Fix coding style issues reported by checkpatch
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260424080508.53992-5-jamin_lin@aspeedtech.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Jamin Lin [Wed, 11 Mar 2026 07:26:17 +0000 (08:26 +0100)]
hw/usb/hcd-ehci.h: Fix coding style issues reported by checkpatch
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260424080508.53992-4-jamin_lin@aspeedtech.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Jamin Lin [Fri, 24 Apr 2026 08:05:12 +0000 (08:05 +0000)]
hw/usb/hcd-ehci: Remove unused EHCIfstn structure and dead code
The EHCIfstn structure, defined according to EHCI spec section 3.7,
is currently unused in the EHCI implementation. Remove it to reduce
unused code and improve maintainability.
Additionally, drop a block of disabled (#if 0) code in
ehci_state_advqueue() that was never implemented. This code path
is incomplete and has no functional impact.
No functional change.
Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com> Reviewed-by: Cédric Le Goater <clg@redhat.com>
Message-ID: <20260424080508.53992-3-jamin_lin@aspeedtech.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/arm/virt: Do not select Kconfig symbol PCI_EXPRESS
The PCIe bus is not provided by the Virt machine but by
its GPEX host bridge (selected via PCI_EXPRESS_GENERIC_BRIDGE).
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260423170229.64655-4-philmd@linaro.org>
Add a stub for cxl_fmws_get_all_sorted() to fix building
a QEMU configured with the '--without-default-devices' option:
Undefined symbols for architecture arm64:
"_cxl_fmws_get_all_sorted", referenced from:
_cxl_build_cedt in hw_acpi_cxl.c.o
Note, the CXL <-> ACPI Kconfig relationship is a bit convoluted.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20260423170229.64655-3-philmd@linaro.org>
Looking at the history of the code, the abort() here has likely just
been forgotten when the register handler had been implemented (it used
to be a reminder about unimplemented functionality initially):
Set the valid max access size to 1 to fix the problem.
Resolves: https://gitlab.com/qemu-project/qemu/-/work_items/3393 Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260421082935.85995-1-thuth@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Peter Maydell [Fri, 17 Apr 2026 09:38:05 +0000 (10:38 +0100)]
hw/arm, hw/ppc: Remove unnecessary audio.h includes from board code
Some boards (mostly arm, but also ppc/prep) include audio.h, but they
don't need anything from it. Drop the unnecessary include lines.
These seem to have been introduced with commits 2b16397264a8e, b8ab0303de, which added the machine-default audiodev handling, but as
far as I can tell they were unecessary right from the start, as the
machine_add_audiodev_property() function has always been in boards.h.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org>
Message-ID: <20260417093805.1076954-1-peter.maydell@linaro.org> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Junjie Cao [Tue, 14 Apr 2026 21:35:23 +0000 (05:35 +0800)]
ati-vga: mask out lock bit from CUR_OFFSET in cursor offset calculation
Bit 31 of CUR_OFFSET is the cursor lock bit, not part of the actual
cursor address (bits 26:4). Although the callers already check for the
lock bit and return early, mask it out with 0x07fffff0 when computing
the cursor source offset so the calculation only uses the address bits.
Suggested-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Junjie Cao <junjie.cao@intel.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
Message-ID: <20260414213523.1125859-2-junjie.cao@intel.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Junjie Cao [Tue, 14 Apr 2026 14:14:58 +0000 (22:14 +0800)]
ati-vga: fix unsigned integer overflow in cursor bounds checks
The cursor bounds checks compare (srcoff + N) against vram_size, but
both sides are uint32_t so the addition can wrap past UINT32_MAX when
srcoff underflows from the cur_hv_offs subtraction, causing the check
to be bypassed.
Rewrite the checks as (srcoff > vram_size - N) to avoid the
overflow-prone addition, matching the style already used in
ati_mm_read() and ati_mm_write().
Cc: qemu-stable@nongnu.org Fixes: 2f1fbe6ee9b5 ("ati-vga: Make sure hardware cursor data is within vram") Signed-off-by: Junjie Cao <junjie.cao@intel.com>
Message-ID: <20260414141458.1076014-1-junjie.cao@intel.com> Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Vivien LEGER [Sat, 11 Apr 2026 15:45:35 +0000 (17:45 +0200)]
hw/ppc/e500: fix bus-frequency property hardcoded to zero in CPU FDT node
The bus-frequency property in the CPU FDT node was hardcoded to 0.
This is incorrect - it should reflect the actual platform bus clock
frequency, as firmware and RTOSes use it to derive peripheral clock
rates.
Notably, the RTEMS QorIQ BSP uses bus-frequency to program the MPIC
global timer interval. With bus-frequency=0, the timer interval
overflows to ~85 seconds, preventing any clock interrupts from firing.
Fix by adding a bus_freq field to PPCE500MachineClass and using it in
the FDT generator. Set bus_freq = PLATFORM_CLK_FREQ_HZ (400MHz) for
existing machines, matching the existing clock_freq value.
Signed-off-by: Vivien LEGER <vivien.leger@gmail.com> Reviewed-by: Bernhard Beschow <shentey@gmail.com>
Message-ID: <20260411154535.1451361-1-vivien.leger@gmail.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/arm/smmuv3: Avoid including CONFIG_DEVICES in hw/ header
By turning the inline functions into stubs we can avoid the
use of target-specific CONFIG_DEVICES include in a hw/ header,
allowing to build the source files including it as common objects.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Shameer Kolothum <skolothumtho@nvidia.com>
Message-Id: <20260410200031.18572-3-philmd@linaro.org>
hw/arm/smmuv3: Have smmuv3_accel_init() take an Error* parameter
By giving smmuv3_accel_init() the ability to populate an error,
we can fail early in smmu_realize() when CONFIG_ARM_SMMUV3_ACCEL
is not available, simplifying smmu_validate_property().
Bin Guo [Wed, 1 Apr 2026 10:00:05 +0000 (18:00 +0800)]
physmem: Simplify dirty memory type checks with loop
In physical_memory_range_includes_clean(), we have three nearly identical
if-statements checking different DIRTY_MEMORY types (VGA, CODE, MIGRATION).
This code duplication makes maintenance harder and increases the risk of
inconsistencies when adding new dirty memory types.
Replace the repetitive checks with a simple loop that iterates through
all DIRTY_MEMORY_NUM types, checking only those specified in the mask.
This reduces code size and makes it easier to add new dirty memory types
in the future.
Signed-off-by: Bin Guo <guobin@linux.alibaba.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260401100005.20651-1-guobin@linux.alibaba.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
hw/acpi/tpm: parameterize PPI base address in tpm_build_ppi_acpi
Add a ppi_base parameter to tpm_build_ppi_acpi() instead of
hardcoding TPM_PPI_ADDR_BASE. This prepares for ARM64 support where
PPI memory is dynamically allocated by the platform bus and the
address is not known at compile time.
Update the x86 callers (ISA TIS and CRB) to pass TPM_PPI_ADDR_BASE
explicitly. No behavioral change.
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Message-ID: <20260327173209.148180-3-mbawa@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
docs/specs/tpm: document PPI support on ARM64 virt
Document that tpm-tis-device on the ARM virt machine supports PPI
with dynamically allocated MMIO via the platform bus, unlike x86
where PPI is at the fixed address 0xFED45000.
Also add hw/arm/virt-acpi-build.c and hw/acpi/tpm.c to the list
of files related to TPM ACPI tables.
Reviewed-by: Stefan Berger <stefanb@linux.ibm.com> Signed-off-by: Mohammadfaiz Bawa <mbawa@redhat.com>
Message-ID: <20260327173209.148180-2-mbawa@redhat.com> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
qom: Restrict compat properties API to system emulation
Move compat properties API definitions to their own file
unit, compile it only when system emulation is configured.
Add a pair of stubs for user emulation.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20260325151728.45378-6-philmd@linaro.org>
qom: Declare compat properties API in 'qom/compat-properties.h'
While most of QEMU files use the QOM concept, few of them
use the compatibility properties API (mostly use in system
emulation). Move its prototype to a new "qom/compat-properties.h"
header, keeping "qom/object.h" for generic QOM.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20260325151728.45378-5-philmd@linaro.org>
qom: Declare GlobalProperty structure in 'qom/compat-properties.h'
While GlobalProperty is expected to only be used by QDev board
layer, it is used by the lower QOM API, so define it in the
qom/ namespace. This helps to build binary which use QOM but
don't need the QDev layer.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20260325151728.45378-4-philmd@linaro.org>
hw/core: Move compat_props_add() to 'hw/core/boards.h'
compat_props_add() is only used by board models, no need
to expose it to any device model. Restrict by defining it
only in "hw/core/boards.h".
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Michael Tokarev <mjt@tls.msk.ru>
Message-Id: <20260325151728.45378-3-philmd@linaro.org>
Prefer the address_space_ld/st API over the legacy ld/st_phys()
because it allow checking for bus access fault, which shouldn't
happen here.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Acked-by: Maciej S. Szmigiero <maciej.szmigiero@oracle.com>
Message-ID: <20260319082954.65069-1-philmd@linaro.org>
The 32-bit binary doesn't use these helpers, so don't need to
compile them. Rather than using 64-bit target #ifdef'ry in a
global header, un-inline the calls since the helpers are called
from I/O (cold) path.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Harsh Prateek Bora <harshpb@linux.ibm.com> Reviewed-by: Chinmay Rath <rathc@linux.ibm.com> Acked-by: Glenn Miles <milesg@linux.ibm.com>
Message-Id: <20260319111936.68041-2-philmd@linaro.org>
TPM instances don't expose any "ppi" property anymore,
remove that dead code.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-Id: <20260317120241.16320-6-philmd@linaro.org>
hw/tpm: Propagate @ppi_enabled to tpm_tis_reset() and remove in TPMState
Of the TPM devices using FIFO mode, only the ISA variant has
PPI, and calls tpm_ppi_init() to initialize the PPI state.
Propagate @ppi_enabled to tpm_tis_reset() so it only resets
the PPI part when requested (ISA case) otherwise the PPI is in
uninitialized state. Remove the now unused TPMState::ppi_enabled
field. Set the generic TPMIfClass::ppi_enabled so ACPI subsystem
can keep checking its availability.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-Id: <20260317120241.16320-5-philmd@linaro.org>
The CRBState::ppi_enabled boolean was only set in the
hw_compat_3_1[] array, via the 'ppi=false' property.
We removed all machines using that array, and the array
itself in commit a861ffef237 ("hw/core/machine: Remove
the hw_compat_3_1[] array"). We can safely remove the
now unused property. Since CRB devices always use PPI,
simplify removing the CRBState::ppi_enabled field.
Set the generic TPMIfClass::ppi_enabled so ACPI subsystem
can keep checking its availability.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-Id: <20260317120241.16320-4-philmd@linaro.org>
Each TPM derived device has a @ppi_enabled field, itself
exposed as a QOM property. External layers (like the ACPI
subsystem) wanting to know whether a device implements PPI
has to check for the QOM property available. This can be
simplified by declaring a single field in the TPM interface.
Here we add such field to TPMIfClass, before converting each
TPM devices to use it in the following commits.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-Id: <20260317120241.16320-3-philmd@linaro.org>
Factor out tpm_ppi_enabled() before modifying it in a unique place.
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org> Reviewed-by: Stefan Berger <stefanb@linux.ibm.com>
Message-Id: <20260317120241.16320-2-philmd@linaro.org>
projects / thirdparty / qemu.git / log
