Marek Vasut [Wed, 26 Jul 2023 23:58:07 +0000 (01:58 +0200)]
ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM
The DHCOM SoM has two options for supplying ETHRX clock to the DWMAC
block and PHY. Either (1) ETHCK_K generates 50 MHz clock on ETH_CLK
pad for the PHY and the same 50 MHz clock are fed back to ETHRX via
internal eth_clk_fb clock connection OR (2) ETH_CLK is not used at
all, MCO2 generates 50 MHz clock on MCO2 output pad for the PHY and
the same MCO2 clock are fed back into ETHRX via ETH_RX_CLK input pad
using external pad-to-pad connection.
Option (1) has two downsides. ETHCK_K is supplied directly from either
PLL3_Q or PLL4_P, hence the PLL output is limited to exactly 50 MHz and
since the same PLL output is also used to supply SDMMC blocks, the
performance of SD and eMMC access is affected. The second downside is
that using this option, the EMI of the SoM is higher.
Option (2) solves both of those problems, so implement it here. In this
case, the PLL4_P is no longer limited and can be operated faster, at
100 MHz, which improves SDMMC performance (read performance is improved
from ~41 MiB/s to ~57 MiB/s with dd if=/dev/mmcblk1 of=/dev/null bs=64M
count=1). The EMI interference also decreases.
Ported from Linux kernel commit 73ab99aad50cd ("ARM: dts: stm32: Switch DWMAC RMII clock to MCO2 on DHCOM")
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Thu, 6 Jul 2023 21:32:27 +0000 (23:32 +0200)]
ARM: stm32: Inhibit PDDS because CSTBYDIS is set
The PWR_MPUCR CSTBYDIS bit is set, therefore the CA cores can never
enter CStandby state and would always end up in CStop state. Clear
the PDDS bit, which indicates the CA cores can enter CStandby state
as it makes little sense to keep it set with CSTBYDIS also set.
This does however fix a problem too. When both PWR_MPUCR and PWR_MCUCR
PDDS bits are set, then the chip enters CStandby state even though the
PWR_MCUCR CSTBYDIS is set. Clearing the PWR_MPUCR PDDS prevents that
from happening.
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Patrick Delaunay [Fri, 23 Jun 2023 13:05:16 +0000 (15:05 +0200)]
clk: stm32mp1: remove error for disabled clock in stm32mp1_clk_get_parent
To disabled a clock in clock tree initialization for a mux of STM32MP15,
the selected clock source index is set with the latest possible index for
the number of bit used. Today this valid configuration cause a error
in U-Boot messages, for example with CLK_ETH_DISABLED, when this clock
is not needed for the used ETH PHY without crystal:
no parents defined for clk id 123
This patch change the level of this message to avoid this trace for
valid clock tree.
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Patrice Chotard <patrice.chotard@foss.st.com>
Marek Vasut [Wed, 17 May 2023 22:02:39 +0000 (00:02 +0200)]
ARM: stm32: Power cycle Buck3 in reset on DHSOM
In case the DHSOM is in suspend state and either reset button is pushed
or IWDG2 triggers a watchdog reset, then DRAM initialization could fail
as follows:
Avoid this failure by not keeping any Buck regulators enabled during reset,
let the SoC and DRAMs power cycle fully. Since the change which keeps Buck3
VDD enabled during reset is ST specific, move this addition to ST specific
SPL board initialization so that it wouldn't affect the DHSOM .
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Patrick Delaunay <patrick.delaunay@foss.st.com>
Tom Rini [Wed, 16 Aug 2023 01:49:34 +0000 (21:49 -0400)]
Merge branch '2023-08-15-add-SGMII-support-for-TI-j7200' into next
To quote the author:
This series adds support for SGMII mode to the CPSW driver to enable the
functionality on TI's J7200 SoC.
Supporting SGMII mode also requires changes to the WIZ driver which acts
as a wrapper for the SerDes used by the CPSW MAC to transmit data to the
Ethernet PHY daughtercard mounted on the I2C GPIO Expander 2 connector
on the J7200 EVM.
Powering on and resetting the Ethernet PHY requires MDIO support which
is added to the CPSW driver.
For supporting DMA transactions from the MAIN CPSW instance to the A72
Host on J7200 SoC, the corresponding PSI-L endpoint information is added
for the J721E SoC, which is applicable to J7200 SoC as well.
The SGMII daughtercard used for testing SGMII mode has TI's DP83869 PHY.
Thus, enable the config for DP83869 driver functionality. Also, enable
GPIO HOG config.
configs: j7200_evm_a72: Enable configs for SGMII support with MAIN CPSW0
The MAIN CPSW0 instance of CPSW Ethernet Switch on TI's J7200 SoC
supports SGMII mode. To enable support for utilizing the SGMII
daughtercard with TI's DP83869 PHY, enable the corresponding config.
Also, since the SGMII daughtercard is connected to the I2C GPIO
Expander 2 connector on the J7200 EVM, powering on the Ethernet PHY and
resetting it requires GPIO Hogging capability. Enable it as well.
Suman Anna [Wed, 2 Aug 2023 08:17:26 +0000 (13:47 +0530)]
net: ti: am65-cpsw-nuss: Add logic to support MDIO reset
Enhance the AM65 CPSW NUSS driver to perform a MDIO reset using a GPIO
line. Logic is also added to perform a pre and post delay around reset
using the optional 'reset-delay-us' and 'reset-post-delay-us' properties.
This is similar to the reset being performed in the Linux kernel. The
reset is done once when the CPSW MDIO bus is being initialized.
Signed-off-by: Suman Anna <s-anna@ti.com> Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Suman Anna [Wed, 2 Aug 2023 08:17:24 +0000 (13:47 +0530)]
dma: ti: Update J21E PSIL endpoint information for MAIN CPSW0
The PSIL endpoint data for J721E currently covers only the MCU domain
CPSW0 instance. Add the data for the MAIN domain CPSW0 as well to allow
the MAIN domain Ethernet ports to be usable on any platform using J721E
SoC.
Additionally, since J721E's PSIL endpoint data is applicable to J7200
SoC as well, the MAIN CPSW0 instance on J7200 will also be usable now.
Signed-off-by: Suman Anna <s-anna@ti.com>
[s-vadapalli@ti.com: Update commit message indicating support for J7200] Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com>
Tom Rini [Tue, 15 Aug 2023 17:08:17 +0000 (13:08 -0400)]
Merge tag 'efi-2023-10-rc3' of https://source.denx.de/u-boot/custodians/u-boot-efi
Pull request for efi-2023-10-rc3
Documentation:
* Correct description of board_get_usable_ram_top
* Add partition API to HTML documentation
* Describe lmb_is_reserved
* doc/sphinx/requirements.txt: Bump certifi up
UEFI:
* Fix efi_add_known_memory
* Make distro_efi_boot() static
board_get_usable_ram_top() returns a physical address that is stored in
gd->ram_top. The return type of the function should be phys_addr_t like the
current type of gd->ram_top.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
In efi_add_known_memory() we currently call board_get_usable_ram_top() with
an incorrect value 0 of parameter total_size. This leads to an incorrect
value for ram_top depending on the code in board_get_usable_ram_top().
Use the value of gd->ram_top instead which is set before relocation by
calling board_get_usable_ram_top().
Fixes: 7b78d6438a2b ("efi_loader: Reserve unaccessible memory") Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Bin Meng [Thu, 3 Aug 2023 09:30:05 +0000 (17:30 +0800)]
bootmeth: efi: Make distro_efi_boot() static
As it is only called in bootmeth_efi.c
Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Tom Rini [Tue, 15 Aug 2023 14:39:41 +0000 (10:39 -0400)]
Merge branch '2023-08-14-assorted-general-updates' into next
- Assorted PCI-related fixes, add Apple Type-C PHY support, semihosting
updates, fix a FAT corner-case, update the help on the pxe cmd and
clean up the gpio uclass slightly.
Sam Edwards [Tue, 25 Jul 2023 22:13:05 +0000 (16:13 -0600)]
i2c: mvtwsi: reset controller if stuck in "bus error" state
The MVTWSI controller can act either as a master or slave device. When
acting as a master, the FSM is driven by the CPU. As a slave, the FSM is
driven by the bus directly. In what is (apparently) a safety mechanism,
if the bus transitions our FSM in any improper way, the FSM goes to a
"bus error" state (0x00). I could find no documented or experimental way
to get the FSM out of this state, except for a controller reset.
Since U-Boot only uses the MVTWSI controller as a bus master, this
feature only gets in the way: we do not care what happened on the bus
previously as long as the bus is ready for a new transaction. So, when
trying to start a new transaction, check for this state and reset the
controller if necessary.
Note that this should not be confused with the "deblocking" technique
(used by the `i2c reset` command), which involves pulsing SCL repeatedly
if SDA is found to be held low, in an attempt to force the bus back to
an idle state. This patch only resets the controller in case something
else had previously upset it, and (in principle) results in no
externally-observable change in behavior.
Signed-off-by: Sam Edwards <CFSworks@gmail.com> Reviewed-by: Stefan Roese <sr@denx.de> Reviewed-by: Heiko Schocher <hs@denx.de>
Marek Vasut [Tue, 1 Aug 2023 23:26:02 +0000 (01:26 +0200)]
gpio: Use separate bitfield array to indicate GPIO is claimed
The current gpio-uclass design uses name field in struct gpio_dev_priv as
an indicator that GPIO is claimed by consumer. This overloads the function
of name field and does not work well for named pins not configured as GPIO
pins.
Introduce separate bitfield array as the claim indicator.
This unbreaks dual-purpose AF and GPIO operation on STM32MP since commit 2c38f7c31806 ("pinctrl: pinctrl_stm32: Populate uc_priv->name[] with pinmux node's name")
where any pin which has already been configured as AF could no longer be
claimed as dual-purpose GPIO. This is important for pins like STM32 MMCI
st,cmd-gpios .
Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Bin Meng [Mon, 31 Jul 2023 08:33:23 +0000 (16:33 +0800)]
cmd: pxe: Update the command help
Currently the "help" displays pxe command help text like this:
=> help
...
printenv - print environment variables
pxe - commands to get and boot from pxe files
To use IPv6 add -ipv6 parameter
qfw - QEMU firmware interface
...
This does not read clearly. Remove the IPv6 stuff as it is in
the detailed help text so that it fits just a single line.
Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Marek Vasut [Sun, 16 Jul 2023 15:53:24 +0000 (17:53 +0200)]
pci: Fix device_find_first_child() return value handling
This function only ever returns 0, but may not assign the second
parameter. Same thing for device_find_next_child(). Do not assign
ret to stop proliferation of this misuse.
Reported-by: Jonas Karlman <jonas@kwiboo.se> Signed-off-by: Marek Vasut <marex@denx.de> Reviewed-by: Simon Glass <sjg@chromium.org>
Mark Kettenis [Fri, 14 Jul 2023 19:15:16 +0000 (21:15 +0200)]
pci: apple: Enable CONFIG_SYS_PCI_64BIT
The Apple hardware supports 64-bit prefetchable memory windows so
enable CONFIG_SYS_PCI_64BIT. This fixes BAR assignments for the
Broadcom Ethernet controller used in some of the desktop machines.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org>
Tom Rini [Mon, 14 Aug 2023 13:14:51 +0000 (09:14 -0400)]
Merge branch '2023-08-14-keep-fixed-gpio-regulator-count-in-balance' into next
To quote the author:
The commit 4fcba5d556b4 ("regulator: implement basic reference counter")
have made it more important to keep fixed/gpio regulators enable/disable
state in balance.
This series fixes an inbalance in the mmc_dw driver and changes to use
the more relaxed regulator_set_enable_if_allowed function for a few
other drivers.
The regulator_set_enable_if_allowed function is more relaxed and will
return ENOSYS if the provided regulator is NULL or when DM_REGULATOR
was disabled. Using the following call convention should be safe:
ret = regulator_set_enable_if_allowed(<supply>, <true|false>);
if (ret && ret != -ENOSYS)
return ret;
Jonas Karlman [Wed, 19 Jul 2023 21:20:59 +0000 (21:20 +0000)]
mmc: Use regulator_set_enable_if_allowed
With the commit 4fcba5d556b4 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Tested-by: Svyatoslav Ryhel <clamor95@gmail.com> # P895 Tegra 3; Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399
Jonas Karlman [Wed, 19 Jul 2023 21:20:57 +0000 (21:20 +0000)]
usb: ehci-generic: Use regulator_set_enable_if_allowed
With the commit 4fcba5d556b4 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Marek Vasut <marex@denx.de>
Jonas Karlman [Wed, 19 Jul 2023 21:20:56 +0000 (21:20 +0000)]
usb: dwc2: Use regulator_set_enable_if_allowed
With the commit 4fcba5d556b4 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399 Reviewed-by: Marek Vasut <marex@denx.de>
Jonas Karlman [Wed, 19 Jul 2023 21:20:55 +0000 (21:20 +0000)]
adc: Use regulator_set_enable_if_allowed
With the commit 4fcba5d556b4 ("regulator: implement basic reference
counter") the return value of regulator_set_enable may be EALREADY or
EBUSY for fixed/gpio regulators.
Change to use the more relaxed regulator_set_enable_if_allowed to
continue if regulator already was enabled or disabled.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Tested-by: Simon Glass <sjg@chromium.org> # rockpro64-rk3399
Jonas Karlman [Mon, 14 Aug 2023 00:28:26 +0000 (00:28 +0000)]
pinctrl: rockchip: Fix drive and input schmitt on RK3568
On RK3568 most pins have a configurable drive strength of level 0-5 and
some pins level 0-11. When rk3568_set_drive is called with a strength
value above 7 the drv value written to reg may overflow into the write
enable bits, resulting in a bad configuration.
This cause e.g. ethernet PHY on Radxa CM3-IO board not to work after
drive is configured according to the device tree.
Level 6-11 can be configured using a second reg for some pins, however
the drv value is reused resulting in lower 6 bits being written to reg.
Input schmitt is configured in 2-bit fields on RK3568 compared to
earlier generation and 2'b10 should be used to enable input schmitt.
Change to use regmap_update_bits with a rmask to fix the overflow issue
and closer match the linux driver. Bit shift the drv value used for the
second reg to configure drive strength level 6-11. Also write correct
values for input schmitt setting.
Fixes: 1977d746aa54 ("rockchip: rk3568: add rk3568 pinctrl driver") Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Meng Li [Wed, 26 Jul 2023 02:42:35 +0000 (10:42 +0800)]
rpi: set the correct parameter for simple framebuffer node
When raspberrpi-4b platform boots up, there are 2 sets of same bootup
log displayed on HDMI monitor screen, it looks like the screen is split
into 2 parts. The root cause is that video format of u-boot is different
from kernel. The fixing "a8r8g8b8" video format is used in u-boot, but
"r5g6b5" video format from framebuffer node is used in kernel image. In
order to avoid weird display status on screen, it needs to set the correct
parameter for simple framebuffer node even if it has existed.
Jason Wessel [Wed, 26 Jul 2023 02:42:34 +0000 (10:42 +0800)]
bcm2835: Add simiple-framebuffer for use with fkms
When the fkms dtb overlay is used only the simple-framebuffer is
presented as a usable video display. So, add "simple-framebuffer"
compatible to enable video driver bcm2835.
Signed-off-by: Jason Wessel <jason.wessel@windriver.com> Signed-off-by: Meng Li <Meng.Li@windriver.com>
Bin Meng [Thu, 3 Aug 2023 09:32:41 +0000 (17:32 +0800)]
video: vidconsole: Fix null dereference of ops->measure
At present vidconsole_measure() tests ops->select_font before calling
ops->measure, which would result in a null dereference when the console
driver provides no ops for measure.
Fixes: b828ed7d7929 ("console: Allow measuring the bounding box of text") Signed-off-by: Bin Meng <bmeng@tinylab.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Hai Pham [Mon, 19 Jun 2023 22:43:18 +0000 (00:43 +0200)]
ARM: rmobile: Update little‐endian byte order option in srec_cat command
Since srecord v1.60, option "-Little_Endian_CONSTant" is deprecated.
Fix the build warnings by updating little‐endian byte order option in
srec_cat command when generating loader header.
Reviewed-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com> Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Marek Vasut [Sat, 25 Apr 2020 12:57:55 +0000 (14:57 +0200)]
clk: renesas: Tear clock controller down last before booting OS
Once all the other drivers got torn down in preparation for the OS
to start, tear down the clock controller last. The clock controller
must be torn down last as some of the clock which get turned off
might have still been needed during the teardown stage of the other
drivers.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org> Signed-off-by: Tam Nguyen <tam.nguyen.xa@renesas.com> Signed-off-by: Hai Pham <hai.pham.ud@renesas.com>
Massimo Pegorer [Thu, 3 Aug 2023 11:08:13 +0000 (13:08 +0200)]
dts: rockchip: rk3308: Avoid warning for serial probe on prereloc
Make device tree complete and consistent for pre relocation phase. Some
nodes are missing, causing warnings to be issued on serial port probing
during pre relocation phase (uclass_get_device_by_phandle_id fails when
called by pinctrl_select_state_full: none of these failures is fatal
nor causing issues). Add to *-u-boot.dtsi all required nodes with the
'bootph-some-ram' attribute.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Massimo Pegorer [Thu, 3 Aug 2023 11:08:12 +0000 (13:08 +0200)]
clk: rockchip: rk3308: Support reading UART rate and clock registers
Add support to read RK3308 registers used to configure UART clocks, and
thus to get UART rate and baudrate. This fixes clock_get_rate returning
error on serial device probing. Moreover, there is no need anymore to
use 'clock-frequency' property for UART nodes in *-u-boot.dtsi files
for all cases where UART is not inited by U-Boot proper or by SPL o by
TPL code but by a preliminary external boot phase (for Rock PI S, UART
is inited by external TPL).
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Massimo Pegorer [Thu, 3 Aug 2023 11:08:11 +0000 (13:08 +0200)]
clk: rockchip: rk3308: Fix ordering between masking and shifting
As per definitions of masks and shift offsets in cru_rk3308.h, values
read from registers must be first masked and then shifted. By the way,
this fix is binary invariant, because in all of fixed cases the shift
offset is zero.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Massimo Pegorer [Wed, 2 Aug 2023 17:05:24 +0000 (19:05 +0200)]
rockchip: spl: Drop out of scope debug message related to uart init
Debug uart is no more inited in board_init_f function: remove this
debug message from board_init_f. If an earliest-as-possible message
after debug uart initialization is needed, enable DEBUG_UART_ANNOUNCE
Kconfig option, instead.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Massimo Pegorer [Wed, 2 Aug 2023 17:05:23 +0000 (19:05 +0200)]
rockchip: spl: Drop useless call to debug_uart_init
Since commit 0dba45864b2a ("arm: Init the debug UART") function
debug_uart_init is called in crt files _main before calling
board_init_f. Therefore, there is no need to call it again
inside board_init_f implementation in arm/mach-rockchip/spl.c.
Signed-off-by: Massimo Pegorer <massimo.pegorer+oss@gmail.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 4 Aug 2023 09:34:01 +0000 (09:34 +0000)]
rockchip: rk356x-u-boot: Set max-frequency prop in sdhci node
Most board device trees for RK356x set max-frequency = <200000000> in
the sdhci node, some boards like Quartz64 do not. This result in an
error message due to sdhci driver trying to set a clock rate of 0
instead of the max-frequency value.
rockchip_sdhci_probe clk set rate fail!
Fix this by setting a common max-frequency in rk356x-u-boot.dtsi. A
patch to set default max-frequency of sdhci node in linux is planned.
Also remove the forced status = "okay" for the sdhci and sdmmc0 nodes,
boards already set correct state for these nodes.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Fri, 4 Aug 2023 09:34:00 +0000 (09:34 +0000)]
clk: rockchip: rk3568: Add dummy support for GMAC speed clocks
Pine64 Quartz64 boards DT reference SCLK_GMAC1_RGMII_SPEED in the
assigned-clocks property of the gmac1 node. This result in a ENOENT
error when driver core tries to set a parent for this clock.
The clock speed in rgmii/rmii mode is changed using clk_set_rate of the
tx_rx clock and not using clk_set_parent of the speed clock.
Add dummy support for SCLK_GMAC1_RGMII_SPEED and similar clocks to clk
driver to allow a driver for gmac node to probe.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
533ad9dc avoided an overflow but causes compilation
failure on 32bit boards (eg. veyron speedy)
this commit uses div_u64 which has a fallback codepath
for 32bit platforms
Signed-off-by: Alvaro Fernando García <alvarofernandogarcia@gmail.com> Tested-by: Simon Glass <sjg@chromium.org> # chromebook_jerry Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Jonas Karlman [Tue, 11 Jul 2023 23:13:56 +0000 (23:13 +0000)]
pci: rockchip: Release resources on failing probe
The PCIe driver for RK3399 is affected by a similar issue that was fixed
for RK35xx in the commit e04b67a7f4c1 ("pci: pcie_dw_rockchip: release
resources on failing probe").
Resources are not released on failing probe, e.g. regulators may be left
enabled and the ep-gpio may be left in a requested state.
Change to use regulator_set_enable_if_allowed and disable regulators
after failure to keep regulator enable count balanced, ep-gpio is also
released on regulator failure.
Also add support for the vpcie12v-supply, remove unused include and
check return value from dev_read_addr_name.
Signed-off-by: Jonas Karlman <jonas@kwiboo.se> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
rockchip: rk3399: remove duplicate call to regulators_enable_boot_on
An earlier commit makes the common SPL code call
regulators_enable_boot_on and regulators_enable_boot_off before
iterating over possible boot media for U-Boot proper. There is therefore
no need to do this in the rk3399-specific code, so let's remove it.
Simon Glass [Sun, 30 Jul 2023 17:17:02 +0000 (11:17 -0600)]
bootstd: cros: Add ARM support
Support booting ChromiumOS on ARM devices using FIT. Add an entry into the
boot implementation which does not require a command line. This can be
expanded over time as the bootm code is refactored.
Simon Glass [Fri, 11 Aug 2023 01:33:18 +0000 (19:33 -0600)]
bootstd: Add a command to read all files for a bootflow
Some bootflows (such as EFI and ChromiumOS) delay reading the kernel until
it is needed to boot. This saves time when scanning and avoids needing to
allocate memory for something that may never be used.
To permit reading of these files, add a new 'bootflow read' command.
Simon Glass [Sun, 30 Jul 2023 17:17:00 +0000 (11:17 -0600)]
bootstd: Allow display of the x86 setup information
Provide an option to dump this information if available.
Move the funciion prototype to the common x86 header. Allow the command
line to be left out since 'bootflow info' show this itself and it is
not in the correct place in memory until the kernel is actually booted.
Simon Glass [Sun, 30 Jul 2023 17:16:57 +0000 (11:16 -0600)]
bootstd: cros: Add a function to read info from partition
The code to read the ChromiumOS information from the partition is
currently all in one function. It reads the entire kernel, which is
unnecessary unless it is to be booted.
Create a new function which reads just the minimum required data from the
disk, then obtains what it needs from there.
For now this function is not used. Future work will plumb it in.
Simon Glass [Sun, 30 Jul 2023 17:16:56 +0000 (11:16 -0600)]
bootstd: Add private bootmeth data to the bootflow
Some bootmeths need to store their own information related to the
bootflow, in addition to the generic information in struct bootflow.
Add a pointer for this.
Simon Glass [Sun, 30 Jul 2023 17:16:55 +0000 (11:16 -0600)]
bootstd: cros: Add private info for ChromiumOS
Create a new private structure to hold information gleaned from the disk.
This will allow separation between reading of the bootflow information and
(later) reading the whole kernel.
Simon Glass [Sun, 30 Jul 2023 17:16:53 +0000 (11:16 -0600)]
bootstd: Move common zimage functions to bootm.h
We want to avoid using #ifdefs around header files and in the code. It
makes sense to collect the various functions used for loading images into
a single header which can be included by all architectures. The best place
for this is the arch-neutral bootm.h header, so use that.
Move some zimage functions into this bootm.h header.
Simon Glass [Sun, 30 Jul 2023 17:16:49 +0000 (11:16 -0600)]
bootstd: cros: Bring in some ChromiumOS structures
Add a header file with structures for booting ChromiumOS, taken from the
vboot tree. Using these makes it easier to understand the code.
Note that the code style has not been updated for U-Boot, with use of
uint64_t, __attribute__((packed)) and one comment-style nit. This should
make it easier to keep the code in sync. It was taken from commit:
+ Add USB host support on VisionFive2 board
+ Enable SPI flash support on VisionFive2 board
+ Enable Random Number Generator in RISC-V QEMU board
+ Display new SBI extension
+ Add SPL_ZERO_MEM_BEFORE_USE Kconfig for jh7110 L2 LIM
(Loosely-Integrated Memory)
Shengyu Qu [Wed, 9 Aug 2023 13:11:32 +0000 (21:11 +0800)]
riscv: Add SPL_ZERO_MEM_BEFORE_USE implementation
Add the actual support code for SPL_ZERO_MEM_BEFORE_USE and remove
existing Starfive JH7110's L2 LIM clean code, since existing code has
following issues:
1. Each hart (in the middle of a function call) overwriting its own
stack and other harts' stacks.
(data-race and data-corruption)
2. Lottery winner hart can be doing "board_init_f_init_reserve",
while other harts are in the middle of zeroing L2 LIM.
(data-race)
Signed-off-by: Bo Gan <ganboing@gmail.com> Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Shengyu Qu [Tue, 8 Aug 2023 13:14:36 +0000 (21:14 +0800)]
configs: starfive: Enable environment in SPI flash support
On Starfive Visionfive 2, the u-boot environment settings are saved to
on-board SPI flash. Enable relative configs by default and set offset
and size according to upstream linux dts.
Signed-off-by: Shengyu Qu <wiagn233@outlook.com> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
projects / thirdparty / u-boot.git / log
