Ye Li [Fri, 3 Feb 2023 10:24:36 +0000 (18:24 +0800)]
power: pmic: Add NXP PCA9451A PMIC support
PCA9451A uses similar BUCKs and LDO regulators as PCA9450B/C but
has LDO2 and LDO3 removed. So reuse pca9450 PMIC and regulator driver
and add new type for PCA9451A.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Marek Vasut <marex@denx.de>
Fabio Estevam [Wed, 15 Feb 2023 18:24:44 +0000 (15:24 -0300)]
pico-imx6: Pass the mmc alias to fix boot regression
Originally, the mmc aliases node was present in imx6qdl-pico.dtsi.
After the sync with Linux in commit d0399a46e7cd ("imx6dl/imx6qdl:
synchronise device trees with linux"), the aliases node is gone as
the upstream version does not have it.
This causes a boot regression in which the eMMC card cannot be found anymore.
Fix it by passing the alias node in the u-boot.dtsi file to
restore the original behaviour where the eMMC (esdhc3) was
mapped to mmc0.
Fixes: d0399a46e7cd ("imx6dl/imx6qdl: synchronise device trees with linux") Signed-off-by: Fabio Estevam <festevam@denx.de>
Ye Li [Tue, 31 Jan 2023 08:42:34 +0000 (16:42 +0800)]
imx8ulp_evk: Clear data at fdt_addr_r before booting kernel
When using dual boot mode, the DDR won't be reset when APD power off
or reboot. It has possibility that obsolete fdt data existing on
fdt_addr_r address. Then even nothing in EFI partitions, the distro boot
still continue to parse fdt and get uboot crashed.
Clear the data at fdt_addr_r, so the fdt header check in above case
will not pass.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Tue, 31 Jan 2023 08:42:33 +0000 (16:42 +0800)]
imx8ulp_evk: disable overflow of port0 for LPAV
Bit0: Port 0 behavior when bandwidth maximized. Set to 1 to allow overflow
With overflow set, we see some issue that A35 may not able to get enough
bandwidth and A35 will report hrtimer takes too much time, workqueue
lockup. With overflow cleared, the issues are gone.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:32 +0000 (16:42 +0800)]
imx8ulp_evk: Update DDR ports arbitration for DCNANO underrun
To resolve DCNANO underrun issue, change the DDR Port 0 arbitration
from round robin fashion to fixed priority level 1, while other ports
are not assigned any priority, so they will be serviced in round robin
fashion if there is no active request from Port 0.
Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:28 +0000 (16:42 +0800)]
misc: fuse: Lock 8ULP ECC-protected fuse when programming
The ECC fuse on 8ULP can't be written twice. If any user did it, the
ECC value would be wrong then cause accessing problem to the fuse.
The patch will lock the ECC fuse word to avoid this problem.
For iMX9, the OTP controller automatically prevents an ECC fuse word to
be written twice. So it does not need the setting.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:27 +0000 (16:42 +0800)]
misc: fuse: Update fuse mapping for 8ULP S400 API
Since new 8ULP A1 S400 FW (v0.0.8-e329b760) can support to read
more fuses: like PMU trim, Test flow/USB, GP1-5, GP8-10. Update
the u-boot driver for the new mapping.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Alice Guo <alice.guo@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:26 +0000 (16:42 +0800)]
imx: sentinel: Update S400 API get info message structure
From Sentinel FW v0.0.9-9df0f503, the response message of get info API
is changed to add OEM SRK and some states (IMEM, CSAL, TRNG).
With old structure, we get failure from sentinel due to the buffer
size can't fit with new response message. So update the API structure
to fix the issue.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:24 +0000 (16:42 +0800)]
imx: imx8ulp: Configure XRDC PDAC and MSC for DBD owner=S400 only
This patch is used to support DBD owner fuse changed to S400 only.
The XRDC PDAC2 for LPAV pbridge5 and MSC1/2/3 for GPIO and LPAV are not
configured by S400 default setting. So these PDAC and MSC are invalid,
only DBD owner can access the corresponding resources.
We have to configure necessary PDAC and MSC for SPL before DDR
initialization.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Peng Fan [Tue, 31 Jan 2023 08:42:22 +0000 (16:42 +0800)]
imx: imx8ulp: upower: replace magic number with macro
The swton indicates the logic switch, magic number 0xfff80 is hard
to understand, so use macro.
Some board design may not have MIPI_CSI voltage input connected per
data sheet. In that case, the upower power on API may dead loop mu to wait
response, however there is no response. So remove MIPI_CSI here, let
linux power domain driver to runtime enable the power domain.
Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:21 +0000 (16:42 +0800)]
imx: imx8ulp: Clear dividers in PLL3DIV_PFD registers
At present, in cgc1_pll3_init we don't set the pll3pfd div values,
just use the default 0. But on A1 part, ROM will set PLL3 pfd1div2
to 1 and pfd2div1 to 3.
This finally causes some clocks' rate decreased, for example USDHC.
So clear the PLL3DIV_PFD dividers to get correct rate.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:20 +0000 (16:42 +0800)]
imx: imx8ulp: Reconfigure MRC3 for SRAM0 access
Some space in SRAM0 will be protected by S400 to allow RX SecPriv mode
access only for boot purpose. Since SW will reuse the SRAM0 as SCMI
buffer and SPL container loading buffer, need to reconfigure MRC3.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:19 +0000 (16:42 +0800)]
ddr: imx8ulp: Change DRAM timing save area to 0x20055000
To align with ARM trusted firmware's change, adjust DRAM timing
save area to new position 0x20055000. So we can release the space
since 0x2006c000 for the NOBITS region of ARM trusted firmware
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:17 +0000 (16:42 +0800)]
imx: imx8ulp: Adjust handshake to sync TRDC and XRDC completion
To fit the DBD_EN fused part, we re-design the TRDC and XRDC assignment.
M33 will be the TRDC owner and needs to configure TRDC. A35 is the
XRDC owner, ATF will configure XRDC.
The handshake between U-boot and M33 image is used to sync TRDC and
XRDC configuration completion. Once the handshake is done, A35 and M33
can access the allowed resources in others domain.
The handshake is needed when M33 is booted or DBD_EN fused, because both
cases will enable the TRDC. If handshake is timeout, the boot will hang.
We use SIM GPR0 to pass the info from SPL to u-boot, because before the
handshake, u-boot can't access SEC SIM and FSB.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:16 +0000 (16:42 +0800)]
imx: imx8ulp: Remove the TRDC configure from A35
As M33 is responsible for TRDC configuration, the settings for A35
nonsecure world access and DMA0 access are moved to M33 image.
So remove the codes to release TRDC and configure it. Just keep
the configurations for reference.
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:13 +0000 (16:42 +0800)]
imx: imx8ulp: Get chip revision from Sentinel
In both SPL and u-boot, after probing the S400 MU, get the chip revision,
lifecycle and UID from Sentinel.
Update get_cpu_rev to use the chip revision not hard coded it for A0
Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Tue, 31 Jan 2023 08:42:12 +0000 (16:42 +0800)]
imx: imx8ulp: Fix MU device probe failure
Since latest DTS has added multiple MU nodes, using compatible
string to find the device node is not proper. It finds the first
node with the compatible string matched even the node is disabled.
Bryan Brattlof [Fri, 17 Mar 2023 23:37:11 +0000 (18:37 -0500)]
configs: am62ax: enable secure device configs by default
TI's security enforcing SoCs will authenticate each binary it loads by
comparing it's signature with keys etched into the SoC during the boot
up process. The am62ax family of SoCs by default will have some level of
security enforcement checking. To keep things as simple as possible,
enable the CONFIG_TI_SECURE_DEVICE options by default so all levels of
secure SoCs will work out of the box
include: environment: ti: Use .env for environment variables
Add K3 common environment variables to .env. We retain the old-style C
environment .h files to maintain compatibility with other K3 boards that
have not moved to using .env yet.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com> Reviewed-by: Tom Rini <trini@konsulko.com>
Janne Grunau [Mon, 13 Mar 2023 13:54:32 +0000 (14:54 +0100)]
apple_m1_defconfig: Bump CONFIG_LMB_MAX_REGIONS to 64
Apple silicon SoCs have numerous embedded co-processors with pre-loaded
firmware. The co-processors text and data sections need to be mapped via
DART iommus controlled by the main processor. Those sections are
exported as reserved-memory. Bump CONFIG_LMB_MAX_REGIONS from 8 to 64 to
deal with the large amount of reserved-memory regions.
Signed-off-by: Janne Grunau <j@jannau.net> Reviewed-by: Mark Kettenis <kettenis@openbsd.org>
Sinthu Raja [Mon, 13 Mar 2023 12:42:24 +0000 (18:12 +0530)]
phy: ti: j721e-wiz: Add support to enable LN23 Type-C swap
The WIZ acts as a wrapper for SerDes and has Lanes 0 and 2 reserved
for USB for type-C lane swap if Lane 1 and Lane 3 are linked to the
USB PHY that is integrated into the SerDes IP. The WIZ control register
has to be configured to support this lane swap feature.
The support for swapping lanes 2 and 3 is missing and therefore
add support to configure the control register to swap between
lanes 2 and 3 if PHY type is USB.
Sinthu Raja [Mon, 13 Mar 2023 12:42:23 +0000 (18:12 +0530)]
phy: ti: j721e-wiz: Manage TypeC lane swap if typec-dir-gpios not specified
It's possible that the Type-C plug orientation on the DIR line will be
implemented through hardware design. In that situation, there won't be
an external GPIO line available, but the driver still needs to address
this since the DT won't use the typec-dir-gpios property.
Add code to handle LN10 Type-C swap if typec-dir-gpios property is not
specified in DT.
Kconfig does not support using 'select' to select a 'choice'. A choice
can be configured by either setting the choice symbol to 'y' in a
configuration file or by setting a 'default' of the choice.
In board/ti/*/Kconfig the SOC_K3_* choice is already set to 'y' in their
corresponding configs/*_defconfig file. So remove selecting it.
Signed-off-by: Neha Malcom Francis <n-francis@ti.com>
Jan Kiszka [Tue, 28 Feb 2023 18:19:23 +0000 (19:19 +0100)]
iot2050: Add support for configuring M.2 connector
The M.2 slots of the related IOT2050 variant need to be configured
according to the plugged cards. This tries to detect the card using the
M.2 configuration pins of the B-key slot. If that fails, a U-Boot
environment variable can be set to configure manually. This variable is
write-permitted also in secure boot mode as it is not able to undermine
the integrity of the booted system.
The configuration is then applied to mux the serdes and to fix up the
device tree passed to or loaded by the bootloader. The fix-ups are
coming from device tree overlays that are embedded into the firmware
image and there also integrity protected. The OS remains free to load
a device tree to which they do not apply: U-Boot will not fail to boot
in that case.
Based on original patch by Chao Zeng.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
chao zeng [Tue, 28 Feb 2023 18:19:22 +0000 (19:19 +0100)]
arm: dts: iot2050: Add support for M.2 variant
Add support for the M.2 board based on the iot2050 advanced board.
The board has two m.2 connectors, one is B-keyed, the other E-keyed.
The B-key slot can connect 5G/SSD devices, and E-key can be used for
WIFI/BT devices.
This variant is covered by PG2 firmware image.
Signed-off-by: chao zeng <chao.zeng@siemens.com>
[Jan: align DT to kernel, polish wording] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 28 Feb 2023 18:19:18 +0000 (19:19 +0100)]
arm: dts: iot2050: Optionally embed OTP programming data into image
Use external blob otpcmd.bin to replace the 0xff filled OTP programming
command block to create a firmware image that provisions the OTP on
first boot. This otpcmd.bin is generated from the customer keys using
steps described in the meta-iot2050 integration layer for the device.
Based on original patch by Baocheng Su.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 28 Feb 2023 18:19:17 +0000 (19:19 +0100)]
iot2050: Add script for signing artifacts
There are many ways to get a signed firmware for the IOT2050 devices,
namely for the parts under user-control. This script documents one way
of doing it, given a signing key. Augment the board documentation with
the required procedure around it.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 28 Feb 2023 18:19:16 +0000 (19:19 +0100)]
tools: Add script for converting public key into device tree include
Allows to create a public key device tree dtsi for inclusion into U-Boot
SPL and proper during first build already. This can be achieved via
CONFIG_DEVICE_TREE_INCLUDES.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 28 Feb 2023 18:19:14 +0000 (19:19 +0100)]
iot2050: Add CFG_ENV_FLAGS_LIST_STATIC
Will be needed when CONFIG_ENV_WRITEABLE_LIST is enabled. The listed
variables shall remain writable, for informational purposes - they have
to be considered untrusted because the persistent U-Boot env is not
protected.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 28 Feb 2023 18:19:13 +0000 (19:19 +0100)]
iot2050: Add watchdog start to bootcmd
Allows run-time control over watchdog auto-start and the timeout via
setting the environment variable watchdog_timeout_ms. A value of zero
means "do not start". Use CONFIG_WATCHDOG_TIMEOUT_MSECS as initial value
and this to zero by default. Users can then enable the watchdog once the
use and OS which picks it up during boot.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Jan Kiszka [Tue, 28 Feb 2023 18:19:11 +0000 (19:19 +0100)]
iot2050: Update firmware layout
The latest version of the binary-only firmware parts come in a combined
form of FSBL and sysfw containers. This implies some layout changes to
the generated firmware image but also makes handling of artifacts much
simpler (4 files less). The env locations will not change, just the
space reserved for U-Boot will shrink from 4 to 3 MB - still plenty of
space left in practice.
Adjust configuration and documentation accordingly.
Along this change, add a new reservation for update commands of the
user-controlled OTP part. A specific userspace tool will fill it, and
the FSBL will evaluate it during boot. This reservation will use 64K of
the former sysfw section.
Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Su Baocheng [Tue, 28 Feb 2023 18:19:10 +0000 (19:19 +0100)]
arm: dts: iot2050: Use the auto generator nodes for fdt
Refactor according to the entry `fit: Entry containing a FIT` of
document tools/binman/README.entries.
As the generator uses the device tree name for the config description,
board_fit_config_name_match requires a small adjustment as well.
Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[Jan: re-add now required CONFIG_OF_LIST, update config matching] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Su Baocheng [Tue, 28 Feb 2023 18:19:09 +0000 (19:19 +0100)]
board: siemens: iot2050: Split the build for PG1 and PG2
Due to different signature keys, the PG1 and the PG2 boards can no
longer use the same FSBL (tiboot3). This makes it impossible anyway to
maintaine a single flash.bin for both variants, so we can also split the
build.
A new target is added to indicates the build is for PG1 vs. PG2 boards.
Hence now the variants have separated defconfig files.
The runtime board_is_sr1() check does make no sense anymore, so remove
it and replace with build time check.
Documentation is updated accordingly. New binary artifacts are already
available via meta-iot2050.
Signed-off-by: Su Baocheng <baocheng.su@siemens.com>
[Jan: refactor config option into targets, tweak some wordings] Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Fabio Estevam [Wed, 22 Mar 2023 19:59:31 +0000 (16:59 -0300)]
imx6sx-udoo-neo-basic: Introduce the u-boot.dtsi
After the conversion to DM_SERIAL in commit 01f372d8d62b ("udoo_neo:
Select DM_SERIAL and drop iomux board level init") the SPL log is gone
and the U-Boot proper log becomes incomplete:
Core: 80 devices, 18 uclasses, devicetree: separate
MMC: FSL_SDHC: 1, FSL_SDHC: 2
Loading Environment from MMC... OK
In: serial@2020000
Out: serial@2020000
Err: serial@2020000
Net: eth0: ethernet@2188000
Hit any key to stop autoboot: 0
Introduce the u-boot.dtsi file that passes the u-boot,dm-pre-reloc
properties to the relevant nodes so that UART can be used early in SPL.
With this change, the complete SPL and U-Boot messages are seen again.
Simon Glass [Mon, 27 Mar 2023 19:34:14 +0000 (08:34 +1300)]
cli: Correct handling of invalid escape sequences in cread_line()
The second call to cli_ch_process() is in the wrong place, meaning that
the one of the characters of an invalid escape sequence is swallowed
instead of being returned.
Fix the bug and add a test to cover this.
This behaviour matches that of the code before cli_getch() was
introduced. This was verified on the commit before b08e9d4b66 i.e.:
7d850f85aad ("sandbox: Enable mmc command and legacy images")
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Simon Glass [Mon, 27 Mar 2023 19:34:13 +0000 (08:34 +1300)]
cli: Correct several bugs in cli_getch()
This function does not behave as expected when unknown escape sequences
are sent to it:
- it fails to store (and thus echo) the last character of the invalid
sequence
- it fails to set esc_len to 0 when it finishes emitting the invalid
sequence, meaning that the following character will appear to be part
of a new escape sequence
- it processes the first character of the rejected sequence as a valid
character, just starting the sequence all over again
The last two bugs conspire to produce an "impossible condition #876"
message which is the main symptom of this behaviour.
Fix these bugs and add a test to verify the behaviour.
Signed-off-by: Simon Glass <sjg@chromium.org> Reported-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Tom Rini [Mon, 27 Mar 2023 15:16:51 +0000 (11:16 -0400)]
Merge branch '2023-03-27-rockchip-rk3399-fixes'
- A series of minor cleanups to DISTRO_DEFAULTS and BOOTSTD so that the
rk3399 bootstd migration can be complete and functional now, and make
future migrations easier.
Tom Rini [Fri, 24 Mar 2023 20:58:15 +0000 (16:58 -0400)]
rockchip: Use BOOTSTD_DEFAULTS if not DISTRO_DEFAULTS
When we do not enable DISTRO_DEFAULTS (generally, to get distro_bootcmd)
we instea do want to imply BOOTSTD_DEFAULTS so that when using bootstd
the general distro boot functionality will still work.
Simon Glass [Fri, 24 Mar 2023 20:58:13 +0000 (16:58 -0400)]
boot: Create a common BOOT_DEFAULTS for distro and bootstd
These two features use a lot of common options. Move them into a common
CONFIG to reduce duplication.
Use 'select' for most options since these are things that boards aren't
supposed to override. For now it is not possible to disable
BOOT_DEFAULTS but we may take another look later.
Note that five options use 'imply' to match existing behaviour.
Signed-off-by: Simon Glass <sjg@chromium.org>
[trini: Rework a bit so we don't grow so many platforms unintentionally] Signed-off-by: Tom Rini <trini@konsulko.com>
Simon Glass [Fri, 24 Mar 2023 20:58:10 +0000 (16:58 -0400)]
rockchip: Drop bootstage stash in TPL and SPL for rockpro64
Unfortunately the IRAM used to stash the bootstage records in TPL
becomes inaccessible after SPL runs. Presumably this is because of ATF
taking it over.
We could move the stash to another address in SPL, before passing it to
U-Boot proper. But it seems easier to wait until we have support for
standard passage[1] which should not be too far away.
Sergiu Moga [Wed, 8 Mar 2023 14:39:53 +0000 (16:39 +0200)]
clk: at91: sam9x60: Add initial setup of UPLL and USBCK rates
In order for some of the functionalities, such as the USB clocks,
to work properly we need some clocks to be properly initialised
at the very beginning of booting.
Claudiu Beznea [Wed, 8 Mar 2023 14:39:52 +0000 (16:39 +0200)]
clk: at91: pmc: export clock setup to pmc
Clock setup was intended for setting clocks at boot time on SAMA7G5,
e.g. for root clocks like PLLs, that were used to feed IPs needed alive
in u-boot (e.g. Ethernet clock feed by a PLL). Export this functionality
to all at91 clocks as it may be necessary on other SoCs.
Sergiu Moga [Wed, 8 Mar 2023 14:39:50 +0000 (16:39 +0200)]
clk: at91: Add support for sam9x60 USB clock
Implement sam9x60 USB clock driver. This clock has
three parents: PLLA, UPLL and MAINXTAL. The driver is
aware of the three possible parents with the help of the
two mux tables provied to the driver during the registration
of the clock.
* Let EFI app call ExitBootServices() before legacy booting kernel
* Support zboot and bootm in the EFI app
* Let efi command show configuration tables
* Support booting a 64-bit kernel from 64-bit EFI app
* Allocate device-tree copy from high memory
* simplify efi_str_to_u16()
projects / thirdparty / u-boot.git / log
