Andy Shevchenko [Wed, 30 Mar 2022 09:14:43 +0000 (12:14 +0300)]
efi_loader: initrddump: Actually use the custom CFLAGS
It seems a copy'n'paste typo when tool had been introduced.
It has never had the 'exit' suffix in the file name. Hence,
the custom CFLAGS never been applied and, for example, BFD
linker complains:
LD lib/efi_loader/initrddump_efi.so
ld.bfd: lib/efi_loader/initrddump.o: warning: relocation in read-only section `.text.efi_main'
ld.bfd: warning: creating DT_TEXTREL in a shared object
Remove wrong 'exit' suffix from the custom CFLAGS variable.
Fixes: 65ab48d69ddb ("efi_selftest: provide initrddump test tool") Fixes: 9c045a49a9c9 ("efi_loader: move dtbdump.c, initrddump.c to lib/efi_loader") Signed-off-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Bin Meng [Mon, 28 Mar 2022 02:43:50 +0000 (10:43 +0800)]
doc: usage: Update vxworks doc to mention RISC-V support
At present the doc only mentions Arm, PowerPC and x86. RISC-V support
has been added since VxWorks SR0650 support for a while, and U-Boot
supports loading a RISC-V VxWorks kernel too. Let's document it.
Signed-off-by: Bin Meng <bmeng.cn@gmail.com> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Patrick Delaunay [Tue, 29 Mar 2022 14:01:13 +0000 (16:01 +0200)]
doc: mmc dev
Provide human readable descriptions of the speed nodes instead of the name
of constants from the code as it is already done for 'mmc rescan'
command in commit 212f078496e4 ("doc: mmc rescan speed mode").
Signed-off-by: Patrick Delaunay <patrick.delaunay@foss.st.com> Reviewed-by: Aswath Govindraju <a-govindraju@ti.com> Reviewed-by: Bin Meng <bmeng.cn@gmail.com>
Sughosh Ganu [Sun, 13 Mar 2022 14:47:58 +0000 (20:17 +0530)]
qemu: arm: Remove platform specific function to get RNG device
The QEMU platform has a function defined to get the random number
generator(RNG) device. However, the RNG device can be obtained simply
by searching for a device belonging to the RNG uclass. Remove the
superfluous platform function defined for the QEMU platform for
getting the RNG device.
Signed-off-by: Sughosh Ganu <sughosh.ganu@linaro.org> Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Tom Rini [Thu, 31 Mar 2022 12:28:43 +0000 (08:28 -0400)]
Merge branch '2022-03-31-critical-fixes'
- Fixes for 2 gateworks platforms, Edison platform, incorrectly showing
2 logos on LCD screens, not cleaning a generated environment file and
correct the CONFIG_SYS_IMMR Kconfig migration on a number of MPC85xx
platforms.
Tim Harvey [Wed, 30 Mar 2022 20:39:02 +0000 (13:39 -0700)]
board: gateworks: venice: determine dram size at runtime
The SPL does not update the memory node with the dram size from EEPROM
but instead we can use get_ram_size which does a simple memory test
to determine the available RAM. Update PHYS_SDRAM_SIZE to 4GiB as that
is the max used on the Venice boards.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Tom Rini [Wed, 30 Mar 2022 13:30:15 +0000 (09:30 -0400)]
powerpc: Fix incorrect SYS_IMMR migration values
When migrating SYS_IMMR, I didn't allow for boards to provide
non-default values here. This lead to an incorrect migration on the
platforms where CONFIG_SYS_IMMR is set to CONFIG_SYS_CCSRBAR and
CONFIG_SYS_CSSRBAR is NOT the same as CONFIG_SYS_CCSRBAR_DEFAULT. Add
text to the prompt so that non-default values can be used and re-migrate
the platforms that have CONFIG_SYS_IMMR=CONFIG_SYS_CSSRBAR where
CONFIG_SYS_CSSRBAR != CONFIG_SYS_CCSRBAR_DEFAULT.
Fixes: be7dbb60c5bf ("Convert CONFIG_SYS_IMMR to Kconfig") Reported-by: Pali Rohár <pali@kernel.org> Signed-off-by: Tom Rini <trini@konsulko.com> Tested-by: Pali Rohár <pali@kernel.org>
Makefile: make clean should delete include/generated/env.in
'make sifive_unamtched_defconfig; make clean; make' fails if file
include/generated/env.in exists. 'make clean' should remove all files that
stop building.
Add file include/generated/env.in to the clean target.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Marek Behún <marek.behun@nic.cz>
commit 7c84319af9c7 ("dm: gpio: Correct use of -ENODEV in drivers")
changed the return code for an I2C NAK from -ENODEV to -EREMOTEIO.
Update the gsc_i2c_read and gsc_i2c_write functions for this change
to properly retry the transaction on a NAK meaning the GSC is busy.
Fixes: 7c84319af9c7 ("dm: gpio: Correct use of -ENODEV in drivers") Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Tom Rini [Wed, 30 Mar 2022 22:08:22 +0000 (18:08 -0400)]
Merge tag 'clk-2022.04-next' of https://source.denx.de/u-boot/custodians/u-boot-clk into next
Clock patches for u-boot/next
This is mostly cleanups/consolidations. clk_free is made to return void, and the
CCF wrappers present in almost every CCF clock are consolidated. I would
particularly like to have the latter upstream, since there are at least two
series adding support for new CCF drivers (imx8mq and imxrt1170) which can
benefit from these commits.
I had to fix up the last commit since I missed an include for at91.
Sean Anderson [Sun, 20 Mar 2022 20:34:46 +0000 (16:34 -0400)]
clk: Use generic CCF ops where possible
This converts most CCF drivers to use generic ops. imx6q is the only
outlier, where we retain the existing functionality by moving the check to
request().
Signed-off-by: Sean Anderson <seanga2@gmail.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Link: https://lore.kernel.org/r/20220320203446.740178-2-seanga2@gmail.com
[ fixed missing include for at91 ] Signed-off-by: Sean Anderson <seanga2@gmail.com>
Sean Anderson [Sun, 20 Mar 2022 20:34:45 +0000 (16:34 -0400)]
clk: ccf: Add some helper functions for clock ops
Most CCF drivers follow a common pattern where their clock ops defer the
actual operation to the backing CCF clock. Add some generic implementations
of these functions to reduce duplication of code.
Sean Anderson [Sun, 27 Feb 2022 19:01:13 +0000 (14:01 -0500)]
clk: Consolidate some clock functions
These functions are exactly the same as their "nodev" varients, except they
accept a device and not an ofnode. Rewrite them to just call the other
function.
Sean Anderson [Sat, 15 Jan 2022 22:25:04 +0000 (17:25 -0500)]
clk: Make clk_free return void
Most callers of this function do not check the return value, and it is
unclear what action they should take if it fails. If a function is freeing
multiple clocks, it should not stop just because the first one failed.
Since the callbacks can no longer fail, just convert the return type to
void.
Sean Anderson [Sat, 15 Jan 2022 22:24:58 +0000 (17:24 -0500)]
clk: Make rfree return void
When freeing a clock there is not much we can do if there is an error, and
most callers do not actually check the return value. Even e.g. checking to
make sure that clk->id is valid should have been done in request() in the
first place (unless someone is messing with the driver behind our back).
Just return void and don't bother returning an error.
Michal Simek [Fri, 15 Oct 2021 13:17:29 +0000 (15:17 +0200)]
pwm: Add driver for cadence TTC
TTC has three modes of operations. Timer, PWM and input counters.
There is already driver for timer under CADENCE_TTC_TIMER which is used for
ZynqMP R5 configuration.
This driver is targeting PWM which is for example configuration which can
be used for fan control.
The driver has been tested on Xilinx Kria SOM platform where fan is
connected to one PL pin. When TTC output is connected via EMIO to PL pin
TTC pwm can be configured and tested for example like this:
pwm config 0 0 10000 1200
pwm enable 0 0
pwm config 0 0 10000 1400
pwm config 0 0 10000 1600
The DLL mode supported SD reference clocks are 50 MHz, 100 MHz and
200 MHz. When user select SD frequency as 200MHz in the design, the
actual frequency is going to come around ~187MHz (<= 200MHz considering
the parent clock and divisor selection). We need to set SDx_BASECLK as
200 in this case, setting 187 will result in tuning failures in mmc.
Set SDx_BASECLK to exact value of 200, 100 or 50 based on the frequency
range.
Michal Simek [Fri, 25 Mar 2022 10:50:07 +0000 (11:50 +0100)]
serial: zynq: Change fifo behavior in debug mode
Serial IP has output buffer which status is indicated by two bits. If fifo
if empty or full. Default configuration is that chars are pushed to fifo
till it is full. Time to time it is visible that chars are scambled and
logs are not visible. Not sure what it is exactly happening but all the
time it helps to change driver behavior to write only one char at a time.
That's why enable this mode when debug uart is enabled not to see scrambled
chars in debug by default.
Michal Simek [Thu, 24 Mar 2022 12:31:26 +0000 (13:31 +0100)]
arm64: zynqmp: Remove low level UART setting cont
There is no reason to do serial initialization. Uart driver does it already
based on DT. Good effect is that it is clear which interface is console.
The same change was done in past by commit 84d2bbf082fa ("arm64: zynqmp:
Remove low level UART setting").
Michal Simek [Thu, 24 Mar 2022 09:17:51 +0000 (10:17 +0100)]
dt-bindings: phy: Sync phy.h with Linux kernel
Make sure that both files are in sync to have the same values in DTs.
The patch is fixing SPDX license as is used in the kernel and adding new
values for PHY_TYPE_DPHY and PHY_TYPE_CPHY.
Michal Simek [Thu, 17 Mar 2022 14:25:31 +0000 (15:25 +0100)]
arm64: versal: Do not place u-boot to reserved memory location
Versal can also have reserved space in DT which u-boot has to avoid to
placing self to that location. The same change was done in ZynqMP by commit ce39ee28ec31 ("zynqmp: Do not place u-boot to reserved memory location")
and also for microblaze by commit d7b5cc89d329 ("microblaze: Do not place
u-boot to reserved memory location").
The patch was tested by adding reserved-memory node to DT and check via
bdinfo back.
Marek Vasut [Mon, 21 Feb 2022 05:16:12 +0000 (06:16 +0100)]
arm: socfpga: vining: Fix mtdparts for 2x256 MiB SF variant
The 2x256 MiB SF variant of this system has 192 MiB rootfs MTD partition
containing UBI on SF0, use the correct size in U-Boot environment, else
U-Boot cannot mount UBI and boot on this variant.
Signed-off-by: Marek Vasut <marex@denx.de> Cc: Siew Chin Lim <elly.siew.chin.lim@intel.com> Cc: Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> Cc: Tien Fong Chee <tien.fong.chee@intel.com> Cc: Tom Rini <trini@konsulko.com>
Tim Harvey [Tue, 22 Mar 2022 18:42:49 +0000 (11:42 -0700)]
imx: ventana: enable ONFI detection to fix NAND chip configuration
Enable ONFI detection to fix NAND chip configuration. Without this
the NAND oobsize will be wrong which leads to invalid ECC strength and
incompatibility with the previous configuration.
Fixes: 777f333c375a ("imx: ventana: enable dm for MTD and NAND") Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Fabio Estevam <festevam@denx.de>
Simon Glass [Sun, 23 Jan 2022 14:04:08 +0000 (07:04 -0700)]
video: Drop references to CONFIG_VIDEO et al
Drop the Kconfigs which are not used and all references to them. In
particular, this drops CONFIG_VIDEO to avoid confusion and allow us to
eventually rename CONFIG_DM_VIDEO to CONFIG_VIDEO.
Also drop the prototype for video_get_info_str() which is no-longer used.
Signed-off-by: Simon Glass <sjg@chromium.org> Acked-by: Jason Liu <jason.hui.liu@nxp.com>
Han Xu [Fri, 25 Mar 2022 13:36:38 +0000 (08:36 -0500)]
mtd: gpmi: fix the bch setting backward compatible issue
Previous u-boot code changed the default bch setting behavior and caused
backward compatible issue. This fix choose the legacy bch geometry back
again as the default option. If the minimum ecc strength that NAND chips
required need to be chosen, it can be enabled by either adding DT flag
"fsl,use-minimum-ecc" or CONFIG_NAND_MXS_USE_MINIMUM_ECC in configs. The
unused flag "fsl,legacy-bch-geometry" get removed.
Fixes: 51cdf83eea (mtd: gpmi: provide the option to use legacy bch geometry) Fixes: 616f03daba (mtd: gpmi: change the BCH layout setting for large oob NAND) Tested-by: Tim Harvey <tharvey@gateworks.com> Tested-by: Sean Nyekjaer <sean@geanix.com> Signed-off-by: Han Xu <han.xu@nxp.com> Reviewed-by: Miquel Raynal <miquel.raynal@bootlin.com>
Mark Kettenis [Mon, 21 Mar 2022 21:41:18 +0000 (22:41 +0100)]
arm: apple: Fix mem layout
The current approach for setting the environment variables that
describe the memory layout runs the risk of overlapping with
reserved memory regions. Use the lmb code to derive the addresses
for these variables instead.
Signed-off-by: Mark Kettenis <kettenis@openbsd.org> Reviewed-by: Simon Glass <sjg@chromium.org>
Up to now the initrddump.efi application has drained the input after
showing the prompt. This works for humans but leads to problems when
automating testing. If the input is drained, this should be done before
showing the prompt.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
efi_loader: nocolor command line attr for initrddump.efi
initrddump.efi uses colored output and clear the screen. This is not
helpful for integration into Python tests. Allow specifying 'nocolor' in
the load option data to suppress color output and clearing the screen.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Andre Przywara [Tue, 15 Mar 2022 23:20:54 +0000 (23:20 +0000)]
sunxi: dts: Update RGMII phy-mode properties
Commit f11513d99787 ("net: phy: realtek: Add tx/rx delay config for
8211e") made the Realtek PHY driver honour the phy-mode DT property,
to set up the proper delay scheme for the RX and TX lines. A similar
change in the kernel revealed that those properties were mostly wrong.
The kernel DTs got updated over the last few months, but we were missing
out on the U-Boot version.
Just sync in the phy-mode properties from the mainline kernel,
v5.17-rc7, to avoid the breaking DT sync that late in the cycle.
This fixes Ethernet operation on the affected boards.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Samuel Holland <samuel@sholland.org>
Andre Przywara [Tue, 15 Mar 2022 00:00:53 +0000 (00:00 +0000)]
sunxi: Fix old GMAC pinmux setup
Commit 5bc4cd05d7d4 ("sunxi: move non-essential code out of s_init()")
moved the call to eth_init_board() from s_init() into board_init_f().
This means it's now only called from the SPL, which makes sense for
most of the other moved low-level functions. However the GMAC pinmux and
clock setup in eth_init_board() was not happy about that, so it broke
the sun7i GMAC.
Since Ethernet is of no use in the SPL anyway, just move the call into
board_init(), which is only run in U-Boot proper.
This fixes Ethernet operation for the A20 SoCs, which broke in
v2022.04-rc1, with the above mentioned commit.
Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Jernej Skrabec <jernej.skrabec@gmail.com> Tested-by: Petr Štetiar <ynezz@true.cz> [a20-olinuxino-lime2]
Billy Tsai [Tue, 8 Mar 2022 03:04:07 +0000 (11:04 +0800)]
ARM: dts: ast2600: Add PWM to device tree
Add the PWM node and enable it for AST2600 EVB
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Billy Tsai [Tue, 8 Mar 2022 03:04:06 +0000 (11:04 +0800)]
pinctrl: Add the pinctrl setting for PWM.
This patchs add the signal description array for PWM pinctrl settings.
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Billy Tsai [Tue, 8 Mar 2022 03:04:05 +0000 (11:04 +0800)]
pwm: Add Aspeed ast2600 PWM support
This patch add the support of PWM controller which can be found at aspeed
ast2600 soc. The pwm supoorts up to 16 channels and it's part function
of multi-function device "pwm-tach controller".
Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com>
Pali Rohár [Fri, 18 Feb 2022 12:16:19 +0000 (13:16 +0100)]
pci: Remove duplicate PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* macros
Macros PCI_CLASS_CODE_* and PCI_CLASS_SUB_CODE_* are unused and are
duplication of PCI_CLASS_* macros defined in pci_ids.h header file.
So remove them.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Pali Rohár [Fri, 18 Feb 2022 12:16:18 +0000 (13:16 +0100)]
sandbox: video: Replace PCI_CLASS_* macros by one from pci_ids.h
Replace old macros PCI_CLASS_CODE_COMM and PCI_CLASS_SUB_CODE_COMM_SERIAL
by new macros defined in pci_ids.h. Old macros would be deleted in followup
commit.
Signed-off-by: Pali Rohár <pali@kernel.org> Reviewed-by: Stefan Roese <sr@denx.de>
Sean Anderson [Tue, 22 Feb 2022 17:19:25 +0000 (12:19 -0500)]
Add option to use -Og
This adds support for using -Og when building U-Boot. According to the
gcc man page:
> -Og should be the optimization level of choice for the standard
> edit-compile-debug cycle, offering a reasonable level of optimization
> while maintaining fast compilation and a good debugging experience.
This optimization level is roughly -O1 minus a few additional
optimizations. It provides a noticably better debugging experience, with
many fewer variables <optimized out>.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>
Sean Anderson [Tue, 22 Feb 2022 17:19:24 +0000 (12:19 -0500)]
Split CONFIG_CC_OPTIMIZE_FOR_SIZE into two configs
This adds a separate CONFIG_CC_OPTIMIZE_FOR_SPEED option in a choice,
in preparation for adding another optimization option. Also convert SH's
makefile to use this new option.
Signed-off-by: Sean Anderson <sean.anderson@seco.com> Reviewed-by: Simon Glass <sjg@chromium.org>