Simon Glass [Fri, 6 Mar 2026 18:12:46 +0000 (11:12 -0700)]
binman: test: Move FIT signing test data to test/fit/
Move the signing-related test data (keys, certificates, OpenSSL and
SoftHSM2 configuration, dummy engine source) into the fit/ subdirectory
alongside the FIT DTS test files. Drop the 340_ prefix from files that
had it. Update the Makefile and all ftest.py references.
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Simon Glass [Fri, 6 Mar 2026 18:12:44 +0000 (11:12 -0700)]
binman: test: Move remaining test files to test/entry/
Move the remaining 60 or so test files into an entry/ subdirectory.
These cover general entry types and features: entry args, fill, text,
env, compress, replace, template, collection, ELF, overlap, listing,
sections, symlink, TEE OS, and other miscellaneous entries. Drop the
numeric prefixes and update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:43 +0000 (11:12 -0700)]
binman: test: Move symbol test files to test/symbols/
Move about 10 test files for binman symbol patching into a symbols/
subdirectory. Drop the numeric prefixes and the redundant symbols_
filename prefix, and update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:42 +0000 (11:12 -0700)]
binman: test: Move vendor-specific test files to test/vendor/
Move about 20 test files for vendor-specific platform support (TI, NXP
i.MX, Renesas R-Car, Rockchip, PowerPC MPC85xx) into a vendor/
subdirectory. Drop the numeric prefixes and update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Simon Glass [Fri, 6 Mar 2026 18:12:41 +0000 (11:12 -0700)]
binman: test: Move UEFI capsule test files to test/capsule/
Move about a dozen test files for UEFI capsule creation (signed,
versioned, accept, revert) into a capsule/ subdirectory. Drop the
numeric prefixes and the redundant capsule_ filename prefix, and
update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:40 +0000 (11:12 -0700)]
binman: test: Move FIP/TF-A test files to test/fip/
Move about 15 test files for ARM Trusted Firmware FIP, ATF BL31, SCP,
OpenSBI, and BL1 entries into a fip/ subdirectory. Drop the numeric
prefixes and the redundant fip_ filename prefix, and update all
references.
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Simon Glass [Fri, 6 Mar 2026 18:12:39 +0000 (11:12 -0700)]
binman: test: Move mkimage test files to test/mkimage/
Move about a dozen test files for mkimage entries into a mkimage/
subdirectory. Drop the numeric prefixes and the redundant mkimage_
filename prefix, and update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:37 +0000 (11:12 -0700)]
binman: test: Move CBFS test files to test/cbfs/
Move about a dozen test files for Coreboot File System entries into a
cbfs/ subdirectory. Drop the numeric prefixes and the redundant cbfs_
filename prefix, and update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:36 +0000 (11:12 -0700)]
binman: test: Move security test files to test/security/
Move about 20 test files for signing, encryption, hash, pre-load,
x509, and Xilinx bootgen entries into a security/ subdirectory. Drop
the numeric prefixes and update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Simon Glass [Fri, 6 Mar 2026 18:12:35 +0000 (11:12 -0700)]
binman: test: Move blob test files to test/blob/
Move about a dozen test files for blob, blob-ext, blob-ext-list,
fake-blob, and blob-symbol entries into a blob/ subdirectory. Drop
the numeric prefixes and the redundant blob_ filename prefix, and
update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:34 +0000 (11:12 -0700)]
binman: test: Move FDT/fdtmap test files to test/fdt/
Move about 30 test files for FDT update, fdtmap, DTB compression,
alternates, and bootph into an fdt/ subdirectory. Drop the numeric
prefixes and the redundant fdt_ filename prefix, and update all
references.
Remove the unused no_alt_format.dts which has no references in any
test.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:33 +0000 (11:12 -0700)]
binman: test: Move FIT image test files to test/fit/
Move about 40 test files for FIT images (signing, external data,
split-elf, encryption, alignment, firmware loadables, templates) into
a fit/ subdirectory. Drop the numeric prefixes and the redundant fit_
filename prefix, and update all references.
Rename the three signature.dts variants to have unique names:
signature.dts, signature_multi_key.dts and signature_no_nodes.dts.
Signed-off-by: Simon Glass <simon.glass@canonical.com>
Simon Glass [Fri, 6 Mar 2026 18:12:32 +0000 (11:12 -0700)]
binman: test: Move x86 and Intel test files to test/x86/
Move about 40 test files for x86 and Intel platform support (ROM,
microcode, ME, IFWI, FSP, descriptor, reset16, start16, FIT) into an
x86/ subdirectory. Drop the numeric prefixes and the redundant x86_
filename prefix, and update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:31 +0000 (11:12 -0700)]
binman: test: Move U-Boot variant test files to test/xpl/
Move about a dozen test files for U-Boot image variants (SPL, TPL,
VPL, DTB, nodtb, bss-pad) into an xpl/ subdirectory. Drop the
numeric prefixes and the redundant u_boot_ filename prefix, and
update all references.
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Simon Glass [Fri, 6 Mar 2026 18:12:30 +0000 (11:12 -0700)]
binman: test: Move pack/layout test files to test/pack/
Move about 50 test files related to basic layout, packing, alignment,
sections, and image structure into a pack/ subdirectory. Drop the
numeric prefixes from the filenames and update all references in
ftest.py, entry_test.py, and binman_tests.rst
Signed-off-by: Simon Glass <simon.glass@canonical.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
David Lechner [Fri, 6 Mar 2026 22:05:55 +0000 (16:05 -0600)]
clk: mediatek: set CLK_PARENT_XTAL on fixed factor clocks
Explicitly set the CLK_PARENT_XTAL flag for fixed factor clocks.
Prior to this, it was assumed that clock ID 0 was CLK_XTAL and other
IDs used a different clock tree when no parent was explicitly set.
Making the parent explicit will allow us to remove this confusing
behavior in the future.
David Lechner [Fri, 6 Mar 2026 22:05:50 +0000 (16:05 -0600)]
clk: mediatek: add MUX_GATE_MIXED macros
Add new MUX_GATE_MIXED and MUX_GATE_MIXED_FLAGS macros for mixed parent
muxes that have a gate. These will be used in a few drivers where we
already have this type of mux clocks.
David Lechner [Fri, 6 Mar 2026 22:05:48 +0000 (16:05 -0600)]
clk: mediatek: rename HAVE_RST_BAR
Rename HAVE_RST_BAR to CLK_PLL_HAVE_RST_BAR. This makes it more clear
that this flag only applies to PLL clocks. Also add a blank line between
CLK_PLL_HAVE_RST_BAR and the CLK_MUX_ macros to keep the grouping of the
flags consistent.
sunxi: a133: dram: Align parameters terminology with Allwinner
There is a mistmatch between Allwinner's dram_para BSP definitions and the
parameters names in mainline u-boot for TPR1-3. What we call TPR1 is actually
MR22 while TPR2 is TPR0 and TPR3 is TPR1. MR22 does get written to the
corresponding register. This only concerns LPDDR4 support.
Introduce a new Kconfig entry for MR22 and proceed with the rename.
Update the only config currently using it.
See the list of parameters from the Allwinner BSP at the end of:
https://linux-sunxi.org/A133/DRAMC
Note that the H616/H6 code is coherent with this new TPR0 definition
(and does not use TPR1 and MR22).
Some of the offsets for the DRAM PHY dx delays are wrong (as compared
to the H616 code and the reference binary) since the
mctl_phy_dx_delay0_inner function does not perform the correct
calculation for some of them.
Introduce a mctl_phy_dx_delay0_inner0 to fix the incorrect offsets and
rename the existing function to mctl_phy_dx_delay0_inner1 for the
offsets it correctly handles.
Also add memory barriers that are also present in the H616 code while
at it.
This fixes detection of 4 GiB DRAM on some boards using LPDDR4.
Chris Chen [Tue, 3 Mar 2026 19:54:55 +0000 (13:54 -0600)]
clk: mediatek: add clock driver for MT8189
Add new clock driver for MedaiTek MT8189 and compatible SoCs.
Signed-off-by: Chris Chen <chris-qj.chen@mediatek.com> Co-developed-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Julien Stephan <jstephan@baylibre.com> Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com> Link: https://patch.msgid.link/20260303-mtk-mt8189-clocks-v4-7-ee85f8dd2f0d@baylibre.com Signed-off-by: David Lechner <dlechner@baylibre.com>
Add a new MUX_MIXED_CLR_SET_UPD_FLAGS() macro. This is the same as
MUX_CLR_SET_UPD_FLAGS() except that it uses the parent_flags member
of the union instead of parent.
This will be needed by the incoming mt8189 clock driver.
David Lechner [Tue, 3 Mar 2026 19:54:52 +0000 (13:54 -0600)]
clk: mediatek: add CLK_PARENT_EXT
Add support for external clock parent type in MediaTek clock driver to
allow multiple external clock sources.
This is intended to eventually replace CLK_PARENT_XTAL which only allows
a single external clock source. Replacing CLK_PARENT_XTAL is not trivial
since it would required touching all chip-specific drivers. So that is
saved for another day.
Before this change, the only way to add additional external clocks was
to use a clock ID mapping and add the external clock in the fixed clocks
portion of the CLK_PARENT_TOPCKGEN clocks. After this change, such hacks
are no longer necessary and external clocks can be added in a cleaner
way.
Add helper functions to check if a clock ID corresponds to a particular
clock type (mux, gate, fdiv). This simplifies the code and makes it more
readable.
Additionally, it removes the restriction that fdivs_offs < muxes_offs <
gates_offs by making the checking more strict in some places. This will
allow future drivers to not have to define a mapping to meet this
requirement.
Refactor duplicate parent rate lookup code into a common function.
Instead of relying on rules like X is always the parent of Y, we use
the driver ops pointer to make sure we are actually getting the correct
parent clock device. This allows the same function to be called from
different clock types and will allow future chip-specific clock drivers
to not have to follow the rules as strictly.
David Lechner [Tue, 3 Mar 2026 19:54:49 +0000 (13:54 -0600)]
clk: mediatek: use correct struct type for infrasys clocks
Fix the private data type struct type in a couple of infrasys clock
functions.
struct mtk_cg_priv is a superset of struct mtk_clk_priv and has the same
layout at the beginning so there was no compile errors or runtime bugs.
This could only be found by inspecting the code.
Change CLK_TOP_CLK13M rate from 130_000_000 to 13_000_000 and
CLK_TOP_CLK26M rate from 260_000_000 to 26_000_000. As the names
suggest, these clocks are 13/26 MHz, not 130/260 MHz.
Daniel Golle [Wed, 4 Mar 2026 03:53:38 +0000 (03:53 +0000)]
clk: mediatek: mt7622: fix infracfg and pericfg clock operations
The MT7622 infracfg and pericfg drivers both use
mtk_common_clk_infrasys_init() for probe, which populates struct
mtk_clk_priv and stores gate definitions in the clk_tree. However,
both drivers were incorrectly wired to mtk_clk_gate_ops which expects
struct mtk_cg_priv with separately populated gates/num_gates/gates_offs
fields from mtk_common_clk_gate_init().
Since those fields were never set, any attempt to enable an infracfg or
pericfg gate clock (e.g. CLK_INFRA_TRNG) would fail with -EINVAL.
Switch both to mtk_clk_infrasys_ops and struct mtk_clk_priv to match
the init function.
Fixes: 72ab603b201 ("clk: mediatek: add driver for MT7622") Signed-off-by: Daniel Golle <daniel@makrotopia.org> Reviewed-by: David Lechner <dlechner@baylibre.com> Signed-off-by: David Lechner <dlechner@baylibre.com>
Fabio Estevam [Fri, 13 Mar 2026 21:00:04 +0000 (18:00 -0300)]
doc: imx95_evk: Update Arm GNU toolchain version to 14.2
The imx-oei and imx-sm build systems defaults to:
TC_VERSION ?= 14.2.rel1
but the documentation still instructs users to download the 13.3 toolchain.
This causes the build to fail because the expected directory name does
not exist.
Update the documentation to reference the 14.2 toolchain to match the build
system default.
Signed-off-by: Fabio Estevam <festevam@nabladev.com> Acked-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Thu, 12 Mar 2026 00:57:23 +0000 (08:57 +0800)]
misc: ele_api: Add support for XSPI SET GMID command
The XSPI SET GMID command is used to assign GMID ownership to the
requester, allowing access to protected XSPI control registers. This API
must be called in SPL if XSPI GMID-protected settings need to be
modified. Otherwise, XSPI configuration depends on the previous GMID
owner to provide the correct settings.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Alice Guo [Thu, 12 Mar 2026 00:57:22 +0000 (08:57 +0800)]
spi: nxp_xspi: Add new driver for NXP XSPI controller
Add new driver to support NXP XSPI controller for NOR and NAND flash.
XSPI controller also uses a programmable sequence engine to provide
flexibility to support existing and future memory devices. It supports
single, dual, quad, octal modes of operation.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com>
Francois Berder [Thu, 5 Mar 2026 16:40:05 +0000 (17:40 +0100)]
liebherr: btt: Fix buffer overflow in board_fit_config_name_match
The maximum length of the board name is not 11 characters
but 14: 11 bytes for the prefix + 3 bytes for the u8 + 1 NULL byte.
Hence, this commit increases the size of the name buffer variable
to 15. Also, this commit fixes the format specifier for the rev_id
variable.
Peng Fan [Mon, 2 Mar 2026 05:20:11 +0000 (13:20 +0800)]
arm64: dts: freescale: Add initial device tree for i.MX952
i.MX952 is designed for AI-powered sensor fusion and vision sensing
applications, it features 4 Corte-A55, 1 Cortex-M33, 1 Cortex-M7 and
NXP eIQ NPU and advanced graphics, video and advanced security with
edgelock. Product info could be found at:
https://www.nxp.com/products/i.MX-952
The basic device tree includes:
- clock, pin, power header files
- device nodes: CPU[0-3], SCMI firmware, Interrupt Controller, Sys counter,
eDMA, MU, SPI, UART, I2C, USB and etc
Alice Guo [Mon, 2 Mar 2026 05:20:10 +0000 (13:20 +0800)]
arm: imx9: Keep WDG3/WDG4 untouched for i.MX952
On i.MX952, WDG3 and WDG4 are not used for system reset. PSCI is used
instead. Keep WDG3 and WDG4 in their default state rather than
explicitly disabling them.
Alice Guo [Mon, 2 Mar 2026 05:20:08 +0000 (13:20 +0800)]
arm: imx9: Add i.MX952 SoC support
Add basic SoC support for i.MX952:
- Add CONFIG_IMX952 Kconfig option
- Include i.MX952 clock and power headers
- Set CPU speed grade to 1.7GHz for i.MX952
Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: David Zang <davidzangcs@gmail.com>
Ye Li [Mon, 2 Mar 2026 05:20:04 +0000 (13:20 +0800)]
pinctrl: nxp: Add i.MX952 support
Multiple pads can drive the same module input pin, and a daisy chain
register is used to select the active input path. This patch defines
DAISY_OFFSET_IMX952 (0x460) and allows binding on i.MX952.
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Ye Li [Mon, 2 Mar 2026 05:20:02 +0000 (13:20 +0800)]
imx9: scmi: Get DDR size through SM SCMI API
System Manager(SM) has implemented the MISC protocol to retrieve DDR
information. Using this API, U-Boot can obtain the DDR size dynamically
instead of relying on static configuration macros.
This change addresses the DDR ECC enabled case, where 1/8 of the total
DDR size is reserved for ECC data. The scmi_misc_ddrinfo() returns the
DDR size with EEC overhead already deducted.
Implementation details:
- Query the DDR size via scmi_misc_ddrinfo()
- Replace direct REG_DDR_CS[0,1]_BNDS register reads with SCMI call
- Switch from PHYS_SDRAM[x]_SIZE macros to runtime detection
- For backward compatibility with older SM firmware, fall back to
static PHYS_SDRAM[x]_SIZE configuration if the SCMI call fails
Signed-off-by: Ye Li <ye.li@nxp.com> Signed-off-by: Alice Guo <alice.guo@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Quentin Schulz [Wed, 28 Jan 2026 16:01:25 +0000 (17:01 +0100)]
sunxi: remove usage of legacy LED API
We are trying to get rid of the legacy LED API and PinePhone is one of
the last ones requiring it.
Unlike all other users of the legacy LED API, PinePhone is controlling
the GPIO LED in SPL. Unfortunately, Sunxi doesn't enable DM support in
SPL because of tight space constraints, so we cannot make use of the
modern LED framework as that is based on DM_GPIO.
Since PinePhone is the last user of this API, I'm moving the logic to
Sunxi SPL code and will let this community decide how to handle this hot
potato.
The logic is extremely simplified as only one GPIO LED is currently
controlled in SPL by PinePhone. No need for handling multiple LEDs or
inverted polarity, let's keep it simple.
This however allows us to use the modern LED framework once in U-Boot
proper since this logic won't collide with the new framework.
Since the only misc drivers that were compiled in SPL were guarded by
CONFIG_LED_STATUS and CONFIG_LED_STATUS_GPIO, we can also disable
CONFIG_SPL_DRIVERS_MISC (which does nothing anymore).
This also saves some space for PinePhone in SPL and proper.
Tested-by: Andre Przywara <andre.przywara@arm.com> Signed-off-by: Quentin Schulz <quentin.schulz@cherry.de> Reviewed-by: Simon Glass <simon.glass@canonical.com>
E Shattow [Thu, 5 Mar 2026 21:49:14 +0000 (13:49 -0800)]
doc: board: starfive: jh7110 common update OPENSBI build env reference
Describe build with OpenSBI fw_dynamic.bin path as OPENSBI=<path> on the
same line instead of as an export. Also remedy a typo which had the wrong
directory path before the filename.
Fixes: 8304f3226700 ("doc: board: starfive: update jh7110 common description") Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
E Shattow [Thu, 5 Mar 2026 17:00:22 +0000 (09:00 -0800)]
doc: board: starfive: Add Xunlong OrangePi RV
OrangePi RV is a board that uses the same EEPROM product serial identifier
as the StarFive VisionFive 2 1.3b.
In fact it is not completely compatible with the StarFive VisionFive 2
1.3b for use with Linux Kernel however it is good enough for use with
U-Boot SPL and U-Boot Main. Describe how to set the devicetree search path
and, for advanced users, suggest that it is possible to update the EEPROM
data with an invented "XOPIRV" identifier for automatic board detection.
Signed-off-by: E Shattow <e@freeshell.de> Reviewed-by: Leo Yu-Chi Liang <ycliang@andestech.com>
Hal Feng [Fri, 24 Oct 2025 08:59:29 +0000 (16:59 +0800)]
pcie: starfive: Add a optional power gpio support
Get and enable a optional power gpio. This feature is ported
from the jh7110 pcie driver in Linux. VisionFive 2 Lite needs
this gpio to enable the PCI bus device (M.2 M-Key) power.
Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
pcb_revision is stored in the pcb_revision field of ATOM4. Correct it.
Move the function description to the header file.
Return 0 instead of 0xFF if read_eeprom() fails.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration") Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Directly return the DDR size instead of the field of 'DxxxExxx'.
Move the function description to the header file.
Return 0 instead of 0xFF if read_eeprom() fails.
Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Fixes: aea1bd95b61e ("eeprom: starfive: Enable ID EEPROM configuration") Signed-off-by: Hal Feng <hal.feng@starfivetech.com>
Simon Glass [Wed, 4 Mar 2026 18:48:53 +0000 (11:48 -0700)]
kbuild: strip sub_make_done from test-script environment
The exported sub_make_done variable leaks into the environment of all
child processes. When make targets like tcheck spawn independent
make-invocations with O=, those child-makes inherit sub_make_done=1,
skip the KBUILD_OUTPUT setup and try to build in the source tree.
A global 'unexport sub_make_done' cannot be used because the build
system itself re-invokes the top-level Makefile for syncconfig (via
'$(MAKE) -f $(srctree)/Makefile syncconfig'). Without sub_make_done,
that child make re-enters the KBUILD_OUTPUT block and recomputes
abs_objtree. With a relative O= path this resolves to a nested
directory (e.g. build/build/) where .config does not exist.
Instead, use 'env -u sub_make_done' in the test-target recipes so only
the test scripts see a clean environment. This allows their child make
invocations to process O= correctly without affecting internal kbuild
recursion.
This is not strictly a bugfix, but compare with:
commit 27529f1cb02d ("kbuild: skip parsing pre sub-make code for recursion")
Macpaul Lin [Thu, 5 Mar 2026 10:23:24 +0000 (18:23 +0800)]
scsi: Adjust SCSI inquiry command data length
Per the SCSI SPC-4 specification, the standard inquiry data length
should not be less than 36 bytes. The current implementation uses 512
bytes, which causes detection failures on some UFS devices (e.g.,
Longsys) that do not expect a transfer length exceeding the standard
inquiry size.
Align the default standard inquiry length with the Linux kernel's
implementation (see drivers/scsi/scsi_scan.c), which uses 36 bytes as
the default. Devices requiring vendor-specific inquiry lengths should
be handled through quirk settings in the future.
Signed-off-by: ht.lin <ht.lin@mediatek.com> Signed-off-by: Macpaul Lin <macpaul.lin@mediatek.com> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Paresh Bhagat [Wed, 11 Feb 2026 09:49:19 +0000 (15:19 +0530)]
configs: Add fragment config for snagfactory tool
Introduce a new fragment configuration in u-boot to enable support for
the snagfactory tool [1], used for factory flashing of boards. Snagfactory
tool first recovers the board via USB DFU (peripheral boot), and then
uses fastboot to flash given binaries/images to MMC or other on-board
memory via USB. The fragment config can be used to generate boot binaries
for board recovery. This fragment config needs to be added additionally,
while building a53 images for USB DFU boot.
The fragment config enables configurations to allow flashing via
fastboot, manage MMC partitions and boot partitions, customize buffer
size and memory usage for fastboot and also integrate OEM commands and
UUU compatibility. It sets CONFIG_BOOTCOMMAND to start fastboot mode
immediately on startup. It also sets BOOTDELAY to 0 to reduce snagfactory
recovery time. Since BOOTCOMMAND and BOOTDELAY configs are being
modified, these changes cannot be placed in existing DFU fragment config.
Snagfactory used mtd support for flashing both SPI NAND and SPI NOR
devices. The fragment config enables mtd in u-boot and also allows SPI
flash to be treated as an MTD device.
Tom Rini [Mon, 16 Mar 2026 14:24:18 +0000 (08:24 -0600)]
Merge patch series "Add PCIe Boot support for TI J784S4 SoC"
Siddharth Vadapalli <s-vadapalli@ti.com> says:
This series adds PCIe endpoint boot support for the TI J784S4 SoC.
Series is based on commit f9ffeec4bdc ("board: toradex: Make A53 get RAM
size from DT in K3 boards") of the master branch of U-Boot.
PCIe Boot Logs (J784S4-EVM running Linux as Root-Complex transfers
bootloaders to another J784S4-EVM configured for PCIe Boot):
https://gist.github.com/Siddharth-Vadapalli-at-TI/2d157003818441fe79a139d0dec1058a
Although the J742S2 EVM supports PCIe boot in Hardware, since it is not
enabled yet in Software, disable PCIe boot related configurations that are
not applicable.
Although the J742S2 EVM supports PCIe boot in Hardware, since it is not
enabled yet in Software, disable PCIe boot related configurations that are
not applicable.
configs: j784s4_evm_a72_defconfig: Enable configs for PCIe boot
J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The
PCIe1 instance is used for PCIe endpoint boot. Enable the configs
required for PCIe boot on the J784S4 platform.
configs: j784s4_evm_r5_defconfig: Enable configs for PCIe boot
J784S4 SoC has two instances of PCIe, namely PCIe0 and PCIe1. The
PCIe1 instance is used for PCIe endpoint boot. Enable the configs
required for PCIe boot on the J784S4 platform.
Additionally, enable configs for J721E WIZ SERDES wrapper, Cadence
Torrent PHY, and MMIO multiplexer. These are required to configure
the SERDES lanes at the R5 SPL stage for PCIe endpoint operation.
phy: ti: Add config to enable J721E WIZ SERDES wrapper at SPL stage
Add SPL_PHY_J721E_WIZ configuration option to enable the WIZ SERDES
wrapper driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.
phy: cadence: Add config to enable Cadence Torrent PHY at SPL stage
Add SPL_PHY_CADENCE_TORRENT configuration option to enable the Cadence
Torrent PHY driver in SPL stage. This is required for PCIe boot support
where SERDES configuration must be done early in the boot sequence
before loading the bootloader image over PCIe.
arm: mach-k3: j784s4: Update SoC autogen data to enable PCIe boot
To enable PCIe boot on J784S4 SoC SERDES0 and PCIE1 should be enabled
and configured at the R5 stage. Add the required clk-data and dev-data
for SERDES0 and PCIE1.
* Require at least 128 KiB of stack space to use EFI sub-system.
* Avoid buffer overrun in efi_var_restore().
* Avoid superfluous variable store writes on unchanged data
* Implement SPI Flash store for EFI variables.
* Add an efidebug ecpt sub-command to display the ECPT table
and a unit test for the command.
Others:
* Add missing include string.h to make exception command build again.
* lib: uuid: add EBBR 2.1 conformance profile GUID
Tom Rini [Tue, 10 Mar 2026 16:26:21 +0000 (10:26 -0600)]
dfu: Make the DFU_WRITE_ALT symbol available outside of DFU
The DFU_WRITE_ALT symbol is used both directly and indirectly (via
UPDATE_COMMON) for EFI capsule updates (FIT or raw), but does not depend
on DFU itself. Move this symbol outside of "if DFU" to remove a Kconfig
dependency problem.
When building qemu_arm64_defconfig with CMD_EXCEPTION a build error occurs:
In file included from cmd/arm/exception64.c:87:
include/exception.h: In function ‘exception_complete’:
include/exception.h:41:23: error: implicit declaration of
function ‘strlen’ [-Wimplicit-function-declaration]
41 | len = strlen(argv[1]);
| ^~~~~~
Add the missing include.
Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Tom Rini <trini@konsulko.com>
Shantur Rathore [Fri, 13 Mar 2026 15:45:27 +0000 (16:45 +0100)]
efi_vars: Implement SPI Flash store
Currently U-Boot uses ESP as storage for EFI variables.
Devices with SPI Flash are used for storing environment with this
commit we allow EFI variables to be stored on SPI Flash.
Signed-off-by: Shantur Rathore <i@shantur.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905D3-CC Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Michal Simek [Fri, 13 Mar 2026 11:20:37 +0000 (12:20 +0100)]
efi_loader: avoid superfluous variable store writes on unchanged data
Every SetVariable() call triggers efi_var_mem_ins() followed by
efi_var_to_storage(), even when the variable value is not actually
changing. This is unfriendly to flash-backed stores that suffer
wear from unnecessary erase/write cycles.
Add a change-detection path to efi_var_mem_ins(): when size2 == 0
(i.e. not an append) and the caller passes a non-NULL changep flag,
look up the existing variable and compare attributes, length, time
and data byte-by-byte. If everything matches, set *changep = false
and return EFI_SUCCESS without touching the variable buffer.
Both efi_set_variable_int() and efi_set_variable_runtime() now
check the flag and skip efi_var_mem_del() / efi_var_to_storage()
when nothing changed.
Introduce efi_memcmp_runtime() - a runtime-safe byte-by-byte memory
comparison helper, following the same pattern as the existing
efi_memcpy_runtime(). The standard memcmp() is not available after
ExitBootServices() and calling it from Linux will crash.
Tested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Vincent Stehlé [Mon, 9 Mar 2026 16:36:35 +0000 (17:36 +0100)]
lib: uuid: add EBBR 2.1 conformance profile GUID
Add support for printing the EFI_CONFORMANCE_PROFILE_EBBR_2_1_GUID as human
readable text.
This is compiled in only when CONFIG_CMD_EFIDEBUG and CONFIG_EFI_EPCT are
set.
Suggested-by: Heinrich Schuchardt <xypron.glpk@gmx.de> Signed-off-by: Vincent Stehlé <vincent.stehle@arm.com> Cc: Tom Rini <trini@konsulko.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
efi_loader: require at least 128 KiB of stack space
The UEFI specification requires at least 128 KiB stack space. Consider this
value as a prerequisite for CONFIG_EFI_LOADER.
Mention the requirement in the CONFIG_STACK_SPACE description and decribe
that the UEFI sub-system uses CONFIG_STACK_SPACE when defining the memory
map.
Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Signed-off-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Jonas Karlman [Mon, 9 Mar 2026 21:02:32 +0000 (21:02 +0000)]
rockchip: rk3568: Include all addressable DRAM in memory map
Rockchip RK356x supports up to 8 GiB DRAM, however U-Boot only includes
the initial 32-bit 0-4 GiB addressable range in its memory map,
something that matches gd->ram_top and current expected memory available
for use in U-Boot.
The vendor DRAM init blobs add following ddr_mem rk atags [1]:
Add the remaining 64-bit 4-8 GiB addressable range, that already is
reported to OS, to the U-Boot memory map to more correctly describe all
available and addressable DRAM of RK356x. While at it also add the
missing UL suffix to the PCIe address range for consistency.
Tom Rini [Fri, 13 Mar 2026 20:59:38 +0000 (14:59 -0600)]
Merge patch series "k3_*: Add config fragments for inline ECC and BIST"
Neha Malcom Francis <n-francis@ti.com> says:
Typically we do not enable these configs by default but would still like to
have the option to start building them in our default build flow for
testing. Also there is the added advantage of users being able to see what
is needed in case they choose to enable these features.
projects / thirdparty / u-boot.git / log
