rockchip: px30: Fix hard dependency to DEBUG_UART_BOARD_INIT
Because DEBUG_UART_BOARD_INIT depends on DEBUG_UART, hard dependency
to DEBUG_UART_BOARD_INIT in ROCKCHIP_PX30 can cause warnings if
DEBUG_UART is disabled.
The DEBUG_UART_BOARD_INIT is already implied by ARCH_ROCKCHIP entry.
Remove hard dependency from ROCKCHIP_PX30, so that it will be
consistent with other rockchip boards.
debug_uart: Replace debug functions with dummies if CONFIG_DEBUG_UART is not set
In case DEBUG UART is not used, define dummy macros replacing
the actual function implementations that will not be available.
This allows to compile code and avoid linker errors.
Redefine the DEBUG_UART_FUNCS macro if DEBUG UART is not available,
to avoid compilation errors.
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
ram: rockchip: Fix dependency of RAM_ROCKCHIP_DEBUG
The RAM_ROCKCHIP_DEBUG can be used only if DEBUG_UART is
available.
The next commit introduces changes in definition of debug
uart functions, so that DEBUG_UART is required to be defined
in order to initialize uart and use print functions.
efi: stub: Change _debug_uart_putc function to inline
Update definition of _debug_uart_putc to static inline.
This will allow to avoid compilation warnings about unused code
after introduction of patch changing debug uart functions to
dummies if CONFIG_DEBUG_UART is not set.
This also matches the instructions in include/debug_uart.h and
provides consistency with implementations for other platforms.
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
arm: uniphier: Change _debug_uart_putc function to inline
Update the definition of _debug_uart_putc to static inline.
This matches the instructions in include/debug_uart.h and
provides consistency with implementations for other platforms.
Signed-off-by: Lukasz Czechowski <lukasz.czechowski@thaumatec.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Heiko Thiery [Wed, 28 May 2025 09:05:37 +0000 (11:05 +0200)]
arm: dts: remove k3-serdes.h
This file is a duplicate and also comes with the sync of the linux
mainline dts files. By removing this the one from the dts folder should
be taken that is more up-to-date.
cmd: bootmenu: permit to select bootmenu entry with a shortcut
Permit to select a bootmenu entry with a key shortcut. This is
especially useful in production or testing scenario to automate flashing
procedure or testing procedure.
The boot entry are changed to append the shortcut key to it.
Example:
1. Run default boot command.
2. Boot system via TFTP.
3. Boot production system from NAND.
4. Boot recovery system from NAND.
5. Load production system via TFTP then write to NAND.
6. Load recovery system via TFTP then write to NAND.
7. Load BL31+U-Boot FIP via TFTP then write to NAND.
8. Load BL2 preloader via TFTP then write to NAND.
9. Reboot.
a. Reset all settings to factory defaults.
0. Exit
0 is always reserved for Exit to console.
On pressing the keyboard key 2, the bootmenu entry 2 is selected and
executed.
Up to 34 key shortcut (0 excluded as reserved) are supported from 1-9
and a-z.
If a shortcut key not present in the bootmenu list is pressed, it is
simply ignored and eventually the autoboot is interrupted.
Capital A-Z are converted to lower a-z and the related option is
selected.
Suggested-by: Weijie Gao <weijie.gao@mediatek.com> Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> Tested-by: Petr Štetiar <ynezz@true.cz>
The high-speed UART from MediaTek supports baudrate accuracy
compensation when using high-speed mode 3.
This is done by calculating the first digit of the fraction part of
sample count value. The fraction value will be then used as the
reference to insert 0 to 10 sample cycle(s) to one frame (assume
that frame format is 8n1, i.e. 10 bits per frame).
The fracdiv_[l/m] registers are used to determine whether a bit in one frame
should be inserted with one sample cycle.
With typical 40MHz source clock, the actual baudrates with/without
accuracy compensation are:
Andrew Davis [Thu, 22 May 2025 16:40:13 +0000 (11:40 -0500)]
board: ti: am62ax: env: Use default MMC related args
There are common MMC args for TI plats in include/environment/ti/mmc.env.
Since we already include this, there is no need to redefine these
MMC vars. Use the defaults.
This seems like something that could have been done while refactoring
these vars in the first place as it happened after this AM62A file
was available hence the fixes tag.
Reported-by: Chirag Shilwant <c-shilwant@ti.com> Fixes: 3709b529156e ("env: ti: mmc.env: Move mmc related args to common place") Signed-off-by: Andrew Davis <afd@ti.com> Reviewed-by: Neha Malcom Francis <n-francis@ti.com> Acked-by: Chirag Shilwant <c-shilwant@ti.com> Reviewed-by: Judith Mendez <jm@ti.com>
usb: onboard-hub: Fix return type for regulator APIs
Apart from ENOENT observing return value as ENOSYS when
!DM_REGULATOR that's why cover both configurations.
Changed code is not working as operation should be "&&"
not "||" (ret != -ENOENT && ret != -ENOSYS).
Also fix the remove function where the regulator_set_enable_if_allowed()
function is returning an error.
Parth Pancholi [Mon, 19 May 2025 15:47:45 +0000 (16:47 +0100)]
board: toradex: add verdin am62p support
This adds initial support for the Toradex Verdin AM62P module.
The module consists of an TI AM62P family SoC, a TPS65219 PMIC, a
Gigabit Ethernet PHY, up to 8GB of LPDDR4 RAM, an eMMC, a TLA2024 ADC,
an I2C EEPROM, an RX8130 RTC, plus an optional Bluetooth/Wi-Fi module.
These specific changes adds support for Toradex Verdin AM62P Quad 2GB WB
IT module.
implement a driver to use semtech pinctrl and
gpio expander, this driver is adapted from a
existent linux driver that is written by
Gregory Bean <gbean@codeaurora.org>.
Anton Moryakov [Fri, 16 May 2025 15:25:38 +0000 (18:25 +0300)]
tools: fix handle leak in ifdtool.c
Prevent file descriptor leaks by properly closing 'fd' and 'new_fd'
when fstat() or write() operations fail.
- Added close(fd) before return in open_for_read() if fstat() fails.
- Added close(new_fd) before return in write_image() if write() fails.
- No close needed if open() fails (fd == -1 is invalid).
Signed-off-by: Anton Moryakov <ant.v.moryakov@gmail.com> Reviewed-by: Quentin Schulz <quentin.schulz@cherry.de>
Tom Rini [Tue, 3 Jun 2025 15:00:52 +0000 (09:00 -0600)]
Merge tag 'qcom-more-for-2025.07' of https://source.denx.de/u-boot/custodians/u-boot-snapdragon
More Qualcomm fixes for 2025.07
* Adjust fdtfile logic to support more boards
* Support linux,code variable in qcom-pmic button driver
* Minor CLK API adjustments and apq8096/msm8916 fixes
* vbus regulator register fixes
* dragonboard410c KASLR support and other fixes
Tom Rini [Mon, 2 Jun 2025 23:43:56 +0000 (17:43 -0600)]
Merge patch series "Audit include list for include/[a-m]*.h"
Tom Rini <trini@konsulko.com> says:
Hey all,
Related to my other series I've posted recently on cleaning up some
headers, this series here is the result of at least lightly auditing the
#includes used in include/[a-m]*.h. This ignores subdirectories, as at
least in part I think the top-level includes we've constructed are the
most likely places to have some extra transitive include paths. I'm sure
there's exceptions and I'll likely audit deeper once this first pass is
done. This only gets as far as "include/m*.h" because I didn't want this
to get too big. This also sets aside <miiphy.h> and <phy.h>. While
miiphy.h does not directly need <phy.h> there are *so* many users and I
think I had half of the tree just about not building when I first tried.
It might be worth further investigation, but it might just be OK as-is.
Tom Rini [Wed, 21 May 2025 22:51:22 +0000 (16:51 -0600)]
global: Cleanup usage of "ETH_ALEN"
The value of "ETH_ALEN" is defined to 6 in <linux/if_ether.h>. This file
is included in <net.h>. In the places where we had ETH_ALEN but no
direct include of <net.h>, add <linux/if_ether.h>. In the places where
we had a custom name used, make use of ETH_ALEN instead.
Tom Rini [Wed, 21 May 2025 22:51:21 +0000 (16:51 -0600)]
include/mtd.h: Cleanup usage
There are only a few things found in <mtd.h> today. Go through and audit
the C files which include <mtd.h> and remove it when not required. Then,
add it to the files which had either missed it or had an indirect
inclusion of it.
Tom Rini [Wed, 21 May 2025 22:51:20 +0000 (16:51 -0600)]
include/mmc.h: Audit include list
This file does not need <linux/sizes.h> nor <linux/compiler.h> so remove
them. This exposes however that a number of other files had been relying
on this implicit include for <linux/sizes.h> so add that where needed.
Tom Rini [Wed, 21 May 2025 22:51:19 +0000 (16:51 -0600)]
include/ide.h: Cleanup usage
At this point in time, <ide.h> provides the IDE_BUS macro and the
function prototype for ide_set_reset, which is used with IDE_RESET. The
only files which should include this header are the ones that either use
that macro or that function. Remove <blk.h> from <ide.h> and remove
<ide.h> from places which do not need it.
Tom Rini [Wed, 21 May 2025 22:51:17 +0000 (16:51 -0600)]
include/efi_loader.h, include/efi_tcg2.h: Audit include list
In include/efi_loader.h we do not directly need <log.h>, <part_efi.h>,
<pe.h> nor <linux/oid_registry.h> so remove them. In include/efi_tcg2.h
we make use of <part_efi.h> but did not include it, so add it directly.
Tom Rini [Wed, 21 May 2025 22:51:08 +0000 (16:51 -0600)]
include/bios_emul.h: Audit include list
This file does not need <pc.h> but does directly need
<linux/types.h>. Furthermore, arch/x86/lib/bios.c was getting <pci.h>
via <bios_emul.h> so add it there.
Marek Vasut [Sun, 18 May 2025 16:02:58 +0000 (18:02 +0200)]
ARM: Align image end to 8 bytes to fit DT alignment
Align U-Boot image end to 8 bytes to make sure DT alignment requirement
is fulfilled. This fixes a possible failure in fdt_find_separate() in
case the U-Boot image is aligned to 4 Bytes and DT is appended at the
end at already 8 Byte aligned offset.
Link: https://source.denx.de/u-boot/u-boot/-/issues/30 Reviewed-by: Simon Glass <sjg@chromium.org> Reviewed-by: Tom Rini <trini@konsulko.com> Signed-off-by: Marek Vasut <marek.vasut@mailbox.org>
Sumit Garg [Mon, 5 May 2025 12:43:33 +0000 (18:13 +0530)]
mach-snapdragon: Update fdtfile logic to work for RB1 and RB2
RB1 and RB2 have three root compatibles where the last one can't be used
to decode fdtfile name (qcm* vs qrb*). So rather just rely on the first
compatible to retrieve the SoC name.
button: qcom-pmic: allow to specify code in devicetree
Most device vendors put "Volume Down" button onto PMIC RESIN.
But Sony is special: see
dts/upstream/src/arm64/qcom/sdm630-sony-xperia-nile.dtsi or [1].
They put "Volume Down" on PMIC GPIO 7 where others usually put
"Volume Up", and KEY_VOLUMEUP is inside &pon_resin.
Currently if you boot U-Boot on such Sony device, you end up
with 2 "Volume Down" buttons, and no "Volume Up", which makes
navigating menu problematic.
Support reading devicetree "linux,code" property and override
statically defined button code & label based on that.
Stephan Gerhold [Thu, 24 Apr 2025 09:16:46 +0000 (11:16 +0200)]
clk: qcom: apq8016: Fix SDCC clock warnings
As of commit dc8754e8e408 ("clk/qcom: apq8016: improve clk_enable logging")
there are now warnings in the U-Boot console on DragonBoard 410c:
apq8016_clk_enable: unknown clk id 122
apq8016_clk_enable: unknown clk id 123
apq8016_clk_enable: unknown clk id 124
apq8016_clk_enable: unknown clk id 125
This is because we don't implement enable() properly for the SDCC clocks.
Currently they are being enabled as part of set_rate().
Fix this by moving the enable calls out of the apq8016_clk_init_sdc()
function and convert them to the equivalent GATE_CLK_POLLED() definitions.
Stephan Gerhold [Thu, 24 Apr 2025 09:16:44 +0000 (11:16 +0200)]
clk: qcom: Allow polling for clock status in qcom_gate_clk_en()
GATE_CLK() in its current state is unsafe: A simple write to the clock
enable register does not guarantee that the clock is immediately running.
Without polling the clock status, we may issue writes to registers before
the necessary clocks start running. This doesn't seem to cause issues in
U-Boot at the moment, but for example removing the CLK_OFF polling in TF-A
for the SMMU clocks on DB410c reliably triggers an exception during boot.
Make it possible to poll the branch clock status register, by adding a new
GATE_CLK_POLLED() macro that takes the extra register address. Existing
usages work just as before, without polling the clock status. Ideally all
usages should be updated to specify the correct poll address in the future.
The Qualcomm naming for these clocks is "branch" and not "gate", but let's
keep the existing naming for now to avoid confusion until all others
drivers have been converted.
Stephan Gerhold [Thu, 24 Apr 2025 09:16:43 +0000 (11:16 +0200)]
clk: qcom: Use setbits_le32() for qcom_gate_clk_en()
The other clock enable functions in clock-qcom.c use setbits_le32() to
read/modify/write the enable registers. Use the same for qcom_gate_clk_en()
to simplify the code a bit.
Stephan Gerhold [Thu, 24 Apr 2025 09:16:41 +0000 (11:16 +0200)]
clk: qcom: apq8016: Fix SDCC clock addresses
The SDCC_...(n) macros in clock-apq8016.c result in the wrong addresses:
- SDCC1: SDCC_APPS_CBCR(0) = ((0 * 0x1000) + 0x41018) = 0x41018
Should be 0x42018, this is an invalid register close to the USB clocks.
- SDCC2: SDCC_APPS_CBCR(1) = ((1 * 0x1000) + 0x41018) = 0x42018
Should be 0x43018, this is the SDCC1 clock.
When we try to enable SDCC2, we actually end up enabling SDCC1. When we try
to enable SDCC1, we just issue some broken register writes.
This hasn't caused any trouble so far, because the boot firmware is keeping
both SDCC clocks running. However, if these clocks are disabled when
entering U-Boot, MMC initialization is failing.
Fix this by using the proper offset for the macros. The SDCC_CMD_RCGR() was
already correct, but change it the same way for consistency.
Fixes: 085921368b7d ("arm: Add support for Qualcomm Snapdragon family") Reviewed-by: Neil Armstrong <neil.armstrong@linaro.org> Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org> Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Reviewed-by: Casey Connolly <casey.connolly@linaro.org> Link: https://lore.kernel.org/r/20250424-apq8016-clock-fixes2-v2-1-fcc371c9e45f@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Stephan Gerhold [Thu, 17 Apr 2025 13:49:12 +0000 (15:49 +0200)]
board: dragonboard410c: Drop custom reduced malloc size
At the moment, the dragonboard410c_defconfig specifies a custom
SYS_MALLOC_LEN, lower than the default for Qualcomm boards defined in
arch/arm/mach-snapdragon/Kconfig. It looks like it's too low, since
flashing larger sparse partition images using Fastboot fails with:
Stephan Gerhold [Thu, 17 Apr 2025 13:49:11 +0000 (15:49 +0200)]
board: dragonboard410c: Fix button cmd name
Commit 359e1d4a57e0 ("board: dragonboard410c: Use button_cmd instead of
custom code") was made in parallel with commit 8f5685d5d32f ("button:
qcom-pmic: prettify and standardise button labels"), which changed the
default button label from "vol_down" to "Volume Down". This is causing
errors in the console during boot now:
No button labelled 'vol_down'
Fix this by using the new label.
Fixes: 359e1d4a57e0 ("board: dragonboard410c: Use button_cmd instead of custom code") Fixes: 8f5685d5d32f ("button: qcom-pmic: prettify and standardise button labels") Signed-off-by: Stephan Gerhold <stephan.gerhold@linaro.org>
Reviewed-by: Reviewed-by: Sumit Garg <sumit.garg@oss.qualcomm.com> Link: https://lore.kernel.org/r/20250417-db410c-fixes2-v1-1-76ad994da152@linaro.org Signed-off-by: Casey Connolly <casey.connolly@linaro.org>
Usb gadget:
dwc2: Fix incorrect ULPI_UTMI_SEL bit setting
dwc2: Fix HBstLen setting for external DMA mode
dwc2: Various refactors to get the code closer to Linux
dwc2: Support reset logic for v4.20a
Tom Rini [Mon, 2 Jun 2025 14:42:04 +0000 (08:42 -0600)]
Merge tag 'i2cfixes-for-2025.07-rc4' of https://source.denx.de/u-boot/custodians/u-boot-i2c
i2c bugfixes for v2025.07-rc4
- designware_i2c: fix globally wrong return value -1 into -ETIMEDOUT
in driver, which leaded in silent errors as a timeout resulted in
an uninitialized value being returned, potentially causing
unexpected behavior.
i2c: designware_i2c Return -ETIMEDOUT for timeout errors
Change the return value for timeout errors in i2c-designware from 1 to
-ETIMEDOUT. Returning errors as negative values is standard practice in the
u-boot, which enhances error handling consistency across the codebase.
The current behavior can lead to silent errors when functions check for
negative return values to identify errors. For example, in
`dm_i2c_reg_read` from i2c-uclass.c, a timeout results in an uninitialized
value being returned, potentially causing unexpected behavior.
Cc: Heiko Schocher <hs@denx.de> Cc: Tom Rini <trini@konsulko.com> Cc: Wojciech Szamocki <wojciech.szamocki@nokia.com> Signed-off-by: Wojciech Szamocki <wojciech.szamocki@nokia.com> Reviewed-by: Heiko Schocher <hs@denx.de>
Junhui Liu [Sun, 26 Jan 2025 08:29:59 +0000 (00:29 -0800)]
usb: dwc2: Refactor register operations with clrsetbits macros
Refactor DWC2 USB gadget driver to replace manual read-modify-write
operations with `clrsetbits_le32`, `setbits_le32`, and `clrbits_le32`
macros, which simplify the code and improve readability.
Kongyang Liu [Fri, 10 Jan 2025 13:55:27 +0000 (21:55 +0800)]
usb: dwc2: Replace uint<x>_t types with u<x>
Updates all instances of uint8_t, uint16_t, and uint32_t to u8, u16, and
u32 respectively, ensuring consistent use of kernel-preferred types and
resolving checkpatch.pl warnings.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-8-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Kongyang Liu [Fri, 10 Jan 2025 13:55:26 +0000 (21:55 +0800)]
usb: dwc2: Unify flush and reset logic with v4.20a support
This patch merges flush and reset logic for both host and gadget code
into a common set of functions, reducing duplication. It also adds support
for the updated reset logic to compatible with core version since v4.20a.
Kongyang Liu [Fri, 10 Jan 2025 13:55:25 +0000 (21:55 +0800)]
usb: dwc2: Extract macro definitions to common header
Some macros are shared between host and gadget code, causing duplicated
definitions. Move DWC2 macro definitions from host and gadget code into a
common header to reduce duplication.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-6-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Kongyang Liu [Fri, 10 Jan 2025 13:55:24 +0000 (21:55 +0800)]
usb: dwc2: Align macros with Linux kernel definitions
Update the DWC2 macros to match those used in the Linux kernel, making
it easier to synchronize updates with kernel. Also removed some unused
macros to cleanup the code.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-5-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Kongyang Liu [Fri, 10 Jan 2025 13:55:23 +0000 (21:55 +0800)]
usb: dwc2: Clean up with bitfield macros
Use FIELD_PREP, FIELD_GET, BIT, and GENMASK macros to standardize bit
manipulation across the DWC2 code, improving readability and
maintainability without altering functionality.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Tested-by: Peter Robinson <pbrobinson@gmail.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-4-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Kongyang Liu [Fri, 10 Jan 2025 13:55:22 +0000 (21:55 +0800)]
usb: dwc2: Fix HBstLen setting for external DMA mode
The loop used to calculate HBstLen for extern DMA mode does not produce
the correct result according to the datasheet [1]. Replacing that loop
with a direct calculation using LOG2 to correctly assign the burst length
in the GAHBCFG register for external DMA mode.
Junhui Liu [Fri, 10 Jan 2025 13:55:21 +0000 (21:55 +0800)]
usb: dwc2: Fix incorrect ULPI_UTMI_SEL bit setting
The ULPI_UTMI_SEL bit in the DWC2 driver was set incorrectly. According
to the datasheet [1], this bit should be set to 0 for UTMI interface and 1
for ULPI interface. The existing code had this logic reversed,
causing the interface selection to be incorrect.
This commit corrects the ULPI_UTMI_SEL bit setting to match the
datasheet's description. Referencing the kernel's code [2] also confirms
this fix.
Kongyang Liu [Fri, 10 Jan 2025 13:55:20 +0000 (21:55 +0800)]
usb: dwc2: Extract register definitions to common header file
The same registers are accessed in both the otg and gatet drivers of
dwc2, and these registers are repeatedly defined in these two parts.
Extract register definitions into a common header file to reduce
redundancy and make the code more maintainable.
Signed-off-by: Kongyang Liu <seashell11234455@gmail.com> Reviewed-by: Marek Vasut <marex@denx.de> Tested-by: Peter Robinson <pbrobinson@gmail.com> Reviewed-by: Mattijs Korpershoek <mkorpershoek@baylibre.com> Signed-off-by: Junhui Liu <junhui.liu@pigmoral.tech> Link: https://lore.kernel.org/r/20250110-dwc2-dev-v4-1-987f4fd6f8b2@pigmoral.tech Signed-off-by: Mattijs Korpershoek <mkorpershoek@kernel.org>
Martin Kaistra [Tue, 15 Apr 2025 15:04:00 +0000 (17:04 +0200)]
net: gem: ignore tx_clk if MII is used
If the MII interface is used, the PHY is the clock master, thus don't
set the clock rate. On Zynq-7000, this will prevent the following
error:
zynq_gem ethernet@e000b000: failed to set tx clock rate 25000000
phy: zynqmp: Fix sgmii clk ctrl GTR lane bit shift
The bitshift in GEM_CLK_CTRL register is five bits, not two. There are
four bits for each GEM, and one bit reserved in between.
This has caused that using more than one GEM is impossible,
additionally corrupting the GEM0's configuration, leaving GEM0
unusable as well (ie. if GEM0 and GEM1 are used, GEM1 configuration is
going to write to GEM0's registers wrong value, leaving GEM0 unusable)
drivers: fpga: intel_sdm_mb: Flush cache before FPGA configuration
FPGA configuration encounters failure when the cache is not flushed.
Add cache flushing to the memory region that holds the FPGA
configuration bitstream.
The pcireg base is not assigned to any address, reading the
pcireg base with PS_LINKUP_OFFSET which is incorrect and
giving random values. So update the pcireg base from
devicetree so that we can read the valid PCIE link status
and PHY ready status.
Introduce the BSH SystemMaster (SMM) M2B board. Notably, the M2B is
designed to leverage the existing device tree of its predecessor, the M2.
The primary distinction arises from memory incompatibilities with the M2.
To address this, we've implemented a configuration system that allows for
selective inclusion of the desired memory components.
Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Add i.MX6UL clk driver for i.MX6UL CLK driver model usage
Reviewed-by: Peng Fan <peng.fan@nxp.com> Reviewed-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Tested-by: Christoph Niedermaier <cniedermaier@dh-electronics.com> Signed-off-by: Michael Trimarchi <michael@amarulasolutions.com>
Tim Harvey [Fri, 23 May 2025 17:20:15 +0000 (10:20 -0700)]
board: venice: add FSA support
The Gateworks Flexible Socket Adapters adapt common
busses such as SDIO/UART/USB/PCI to various connectors
such as M.2 B-Key, M.2 E-Key, M.2 M-Key, and MiniPCIe.
Each FSA has an EEPROM onboard describing its details as well as an
optional port-expander for configurable GPIO's.
Add support for identifying the FSA's and configuring their
details such as user description and GPIO's:
- enable pca953x, pca954x and eeprom support for communicating
with the I2C eeprom and gpio port expander on the FSA
- add FSA detection support
- add FSA gpio configuration support
Each FSA is identified in the device-tree by an alias to it's I2C
bus where an eeprom@54 node must exist as well as an gpio@20 node
for an io-expander. These nodes must be enabled so that
they can be probed to determine if they are actually present in
the system. If not present or not enabled the gpio expander can
not be used. This also requires livetree as the gpio expander
node if not present must be disabled.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tim Harvey [Fri, 23 May 2025 17:20:14 +0000 (10:20 -0700)]
board: venice: add imx8mp-gw82xx support
The Gateworks GW82XX-2X is an ARM based single board computer (SBC)
comprised of the i.MX8M Plus based gw702x SoM and the gw82xx
baseboard featuring:
- i.MX8M Plus SoC
- LPDDR4 DRAM
- eMMC FLASH
- Gateworks System Controller (GSC)
- microSD (1.8V/3.3V Capable)
- panel status bi-color LED
- pushbutton switch
- fan controller with tachometer
- USB Type-C connector
- PCIe switch
- 2x GbE RJ45 connectors
- multi-protocol RS232/RS485/RS422 Serial ports
- 2x Flexible Socket Adapters with SDIO/UART/USB/PCIe
(for M.2 and miniPCIe expansion)
- 2x isolated CAN
- GPS
- accelerometer
- magnetometer
- off-board connectors for: SPI, GPIO, I2C, ADC
- Wide range DC power input
- support for 802.3at PoE (via adapter)
Add support for it by providing its device-tree.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tim Harvey [Fri, 23 May 2025 17:20:13 +0000 (10:20 -0700)]
board: venice: flip logic for GSC supervisor enable
Flip the logic used to determine if a board has the proper hardware to
support enabling the GSC voltage supervisor so that we do not need to
keep adding new models to the list.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tim Harvey [Fri, 23 May 2025 17:20:10 +0000 (10:20 -0700)]
board: venice: fix dram size for GW7901-SP486
The GW7901-SP486 with the exception of the -C revision has 2GB DRAM
loaded but incorrectly specifies 1GB in the EEPROM. Adjust the DRAM size
to account for this.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
Tim Harvey [Fri, 23 May 2025 17:20:09 +0000 (10:20 -0700)]
board: venice: fix dram bus config for GW7902/GW7903/GW7904
The GW7902/GW7903/GW7904 have an alternate databus layout affecting a few
of the DDRC and DDR PHY registers.
The 512MB configuration used this alternate bus layout. Change
the 512MB config to the standard bus configuration and add a generic
function to patch the DDRC/PHY configs for the alternate bus layout.
Signed-off-by: Tim Harvey <tharvey@gateworks.com> Reviewed-by: Peng Fan <peng.fan@nxp.com>
projects / thirdparty / u-boot.git / log
