Julien Stephan [Mon, 2 Feb 2026 12:41:49 +0000 (13:41 +0100)]
clk: mediatek: mt8188: remove separate topckgen-cg driver
Remove the separate topckgen-cg driver for handling clock gates in the
topckgen address space.
Commit 8aeeeff50d46 ("clk: mediatek: allow gates in topckgen drivers")
added support for gates in topckgen driver.
This commit fixes MT8188 driver, the same way commit ba207d7f54f9 ("clk:
mediatek: mt8365: remove separate topckgen-cg driver") does for MT8365.
Signed-off-by: Julien Stephan <jstephan@baylibre.com>
Tom Rini [Wed, 18 Feb 2026 17:57:24 +0000 (11:57 -0600)]
Merge patch series "arm: mediatek: clean up some redundant board init"
David Lechner <dlechner@baylibre.com> says:
Before adding more targets, we take a moment to clean up some some
redundant code in existing Mediatek SoC support.
The first three patches are removing no-op functions. The last patch
generalizes the mem_map code so that it can be shared between all
Mediatek ARMv8 SoCs.
Add a CONFIG_MTK_MEM_MAP_DDR_BASE_PHY variable to specify the DDR base
physical address for the Mediatek ARMv8 memory map. This will be used
by MT8196 in the future which has a different DDR base address than
other Mediatek SoCs.
Signed-off-by: David Lechner <dlechner@baylibre.com> Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
David Lechner [Mon, 9 Feb 2026 16:39:31 +0000 (10:39 -0600)]
arm: mediatek: consolidate ARMv8 memory maps
Consolidate all mem_map definitions for MediaTek ARMv8 platforms into a
single file. The size of the DDR and MMIO regions can vary, so Kconfig
options are added to configure them by target.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Mon, 9 Feb 2026 16:39:30 +0000 (10:39 -0600)]
board/mediatek: move EVK MAINTAINERS to common file
Move the mt8365_evk and mt8390_evk MAINTAINERS files to a common
MAINTAINERS file. We will be deleting the board-specific directories
soon but we need to keep the MAINTAINERS for the defconfig entries.
Signed-off-by: David Lechner <dlechner@baylibre.com>
David Lechner [Mon, 9 Feb 2026 16:39:29 +0000 (10:39 -0600)]
arm: mediatek: make mtk_pll_early_init() static
Make the mtk_pll_early_init() function static in several files. It is
only used within those files, so there is no need to have it in the
global namespace.
Reviewed-by: Macpaul Lin <macpaul.lin@mediatek.com>
David Lechner [Mon, 9 Feb 2026 16:39:26 +0000 (10:39 -0600)]
arm: mediatek: use default weak mtk_soc_early_init()
Add a weak default implementation of mtk_soc_early_init() in spl.c to
avoid having to define it in every SoC init.c file that does not need
any additional early initialization.
The init.h header file is no longer needed in this case and is removed.
Signed-off-by: David Lechner <dlechner@baylibre.com>
Tom Rini [Wed, 18 Feb 2026 14:27:58 +0000 (08:27 -0600)]
Merge patch series "Implement all missing SMBIOS types required by distro tooling"
Raymond Mao <raymondmaoca@gmail.com> says:
From: Raymond Mao <raymond.mao@riscstar.com>
This series finish the last missing puzzle of required SMBIOS types by:
1) Fixing duplicated handles when multiple instances exist in one type;
2) Implementing the rest of required types 9/16/17/19;
3) Adding version control when printing properties for all types.
Type 9/16/17/19 are generally DT-based, the idea is to write these tables
using a hybrid approach:
Explicit DT definitions under existing '/smbios/smbios' take precedence,
with fallback to scan and interpret values from the entire DT.
Moreover, all below APIs:
smbios_get_val_si()
smbios_get_u64_si()
smbios_add_prop_si()
are on top of sysinfo, thus allow vendors to get values from other
subsystems by implementing their own sysinfo driver if needed.
Raymond Mao [Fri, 13 Feb 2026 22:52:50 +0000 (17:52 -0500)]
smbios: add support for dynamic generation of Type 19 table
This commit implements SMBIOS Type 19 (Memory Array Mapped Address)
generation with a hybrid approach supporting both:
1. Explicit definition via Device Tree 'smbios' node:
Child node under '/smbios/smbios/memory-array-mapped-address' will be
used to populate as individual Type 19 structure directly.
- Properties follow SMBIOS field names with lowercase letters and
hyphen-separated words (e.g., 'starting-address', 'ending-address',
'partition-width', etc.).
- This method supports precise platform-defined overrides and system
descriptions.
2. Fallback to automatic DT-based discovery:
If child node under '/smbios/smbios/memory-array-mapped-address' does
not exist, the implementation will:
- Scan all top-level 'memory@' nodes to populate Type 19 structure with
inferred size and location data.
- Scan nodes named or marked as 'memory-controller' and parse
associated 'dimm@' subnodes (if present) to extract DIMM sizes and
map them accordingly.
This dual-mode support enables flexible firmware SMBIOS reporting while
aligning with spec-compliant naming and runtime-detected memory topology.
Type 19 support is under GENERATE_SMBIOS_TABLE_VERBOSE to avoid
increasing rom size for those platforms which only require basic SMBIOS
support.
Signed-off-by: Raymond Mao <raymondmaoca@gmail.com> Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Fri, 13 Feb 2026 22:52:49 +0000 (17:52 -0500)]
smbios: add support for dynamic generation of Type 17 table
This commit implements SMBIOS Type 17 (Memory Device) generation with a
hybrid approach supporting both:
1. Explicit definition via Device Tree 'smbios' node:
Child node under '/smbios/smbios/memory-device' will be used to
populate as individual Type 17 structure directly.
- Properties follow SMBIOS field names with lowercase letters and
hyphen-separated words (e.g., 'physical-memory-array-handle',
' memory-error-information-handle', 'configured-memory-speed', etc.).
- This method supports precise platform-defined overrides and system
descriptions.
2. Fallback to automatic DT-based discovery:
If child node under '/smbios/smbios/memory-device' does not exist,
the implementation will:
- Scan all top-level 'memory@' nodes to populate Type 17 structure with
inferred size and location data.
- Scan nodes named or marked as 'memory-controller' and parse
associated 'dimm@' subnodes (if present) to extract DIMM sizes and
map them accordingly.
This dual-mode support enables flexible firmware SMBIOS reporting while
aligning with spec-compliant naming and runtime-detected memory topology.
Type 17 support is under GENERATE_SMBIOS_TABLE_VERBOSE to avoid
increasing rom size for those platforms which only require basic SMBIOS
support.
Signed-off-by: Raymond Mao <raymondmaoca@gmail.com> Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Fri, 13 Feb 2026 22:52:48 +0000 (17:52 -0500)]
smbios: add support for dynamic generation of Type 16 table
This commit implements SMBIOS Type 16 (Physical Memory Array)
generation with a hybrid approach supporting both:
1. Explicit definition via Device Tree 'smbios' node:
Child node under '/smbios/smbios/memory-array' will be used to
populate as individual Type 16 structure directly.
- Properties follow SMBIOS field names with lowercase letters and
hyphen-separated words (e.g., 'memory-error-correction',
'maximum-capacity', 'extended-maximum-capacity', etc.).
- This method supports precise platform-defined overrides and system
descriptions.
2. Fallback to automatic DT-based discovery:
If child node under '/smbios/smbios/memory-array' does not exist,
the implementation will:
- Scan all top-level 'memory@' nodes to populate Type 16 structure with
inferred size and location data.
- Scan nodes named or marked as 'memory-controller' and parse
associated 'dimm@' subnodes (if present) to extract DIMM sizes and
map them accordingly.
This dual-mode support enables flexible firmware SMBIOS reporting while
aligning with spec-compliant naming and runtime-detected memory topology.
Type 16 support is under GENERATE_SMBIOS_TABLE_VERBOSE to avoid
increasing rom size for those platforms which only require basic SMBIOS
support.
Signed-off-by: Raymond Mao <raymondmaoca@gmail.com> Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Fri, 13 Feb 2026 22:52:47 +0000 (17:52 -0500)]
smbios: add support for dynamic generation of Type 9 system slot tables
This commit introduces support for generating SMBIOS Type 9 (System Slot)
tables using a hybrid approach:
1. Explicit Device Tree definitions:
Child node under '/smbios/smbios/system-slot' will be interpreted as
individual slot definitions.
- Each child represents a slot (e.g., isa, pcmcia, etc.).
- Properties follow the SMBIOS specification using lowercase
hyphen-separated names such as 'slot-type', 'slot-id',
'segment-group-number', 'bus-number', 'slot-information', etc.
- This approach allows full customization of each system slot and is
especially suitable for platforms with well-defined slot topology.
2. Automatic detection fallback:
If child node under '/smbios/smbios/system-slot' does not exist, the
implementation will scan the entire device tree for nodes whose
'device_type' matches known slot-related types ("pci", "isa", "pcmcia",
etc.).
- When a match is found, default values or heuristics are applied to
populate to the System Slot table.
- This mode is useful for platforms that lack explicit SMBIOS nodes
but still expose slot topology via standard DT conventions.
Together, two approaches ensure that SMBIOS Type 9 entries are available
whether explicitly described or automatically derived.
Signed-off-by: Raymond Mao <raymondmaoca@gmail.com> Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Raymond Mao [Fri, 13 Feb 2026 22:52:46 +0000 (17:52 -0500)]
smbios: Fix duplicated smbios handles
Some smbios types can have multiple instances (e.g. Type 7, 9, 16, 17,
19), thus the 'handle' argument should be a pointer so that the value
can be accumulated when writing all the instances.
This also fix the observed duplicated Type 7 handles.
Fixes: bcf456dd369e ("smbios: add detailed smbios information") Signed-off-by: Raymond Mao <raymondmaoca@gmail.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Tom Rini [Tue, 17 Feb 2026 19:51:26 +0000 (13:51 -0600)]
Merge patch series "treewide: Clean up usage of DECLARE_GLOBAL_DATA_PTR"
Peng Fan (OSS) <peng.fan@oss.nxp.com> says:
This patch set primarily removes unused DECLARE_GLOBAL_DATA_PTR
instances.
Many files declare DECLARE_GLOBAL_DATA_PTR and include
asm/global_data.h even though gd is never used. In these cases,
asm/global_data.h is effectively treated as a proxy header, which is
not a good practice.
Following the Include What You Use principle, files should include
only the headers they actually depend on, rather than relying on
global_data.h indirectly. This approach is also adopted in Linux kernel
[1].
The first few patches are prepartion to avoid building break after
remove the including of global_data.h.
A script is for filtering the files:
list=`find . -name "*.[ch]"`
for source in ${list}
do
result=`sed -n '/DECLARE_GLOBAL_DATA_PTR/p' ${source}`
if [ "${result}" == "DECLARE_GLOBAL_DATA_PTR;" ]; then
echo "Found in ${source}"
result=`sed -n '/\<gd\>/p' ${source}`
result2=`sed -n '/\<gd_/p' ${source}`
result3=`sed -n '/\<gd->/p' ${source}`
if [ "${result}" == "" ] && [ "${result2}" == "" ] && [ "${result3}" == "" ];then
echo "Cleanup ${source}"
sed -i '/DECLARE_GLOBAL_DATA_PTR/{N;/\n[[:space:]]*$/d;s/.*\n//;}' ${source}
sed -i '/DECLARE_GLOBAL_DATA_PTR/d' ${source}
sed -i '/global_data.h/d' ${source}
git add ${source}
fi
fi
done
Peng Fan [Mon, 9 Feb 2026 01:30:13 +0000 (09:30 +0800)]
rockchip: evk_rk3308: Cleanup headers
There is no user of 'gd', so drop the usage of DECLARE_GLOBAL_DATA_PTR
and the including of 'asm/global_data.h'. Also include correct headers
to avoid build error.
x86/coreboot: Exclude memory regions starting above 4GB
This commit updates the RAM region filtering logic in
board_get_usable_ram_top() to skip any memory regions whose start address
is above 4GB. Previously, only the end address was capped at 4GB, but
regions entirely above this threshold were still considered.
Typically, the following memory map entries would cause
board_get_usable_ram_top() to return 0x100000000, which is incorrect.
By adding a check to continue the loop if the region's start address
exceeds 0xffffffffULL, the function now properly ignores regions that are
not usable in 32-bit address space.
Signed-off-by: Jeremy Compostella <jeremy.compostella@intel.com>
Since commit 27cc5951c862 ("include: env: ti: add default for
do_main_cpsw0_qsgmii_phyinit"), the value of the environment variable
do_main_cpsw0_qsgmii_phyinit happened to remain '0' and couldn't be
changed without user intervention. This behavior is due to the following
cyclic dependency:
A) ti_common.env sets do_main_cpsw0_qsgmii_phyinit to '0' and its value
can only be updated automatically by main_cpsw0_qsgmii_phyinit.
B) main_cpsw0_qsgmii_phyinit is defined in j721e.env and it can run only
if 'do_main_cpsw0_qsgmii_phyinit' is already '1' which isn't possible
unless the user manually assigns the value.
Fix the aforementioned cyclic dependency by using board_late_init() to
detect the QSGMII Daughtercard and set do_main_cpsw0_qsgmii_phyinit.
Additionally, to address the issue of do_main_cpsw0_qsgmii_phyinit being
'undefined' for other platforms, replace:
if test ${do_main_cpsw0_qsgmii_phyinit} -eq 1;
with:
if env exists do_main_cpsw0_qsgmii_phyinit;
in ti_common.env.
Martin Schwan [Wed, 11 Feb 2026 08:36:22 +0000 (09:36 +0100)]
bootstd: rauc: Fix null pointer access while checking root part
Fix a segmentation fault caused by a null pointer access during root
partition checking. The function part_get_info() was falsely given null
for the disk_partition struct, which later resulted in accessing a null
pointer and thus undefined behavior.
Fixes: 5d7c080ae5dc ("bootstd: rauc: Don't check root part filesystem") Signed-off-by: Martin Schwan <m.schwan@phytec.de>
James Hilliard [Thu, 12 Feb 2026 21:34:09 +0000 (14:34 -0700)]
image: fit: Apply overlays using aligned writable FDT copies
libfdt expects FDT/DTO blobs to be 8-byte aligned. When loading the
base FDT or overlays from a FIT, the mapped buffer may be unaligned,
which can break fdt_open_into() on strict-alignment architectures.
boot_get_fdt_fit() relocates the base FDT with boot_relocate_fdt()
before applying overlays. That uses the bootm memory map and can
overlap with the FIT buffer when the FIT is loaded into RAM,
corrupting data needed to load the kernel and ramdisk.
Allocate writable, 8-byte aligned copies of the base FDT and overlays
with memalign() and fdt_open_into(). Grow the base buffer as needed,
apply overlays to it and pack the final tree. Free each temporary
overlay copy after application and check fdt_pack() errors.
Fixes: 8fbcc0e0e839 ("boot: Assure FDT is always 8-byte aligned") Fixes: 881f0b77dc8c ("image: apply FDTOs on FDT image node") Signed-off-by: James Hilliard <james.hilliard1@gmail.com> Cc: Jamie Gibbons <Jamie.Gibbons@microchip.com> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
Tom Rini [Tue, 10 Feb 2026 17:13:44 +0000 (11:13 -0600)]
MAINTAINERS: Remove a few inactive people
It has been a long while since Jagan Teki, Joe Hershberger or Ramon
Fried have been active in the community. We thank them for their time
over the years. Remove them from the active maintainer list and mark a
few things as Orphaned for now.
An update on AB subsystem allowing multiple FWU metadata
storage drivers to be selected simultaneously instead of
being mutually exclusive. The board can then select the
appropriate driver at runtime based on the devicetree
description.
usb: cdns3: use VBUS Valid to determine role for dr_mode OTG
The cdns3_bind() function is responsible for identifying the appropriate
driver to bind to the USB Controller's device-tree node. If the device-tree
node has the 'dr_mode' property set to 'otg', the existing approach fails
to bind a driver, leading to loss of functionality.
To address this, use the VBUS Valid field of the OTG Status register to
determine the role as follows:
- If VBUS Valid field is set, it indicates that a USB Host is supplying
power and the Controller should assume the Peripheral role.
- If VBUS Valid field is clear, it indicates the absence of a USB Host and
the Controller should assume the Host role.
Additionally, when 'dr_mode' happens to be 'otg' and the STRAP settings
are not specified, use VBUS Valid to determine the role in cdns3_drd_init()
and assign it to cdns->dr_mode.
Signed-off-by: Siddharth Vadapalli <s-vadapalli@ti.com> Reviewed-by: Marek Vasut <marek.vasut@mailbox.org>
* Add MBR support to EFI_PARTITION_INFO_PROTOCOL
* disk: part_dos: Move header to the main include directory
* disk: part_dos: Align dos_partition_t with struct partition
* disk: part_efi: Remove redundant struct partition definition
* disk: part_dos: Document part_get_info_extended() helper function
* disk: part_dos: Refactor to allow retrieving raw MBR partition data
* efi_loader: disk: Extend EFI_PARTITION_INFO_PROTOCOL to support MBR
* efi_selftest: Enhance MBR test for PARTITION_INFO_PROTOCOL
* Prepare for supporting more stores (e.g. SPI-flash) for EFI variables.
* efi_var: Unify read/write access helper function
* efi_loader: Setup default location for UEFI Variables storing
* efi_var_file: refactor to move buffer functions
Michal Simek [Wed, 11 Feb 2026 15:56:22 +0000 (16:56 +0100)]
efi_loader: Setup default location for UEFI Variables storing
EFI_VARIABLE_FILE_STORE is only available when FAT_WRITE is enabled but
that's not valid for all platforms and dependency should be covered.
Also Kconfig behavior is that if default option is not valid then Kconfig
selects the first presented valid option instead hence it is better to
record EFI_VARIABLE_NO_STORE as safe default option.
Suggested-by: Tom Rini <trini@konsulko.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
Michal Simek [Wed, 11 Feb 2026 15:56:21 +0000 (16:56 +0100)]
efi_var: Unify read/write access helper function
efi_var_to/from_file() suggest method where variables are placed. But there
is no reason for it and generic name can be used to wire also different
locations for variables.
Signed-off-by: Michal Simek <michal.simek@amd.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905D3-CC Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
Shantur Rathore [Wed, 11 Feb 2026 15:56:20 +0000 (16:56 +0100)]
efi_var_file: refactor to move buffer functions
Currently efi_var_file.c has functions to store/read
EFI variables to/from memory buffer. These functions
can be used with other EFI variable stores so move
them out to efi_var_common.c
Signed-off-by: Shantur Rathore <i@shantur.com> Signed-off-by: Michal Simek <michal.simek@amd.com> Tested-by: Neil Armstrong <neil.armstrong@linaro.org> # on AML-S905D3-CC Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
efi_selftest: Enhance MBR test for PARTITION_INFO_PROTOCOL
The EFI_PARTITION_INFO_PROTOCOL test was added before the protocol fully
supported MBR partitions. As a result, it lacked specific checks for the
content of the raw MBR partition record.
Now that MBR support has been implemented, enhance the selftest to provide
coverage for the MBR entries too.
This verifies that the protocol correctly reads and exposes MBR partition
records and prevents this functionality to regress due future changes.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Acked-by: Ilias Apalodimas <ilias.apalodimas@linaro.org> Reviewed-by: Heinrich Schuchardt <heinrich.schuchardt@canonical.com>
efi_loader: disk: Extend EFI_PARTITION_INFO_PROTOCOL to support MBR
The EFI_PARTITION_INFO_PROTOCOL provides detailed information about
partitions. The UEFI specification mentions that both GPT and MBR
partition schemes are supported, but the U-Boot implementation only
supports the former.
This can cause compatibility issues for platforms whose boot ROM only
supports MBR. This change adds support for MBR partition tables to
the protocol, making U-Boot compatible with systems that require a
legacy MBR table.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
disk: part_dos: Refactor to allow retrieving raw MBR partition data
Refactor the part_get_info_extended() helper function (which already
recursively traverses DOS partitions) to optionally return the raw MBR
partition structure (dos_partition_t).
This allows other subsystems, such as EFI, to retrieve the partition
details in the legacy MBR format.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
disk: part_dos: Align dos_partition_t with struct partition
The dos_partition_t struct defined in part_dos.h is nearly identical to
the struct partition defined in part_efi.h. They differ primarily in how
define their starting sector and number of sectors fields.
The former uses unsigned char arrays while the latter uses __le32 types.
Using __le32 is preferable, as it removes the ambiguity and potential
misuse of a raw byte array. This also aligns the structure with how the
Linux kernel defines it nowadays, which is the original source of it.
To prepare for future consolidation where one of the data structures can
be removed, this change aligns both definitions and updates all accessors
for dos_partition_t.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
disk: part_dos: Move header to the main include directory
There are two different struct definitions for MBR partition table
entries: one in part_dos.h and a nearly identical one in part_efi.h.
To enable future consolidation of these two structures, move part_dos.h
to the main include directory. This makes it accessible from other parts
of the codebase, such as part_efi.h, and is the first step toward removing
the redundant definition.
Signed-off-by: Javier Martinez Canillas <javierm@redhat.com> Reviewed-by: Tom Rini <trini@konsulko.com> Reviewed-by: Ilias Apalodimas <ilias.apalodimas@linaro.org>
The size of the memory allocated for the EFI Conformance Profiles Table is
computed with `num_entries' always equal to zero, which is incorrect when
CONFIG_EFI_EBBR_2_1_CONFORMANCE is enabled.
This can be verified by allocating the ECPT memory with malloc() instead of
efi_allocate_pool(), building u-boot with sandbox_defconfig and
CONFIG_VALGRIND=y, and by finally running the following command:
Fix this by using an array of the supported profiles GUIDs instead, which
should also be easier to extend in the future as U-Boot should publish the
GUIDs for all supported EBBR revisions.
efi_loader: add missing EFI_CALL around tcg2 read_blocks calls
The read_blocks() function from the Block IO protocol is a UEFI function;
make sure to call it from within U-Boot using the EFI_CALL() macro.
To demonstrate the issue on an AArch64 machine, define the DEBUG macro in
include/efi_loader.h and build u-boot with sandbox_defconfig, then download
and uncompress the ACS-DT image [1], and finally execute the following
command:
Tom Rini [Sat, 14 Feb 2026 14:58:38 +0000 (08:58 -0600)]
Merge tag 'u-boot-socfpga-next-20260213' of https://source.denx.de/u-boot/custodians/u-boot-socfpga into next
This pull request updates SoCFPGA platforms with DDR improvements, new
board support, Agilex5 enhancements and general cleanup across the
codebase.
DDR and memory handling
* Add DRAM size checking support for Arria10.
* Widen MEM_TOTAL_CAPACITY mask handling in IOSSM mailbox driver.
* Assign unit address to memory node for improved memory
representation and consistency.
Agilex / Agilex5 updates
* Restore multi-DTB support for NAND boot and fix NAND clock handling.
* Enable SD card UHS mode and eMMC HS200/HS400 mode support on Agilex5.
* Fix DT property naming conventions for Agilex5.
* Exclude AGILEX_L4_SYS_FREE_CLK from clock enable/disable operations
to avoid unintended clock control.
New board support
* Add support for CoreCourse Cyclone V boards:
* AC501
* AC550
Including device trees, QTS configuration, defconfigs and maintainers
entries.
Fixes and cleanup
* Fix GEN5 handoff script path.
* Remove incorrect CONFIG_SPL_LDSCRIPT settings.
* Replace legacy TARGET namespace and perform related cleanup across
SoCFPGA code.
* General Kconfig, build and SoCFPGA maintenance updates.
Overall this pull request improves platform robustness, adds new board
coverage and cleans up legacy configuration usage across the SoCFPGA
U-Boot codebase.
[trini: Change TARGET_SOCFPGA_CYCLONE5 to ARCH_SOCFPGA_CYCLONE5 in the
new platforms this added] Signed-off-by: Tom Rini <trini@konsulko.com>
Tien Fong Chee [Fri, 13 Feb 2026 12:27:23 +0000 (20:27 +0800)]
Replace TARGET namespace and cleanup properly
TARGET namespace is for machines / boards / what-have-you that
building U-Boot for. Simply replace from TARGET to ARCH
make things more clear and proper for ALL SoCFPGA.
Signed-off-by: Brian Sune <briansune@gmail.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
# Conflicts:
# drivers/ddr/altera/Makefile
Brian Sune [Wed, 28 Jan 2026 14:18:16 +0000 (22:18 +0800)]
Add CoreCourse socfpga Board - AC550
CoreCourse Altera GEN5 Cyclone V board
do support different size and formfactor.
Now introducing AC550 C5 to mainstream u-boot
This is a more complex and unified board with
feature. More info on [1]
Brian Sune [Wed, 28 Jan 2026 14:18:15 +0000 (22:18 +0800)]
Add CoreCourse socfpga Board - AC501
CoreCourse Altera GEN5 Cyclone V board
do support different size and formfactor.
Now introducing AC501 C5 to mainstream u-boot
This is a UBGA-484 based board with basic
feature. More info on [1]
arm: agilex5: Enable eMMC HS200 and HS400 mode support
Enable high-speed eMMC modes on Agilex5 SoC development kit for
improved storage performance.
Defconfig changes:
- Enable CONFIG_MMC_HS400_SUPPORT and CONFIG_SPL_MMC_HS400_SUPPORT
Device tree changes:
- Add mmc-hs200-1_8v and mmc-hs400-1_8v capabilities
- Add sdhci-caps-mask to mask SDHCI_CLOCK_V3_BASE_MASK bits
- Add sdhci-caps to set 200MHz base clock and 8-bit bus width
- Add PHY and controller timing configuration for HS200 mode
- Add PHY and controller timing configuration for HS400 mode
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com> Acked-by: Tien Fong Chee <tien.fong.chee@altera.com>
Enable Ultra High Speed (UHS-I) mode support for SD cards on
Agilex5 SoC development kit.
Defconfig changes:
- Enable CONFIG_MMC_UHS_SUPPORT and CONFIG_SPL_MMC_UHS_SUPPORT
Device tree changes:
- Remove no-1-8-v to allow 1.8V signaling for UHS modes
- Add sd-uhs-sdr50 and sd-uhs-sdr104 capabilities
- Add sdhci-caps and sdhci-caps-mask for proper capability reporting
- Add PHY and controller timing configuration
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com> Acked-by: Tien Fong Chee <tien.fong.chee@altera.com>
Replace underscores with hyphens in the PHY timing configuration
property names to follow standard devicetree naming conventions:
- phy-gate-lpbk_ctrl-delay-sd-ds -> phy-gate-lpbk-ctrl-delay-sd-ds
- phy-gate-lpbk_ctrl-delay-sd-hs -> phy-gate-lpbk-ctrl-delay-sd-hs
Signed-off-by: Tanmay Kathpalia <tanmay.kathpalia@altera.com> Acked-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards, Tien
clk: altera: agilex: Exclude AGILEX_L4_SYS_FREE_CLK from enable/disable operations
AGILEX_L4_SYS_FREE_CLK is a free-running clock with no gate control in
hardware, therefore attempting to enable or disable it is not applicable.
Update the clock driver to explicitly exclude this clock ID from
enable/disable operations by returning -EOPNOTSUPP in bitmask_from_clk_id()
and treating this as a no-op in the socfpga_clk_enable() and
socfpga_clk_disable() functions.
This prevents unnecessary register access for clocks that cannot be gated
and ensures clean handling when the clock is present in the device tree.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Add DRAM size checking compare between size from device tree and actual
hardware.
Trigger hang if DRAM size from device tree is greater than actual hardware.
Display warning message if DRAM size mismatch between device tree and
actual hardware.
Signed-off-by: Alif Zakuan Yuslaimi <alif.zakuan.yuslaimi@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com> Best regards,
Dinesh Maniyam [Tue, 3 Feb 2026 07:56:53 +0000 (15:56 +0800)]
socfpga: agilex: fix NAND clock handling
In v2025.10, the Agilex clock driver was updated to support
clk_enable() and clk_disable() using clock-ID based bitmasks.
However, only AGILEX_NAND_CLK was implemented, while the NAND DT
node still referenced both nand and nand_x clocks.
Since AGILEX_NAND_X_CLK is not defined in the clock driver or the
clock-ID specification, clk_enable() failed during NAND probe.
As a result, the Denali NAND controller never completed
initialization.
Fix this by mapping the NAND X clock to the existing l4_mp clock
bitmask, aligning the DT expectations with the clock driver and
restoring proper NAND controller initialization.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Dinesh Maniyam [Tue, 3 Feb 2026 07:55:57 +0000 (15:55 +0800)]
arm: socfpga: agilex: restore Multi-DTB support for NAND boot
From v2025.10 onward, Agilex platforms use the upstream Linux device
tree sources instead of local copies.
To continue using a single defconfig while supporting NAND boot,
restore Multi-DTB support and update the DT paths to the upstream
intel directory.
NAND boot is configured to use FDT-1, while other boot flows
continue to use the default device tree.
No functional change is intended for non-NAND boot paths.
Signed-off-by: Dinesh Maniyam <dinesh.maniyam@altera.com> Reviewed-by: Tien Fong Chee <tien.fong.chee@altera.com>
Suhaas Joshi [Thu, 12 Feb 2026 10:28:47 +0000 (15:58 +0530)]
board: toradex: Make A53 get RAM size from DT in K3 boards
`dram_init()` is called by R5 SPL and U-Boot, both. It starts by
computing the size of the RAM. In verdin-am62(p), it does so by calling
`get_ram_size()`. This function computes the size of the RAM by writing
over the RAM.
When R5 computes the size of the RAM, it does not update the DT with
this size. As a result, when A53 invokes `dram_init()` again, it has to
compute the size through `get_ram_size()` again.
Commit 13c54cf588d82 and 0c3a6f748c9 add firewall over ATF's and OPTEE's
regions. This firewall is added during the R5 SPL stage of boot. So when
A53 attempts to write over RAM in `get_ram_size()`, it writes over the
protected region. Since A53 is a non-secure core, this is blocked by the
firewall.
To fix this, do the following:
* Implement `spl_perform_board_fixups()` function for verdin-am62
and verdin-am62p. Make this function call `fixup_memory_node()`,
which updates the DT.
* Add an if-block in `dram_init()`, to ensure that only R5 is able
to call `get_ram_size()`, and that A53 reads this size from the
DT.
Signed-off-by: Suhaas Joshi <s-joshi@ti.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Shiji Yang [Wed, 26 Nov 2025 01:37:41 +0000 (09:37 +0800)]
mtd: spi-nor-tiny: fix 4-Byte address instructions for Cypress and ISSI
In theory, for the same vendor, we should use the same instructions as
the spi-nor-core implementation.
Fixes: 72151ad10f8d ("mtd: spi-nor-core: Add Cypress manufacturer ID in set_4byte") Fixes: 5bf3f3dd11db ("mtd: spi-nor: Enable QE bit for ISSI flash") Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
mtd: spi-nor: winbond: Make sure w25q{01, 02}jv behave correctly
These chips are internally made of two/four dies with linear addressing
capabilities to make it transparent to the user that two/four dies were
used. There is one drawback however, the read status operation is racy
as the status bit only gives the active die status and not the status of
the other die. For commands affecting the two dies, it means if another
command is sent too fast after the first die has returned a valid
status (deviation can be up to 200us), the chip will get corrupted/in an
unstable state.
The solution adopted here is to iterate manually over all internal
dies (which takes about 30us per die) until all are ready. This approach
will always be faster than a blind delay which represents the maximum
deviation, while also being totally safe.
A flash-specific hook for the status register read had to be
implemented. Testing with the flash_speed benchmark in Linux shown no
difference with the existing performances (using the regular status read
core function).
As the presence of multiple dies is not filled in these chips SFDP
tables (the table containing the crucial information is optional), we
need to manually wire the hook.
Marek Vasut [Fri, 31 Oct 2025 22:43:42 +0000 (23:43 +0100)]
spi: Squash spi_slave_of_to_plat() into spi_child_post_bind()
The spi_slave_of_to_plat() is called from one place, spi_child_post_bind().
Squash it into the later and remove the public declaration, make this
function local static. No functional change.
Signed-off-by: Marek Vasut <marek.vasut+renesas@mailbox.org>
Shiji Yang [Wed, 26 Nov 2025 02:04:09 +0000 (10:04 +0800)]
mtd: spi-nor-ids: remove duplicate IDs for w25q32 and w25q512 series
Some Winbond Flash chips share the same device ID. Names are not that
important for the SPI Flash, hence we don't need these duplicate ID
definitions. And the Flash size of w25q512jv is actually wrong. Clean
them up to keep the source file tidy.
Signed-off-by: Shiji Yang <yangshiji66@outlook.com>
Kory Maincent [Wed, 14 Jan 2026 09:56:53 +0000 (10:56 +0100)]
fwu-mdata: Allow multiple metadata storage drivers to be enabled
Change the Kconfig from a "choice" to a conditional block, allowing
multiple FWU metadata storage drivers to be selected simultaneously
instead of being mutually exclusive.
This enables systems with FWU metadata on different storage types
(e.g., both GPT-partitioned block devices and MTD devices) to have
both drivers compiled in. The board can then select the appropriate
driver at runtime based on the devicetree description.
The change converts FWU_MDATA to a menuconfig and replaces the
"choice/endchoice" block with "if FWU_MDATA/endif", making
FWU_MDATA_GPT_BLK default to 'y' for backward compatibility.
Michal Simek [Tue, 3 Feb 2026 07:52:30 +0000 (08:52 +0100)]
gpio: Add GPIO delay driver
Add a GPIO controller driver that provides configurable delays when
setting GPIO output values. This is useful for hardware that requires
specific timing delays during power sequencing or GPIO state changes.
The driver wraps underlying GPIO controllers and adds programmable
ramp-up and ramp-down delays specified in microseconds through the
device tree. Each GPIO can have independent delay timings.
Michal Simek [Wed, 11 Feb 2026 08:30:06 +0000 (09:30 +0100)]
xilinx: mbv: Disable EFI loader
There is no intention to use EFI on Microblaze V that's why disable it to
save some space. Also it is indication that this feature is not
tested/supported.
Sean Anderson [Thu, 29 Jan 2026 18:40:11 +0000 (13:40 -0500)]
pinctrl: zynqmp: Add SPL support
Although the pinctrl pm requests are implemented in the PMU firmware,
PM_QUERY_DATA is actually implemented in ATF. In SPL (or when running in
EL3), ATF is not yet running, so we need to implement this API
ourselves. Do the bare minimum, allowing SPL to enumerate functions, but
don't bother with groups. Groups take up a lot of space, and can be
emulated with pins. For example, a node like
display-port {
mux {
groups = "dpaux0_1";
function = "dpaux0";
};
};
While this isn't backwards-compatible with existing devicetrees, it's
more than enough for SPL where we may only need to mux one or two pins.
Add SPL_PINCTRL_ZYNQMP to ensure there's no SPL size growth when pinctrl
is enabled in U-Boot but isn't necessary for SPL. The only config this
would affect is Kria, but SPL_PINCTRL_GENERIC is disabled so
SPL_PINCTRL_ZYNQMP is not selected.
Pranav Sanwal [Thu, 29 Jan 2026 12:00:21 +0000 (17:30 +0530)]
arm64: versal2: Populate DRAM banks before page table size calculation
Move DRAM bank detection from fdtdec to custom implementation to
ensure memory banks are populated before get_page_table_size() is
called during MMU initialization.
The current fdtdec-based approach populates gd->bd->bi_dram[] too
late in the boot sequence, causing get_page_table_size() to be
called with unpopulated DRAM information. This prevents dynamic
page table sizing based on actual memory configuration.
Parse /memory nodes in dram_init() to fill versal2_mem_map[]
early enough for MMU setup. Supports up to
CONFIG_NR_DRAM_BANKS (36) non-contiguous banks with high memory
regions (>4GB) and use __weak get_page_table_size implementation
to estimate page table size based on the populated DRAM banks.
Pranav Sanwal [Thu, 29 Jan 2026 12:00:20 +0000 (17:30 +0530)]
fdtdec: Add declaration for get_next_memory_node() helper
Add get_next_memory_node() function declaration to fdtdec.h to support
iterating through multiple memory nodes in device tree. This function
is used to enumerate memory banks when the system has non-contiguous
or multiple memory regions defined with device_type = "memory".
The function implementation already exists in lib/fdtdec.c (lines
1298-1305) but was missing the public declaration in the header file.
This patch adds the declaration and includes dm/ofnode_decl.h for the
ofnode type definition.
This is needed for platforms that require early memory enumeration
before standard fdtdec_setup_memory_banksize() is called, particularly
for dynamic MMU page table size calculation based on actual DRAM
configuration.
Pranav Tilak [Tue, 20 Jan 2026 11:00:56 +0000 (16:30 +0530)]
rtc: zynqmp: Add clock framework support with calibration fallback
Add support for reading RTC clock from device tree using clock
framework also update the default calibration value to 0x7FFF
as per RTC specifications.
Falls back to 'calibration' property if clock unavailable, and uses
default calibration if neither is present. Only writes calibration when
hardware register reads zero.
The calibration write previously in zynqmp_rtc_set() has been moved to
the probe function. The earlier implementation wrote calibration on
every time update to clear the tick counter, but since calibration is
now dynamically configured from clock framework or device tree during probe,
it only requires one-time initialization. This avoids repeated tick
counter resets and unnecessary overhead.
Suhaas Joshi [Thu, 12 Feb 2026 10:28:47 +0000 (15:58 +0530)]
board: toradex: Make A53 get RAM size from DT in K3 boards
`dram_init()` is called by R5 SPL and U-Boot, both. It starts by
computing the size of the RAM. In verdin-am62(p), it does so by calling
`get_ram_size()`. This function computes the size of the RAM by writing
over the RAM.
When R5 computes the size of the RAM, it does not update the DT with
this size. As a result, when A53 invokes `dram_init()` again, it has to
compute the size through `get_ram_size()` again.
Commit 13c54cf588d82 and 0c3a6f748c9 add firewall over ATF's and OPTEE's
regions. This firewall is added during the R5 SPL stage of boot. So when
A53 attempts to write over RAM in `get_ram_size()`, it writes over the
protected region. Since A53 is a non-secure core, this is blocked by the
firewall.
To fix this, do the following:
* Implement `spl_perform_board_fixups()` function for verdin-am62
and verdin-am62p. Make this function call `fixup_memory_node()`,
which updates the DT.
* Add an if-block in `dram_init()`, to ensure that only R5 is able
to call `get_ram_size()`, and that A53 reads this size from the
DT.
Signed-off-by: Suhaas Joshi <s-joshi@ti.com> Reviewed-by: Francesco Dolcini <francesco.dolcini@toradex.com>
Tom Rini [Wed, 11 Feb 2026 16:42:18 +0000 (10:42 -0600)]
Merge tag 'ab-next-11022026' of https://source.denx.de/u-boot/custodians/u-boot-tpm into next
Kory has updated the A/B implementation and added an invalid bank
state. This is already described in the spec and can help boards
boot faster by skipping banks marked as invalid
USB Gadget:
* dwc3: Support ip and version type
* dwc3: Increase controller halt timeout
* dwc3: Don't send unintended link state change
* dwc3: Improve reset sequence
* dwc2: Move dr_mode check to bind to support RK3288/RK3506 with
2 DWC2 controllers
Kory Maincent [Mon, 19 Jan 2026 16:07:42 +0000 (17:07 +0100)]
fwu: Mark failed bank as invalid during rollback
When boot_idx differs from active_idx at boot time, it indicates a
rollback scenario where the firmware update failed and the system
reverted to the previous working bank. In this case, mark the failed
bank (active_idx) as invalid to prevent future boot attempts from that
bank.
Kory Maincent [Mon, 19 Jan 2026 16:07:41 +0000 (17:07 +0100)]
fwu: Pass bank state enum to fwu_state_machine_updates()
Change fwu_state_machine_updates() to accept an enum fwu_bank_states
parameter instead of a boolean. This makes the function interface more
explicit and prepares for adding FWU_BANK_INVALID support to handle
boot failures on the active bank.
Convert the FWU_BANK_* defines to an enum and update all call sites
accordingly.
Heiko Schocher [Fri, 23 Jan 2026 02:25:51 +0000 (03:25 +0100)]
lib: sm3: fix coverity error
Coverity scan reported:
CID 449815: Memory - illegal accesses (OVERRUN)
Overrunning array of 64 bytes at byte offset 64 by dereferencing pointer
"sctx->buffer + partial". [Note: The source code implementation of the
function has been overridden by a builtin model.]
In line: 252
memset(sctx->buffer + partial, 0, SM3_BLOCK_SIZE - partial);
Pranav Tilak [Thu, 29 Jan 2026 08:10:54 +0000 (13:40 +0530)]
net: phy: mscc: Enable RMII clock output for VSC8541 PHY
Set RMII reference clock output to enabled (1) by default for VSC8541
PHY in RMII mode. The RMII specification requires a 50MHz reference
clock, and many board designs expect the PHY to provide this clock to
the MAC controller.
Previously, the driver defaulted rmii_clk_out to 0 (disabled) for all
interface modes, which caused the PHY to not output the required 50MHz
clock. This resulted in MAC-PHY communication failures and prevented
network operations like DHCP from working on RMII-configured boards.
This change alligns with the hardware power-up default behavior and
aligns with both the generic PHY driver and Linux MSCC PHY driver
implementations.
projects / thirdparty / u-boot.git / log
