Run the test with -q so that it works both on glibc-2.2 and 2.3. The
problem if -q is not used is that the lines "malloc/free: 1 allocs, 0
frees, 8 bytes allocated." have different counts depending on the
glibc version.
load_one_suppressions_file(): Make sure to finish reading
up-to-and-including the '}' when the number of callers is >=
VG_N_SUPP_CALLERS. (Jeffrey Stedfast)
The Pentium 4 recycles the CS segment override prefix (0x2E) to mean
'predict not taken' when it appears before a conditional branch.
Valgrind 1.9.6 doesn't know how to handle this. The appended patch
makes it ignore the prefix in this case, which should be safe.
A DS segment override means 'predict taken', but valgrind already
ignores that on a conditional branch, so nothing needs to be done.
Add memcheck client requests VALGRIND_GET_VBITS / VALGRIND_SET_VBITS
for fetching/setting metadata so that it can be sent between
unconnected address spaces (or whatever).
Julian Seward [Wed, 18 Jun 2003 23:30:14 +0000 (23:30 +0000)]
Make the CPUID helper really do cpuid, so that what is returned
depends on the host CPU. We no longer claim to be Werner Trobin's
P54C or any more recent variant thereof :-)
Julian Seward [Sun, 15 Jun 2003 22:28:05 +0000 (22:28 +0000)]
- Continue to clear up SSE insn emitters following recent cleanups re
G vs E register fields in encoding
- Add SSE3e_RegWr and use it to implement a case in MOVD.
Julian Seward [Sun, 15 Jun 2003 21:54:34 +0000 (21:54 +0000)]
Rename the SSE and MMX uinstrs which read/write integer registers, in
a way consistent with the position of the register field in the
instruction. In Intel encoding parlance, the G register is in bits
5,4,3 and the E register is bits 2,1,0, and so we adopt this scheme
consistently. Considering how much confusion this has caused me in
this recent bout of SSE hacking, consistent renaming can only be a
good thing. It makes it a lot easier to figure out if parts of the
SSE handling machinery are correct, or not.
Julian Seward [Sat, 14 Jun 2003 11:57:59 +0000 (11:57 +0000)]
When exiting with VgSrc_BbsDone (switching back to real CPU because
block execution count exceeded, debugging only), restore the signal
state before switching back rather than after. I no longer understand
why it had to be done afterwards. This simplifies vg_startup.S a bit.
Julian Seward [Thu, 12 Jun 2003 00:56:06 +0000 (00:56 +0000)]
Fill in a few more SSE/SSE2 insns, with current aim of being able to
run Qt-3.1 as built with "icc -xW" (P4 code generation). Hopefully by
now I've worked through most SSE/SSE2 conceptual nasties, and it's
mostly a question of filling in the gaps.
I think I might have created a bug of some kind with SSE3g_RegWr. My
current test app segfaults if I run without --optimise=no, which makes
me think I've written something erroneous in the UInstr predicates
controlling optimisation. I don't know what though.
Julian Seward [Tue, 27 May 2003 00:46:28 +0000 (00:46 +0000)]
Fix a design flaw in the SSE decoder. Remove duplication and
generally rationalise it as the structure of Intel's encoding scheme
becomes more apparent. Add a bunch more instructions.
Julian Seward [Mon, 26 May 2003 08:47:27 +0000 (08:47 +0000)]
Implement enough SSE/SSE2 insns so that all the GL demos in qt-3.1.0
work, when running on a P4 with an NVidia Vanta card and using
NVidia-supplied libGL.so.1.0.3123. Surprisingly this seems to require
only a minimal set of instructions. So far this is only with
--skin=none.
Using __PRETTY_FUNCTION__ and some macros, removed 148 lines of very repetitive
code (also removing the perennial problem of matching the error strings to the
functions they were in).
Added VALGRIND_MALLOCLIKE_BLOCK and VALGRIND_FREELIKE_BLOCK which allow you to
use a custom-allocator and detect almost as many errors as you could detect if
you used malloc/new/new[]. (eg. leaks detected, free errors, free mismatch,
etc).
Had to fiddle with mac_malloc_wrappers.c a bit to factor out the appropriate
code to be called from the client request handling code. Also had to add a
new element `MAC_AllocCustom' to the MAC_AllocKind type.
Also added a little documentation, and a regression test.
This commit fixes up the handling of shadow registers quite a bit.
Removed the SK_(written_shadow_regs_values)() function. Instead, skins that
use shadow regs can track the `post_regs_write_init' event, and set the shadow
regs from within it. This is much more flexible, since it allows each shadow
register to be set to a separate value if necessary. It also matches the new
shadow-reg-change events described below.
In the core, there were some places where the shadow regs were changed, and
skins had no way of knowing about it, which was a problem for some skins.
So I added a bunch of new events to notify skins about these:
Any skin that uses shadow regs should almost certainly track these events. The
post_reg_write_clientcall_return allows a skin to tailor the shadow reg of the
return value of a CLIENTCALL'd function appropriately; this is especially
useful when replacing malloc() et al.
Defined some macros that should be used *whenever the core changes the value of
a shadow register* :
SET_SYSCALL_RETVAL
SET_SIGNAL_EDX (maybe should be SET_SIGNAL_RETVAL? ... not sure)
SET_SIGNAL_ESP
SET_CLREQ_RETVAL
SET_CLCALL_RETVAL
SET_PTHREQ_ESP
SET_PTHREQ_RETVAL
These replace all the old SET_EAX and SET_EDX macros, and are added in a few
places where the shadow-reg update was missing.
Added shadow registers to the machine state saved/restored when signal handlers
are pushed/popped (they were missing).
Added skin-callable functions VG_(set_return_from_syscall_shadow)() and
VG_(get_exit_status_shadow)() which are useful and abstract away from which
registers the results are in.
Also, poll() changes %ebx (it's first argument) sometimes, I don't know why.
So we notify skins about that too (with the `post_reg_write_syscall_return'
event, which isn't ideal I guess...)
projects / thirdparty / valgrind.git / log
