]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/arm: Don't set HCR.RW for AArch32 only CPUs
authorPeter Maydell <peter.maydell@linaro.org>
Thu, 25 Sep 2025 11:57:23 +0000 (12:57 +0100)
committerPeter Maydell <peter.maydell@linaro.org>
Tue, 7 Oct 2025 09:32:21 +0000 (10:32 +0100)
commita23e719ca8e80d22eafe4b2b57833918d439fa0c
tree542aaf2b9d23aa19ca3775e2b9ad38bf2b9088b4
parenteb7abb4a719f93ddd56571bf91681044b4159399
target/arm: Don't set HCR.RW for AArch32 only CPUs

In commit 39ec3fc0301 we fixed a bug where we were not implementing
HCR_EL2.RW as RAO/WI for CPUs where EL1 doesn't support AArch32.
However, we got the condition wrong, so we now set this bit even on
CPUs which have no AArch64 support at all.  This is wrong because the
AArch32 HCR register defines this bit as RES0.

Correct the condition we use for forcing HCR_RW to be set.

Cc: qemu-stable@nongnu.org
Resolves: https://gitlab.com/qemu-project/qemu/-/issues/3128
Fixes: 39ec3fc0301 ("target/arm: HCR_EL2.RW should be RAO/WI if EL1 doesn't support AArch32")
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20250925115723.1293233-1-peter.maydell@linaro.org
target/arm/helper.c