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x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN
authorTony Luck <tony.luck@intel.com>
Fri, 19 Mar 2021 17:39:19 +0000 (10:39 -0700)
committerIngo Molnar <mingo@kernel.org>
Sat, 20 Mar 2021 11:12:10 +0000 (12:12 +0100)
commita331f5fdd36dba1ffb0239a4dfaaf1df91ff1aab
treee185837b47cc1d234605420fe76c7ceac8853424tree | snapshot
parent301cddc21a157a3072d789a3097857202e550a24commit | diff
x86/mce: Add Xeon Sapphire Rapids to list of CPUs that support PPIN

New CPU model, same MSRs to control and read the inventory number.

Signed-off-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Link: https://lore.kernel.org/r/20210319173919.291428-1-tony.luck@intel.com
arch/x86/kernel/cpu/mce/intel.c diff | blob | blame | history
Mirror https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git