]> git.ipfire.org Git - thirdparty/qemu.git/commit
target/riscv: Fix the mepc when sspopchk triggers the exception
authorJim Shu <jim.shu@sifive.com>
Wed, 24 Sep 2025 07:48:16 +0000 (15:48 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Fri, 3 Oct 2025 03:15:14 +0000 (13:15 +1000)
commitc851052a77fd79300708df2070297b5428b4be8d
treecbd7db1f51c0d56b28f2fe3be17c222ba8479ed2
parenta86d3352ab70f33f5feabbf9bad9450d3c19d0bf
target/riscv: Fix the mepc when sspopchk triggers the exception

When sspopchk is in the middle of TB and triggers the SW check
exception, it should update PC from gen_update_pc(). If not, RISC-V mepc
CSR will get wrong PC address which is still at the start of TB.

Signed-off-by: Jim Shu <jim.shu@sifive.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-ID: <20250924074818.230010-2-jim.shu@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
target/riscv/insn_trans/trans_rvzicfiss.c.inc