AArch64: Extend intrinsics framework to account for merging predications without...

AArch64: Extend intrinsics framework to account for merging predications without gp [PR121604]

In PR121604 the problem was noted that currently the SVE intrinsics
infrastructure assumes that for any predicated operation that the GP is at the
first argument position which has a svbool_t or for a unary merging operation
that it's in the second position.

However you have intrinsics like fmov_lane which have an svbool_t but it's not
a GP but instead it's the inactive lanes.

You also have instructions like BRKB which work only on predicates so it
incorrectly determines the first operand to be the GP, while that's also the
inactive lanes.

However during apply_predication we do have the information about where the GP
is.  This patch re-organizes the code to record this information into the
function_instance such that folders have access to this information.

For functions that are outliers like pmov_lane we can now override the
availability of the intrinsics having a GP.

gcc/ChangeLog:

	PR target/121604
	* config/aarch64/aarch64-sve-builtins-shapes.cc (apply_predication):
	Store gp_index.
	(struct pmov_to_vector_lane_def): Mark instruction as has no GP.
	* config/aarch64/aarch64-sve-builtins.h (function_instance::gp_value,
	function_instance::inactive_values, function_instance::gp_index,
	function_shape::has_gp_argument_p): New.
	* config/aarch64/aarch64-sve-builtins.cc (gimple_folder::fold_pfalse):
	Simplify code and use GP helpers.

gcc/testsuite/ChangeLog:

	PR target/121604
	* gcc.target/aarch64/sve/pr121604_brk.c: New test.
	* gcc.target/aarch64/sve2/pr121604_pmov.c: New test.

Co-authored-by: Jennifer Schmitz <jschmitz@nvidia.com>