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(parent: 07d16e4) | patch
zynqmp: Fix veloce for RTL5.4
authorMichal Simek <michal.simek@xilinx.com>
Mon, 20 Apr 2015 12:07:00 +0000 (14:07 +0200)
committerMichal Simek <michal.simek@xilinx.com>
Thu, 23 Apr 2015 10:04:37 +0000 (12:04 +0200)
commitdc6795b3604e1a1533e7f9eabe31a70c0fef16b4
tree470b28595a4a46f5319cb906f586406f01b4c4f9tree | snapshot
parent07d16e4ff194c4cd8e5b939561d0c11e20a777dbcommit | diff
zynqmp: Fix veloce for RTL5.4

Command:
DTS file has changed a little bit that's why fix veloce
booting command to reflect these changes.
Do not use fdt_addr variable and hardcode FDT address because it is used
in Veloce boot script.
Also fix uart baudrate setup to use 4800bps and 48kHz input clock based
on Veloce 5.4 spec.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
arch/arm/cpu/armv8/zynqmp/clk.c diff | blob | blame | history
board/xilinx/zynqmp/zynqmp.c diff | blob | blame | history
drivers/serial/serial_zynq.c diff | blob | blame | history
include/configs/xilinx_zynqmp.h diff | blob | blame | history
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