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target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss...
authorMax Chou <max.chou@sifive.com>
Tue, 8 Apr 2025 10:39:32 +0000 (18:39 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 19 May 2025 03:38:50 +0000 (13:38 +1000)
commitfbeaf35838768086b435833cb4dc5182c73ec2bc
tree1063db6b129bede726277478520a660f0356152dtree | snapshot
parent629c2a8dd7506e1cb9b6b7127604641632ac453fcommit | diff
target/riscv: rvv: Apply vext_check_input_eew to OPIVI/OPIVX/OPFVF(vext_check_ss) instructions

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-5-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git