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target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions
authorMax Chou <max.chou@sifive.com>
Tue, 8 Apr 2025 10:39:33 +0000 (18:39 +0800)
committerAlistair Francis <alistair.francis@wdc.com>
Mon, 19 May 2025 03:38:56 +0000 (13:38 +1000)
commitfda68acb7761af40df78db18e44ca1ff20195fe0
treef4b84140b62fee7c0d548ac8845e1f79474018adtree | snapshot
parentfbeaf35838768086b435833cb4dc5182c73ec2bccommit | diff
target/riscv: rvv: Apply vext_check_input_eew to OPIVV/OPFVV(vext_check_sss) instructions

Handle the overlap of source registers with different EEWs.

Co-authored-by: Anton Blanchard <antonb@tenstorrent.com>
Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
Signed-off-by: Max Chou <max.chou@sifive.com>
Message-ID: <20250408103938.3623486-6-max.chou@sifive.com>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
Cc: qemu-stable@nongnu.org
target/riscv/insn_trans/trans_rvv.c.inc diff | blob | blame | history
Mirror of https://git.qemu.org/git/qemu.git