From 030778ab8d22cb52c53560d04ad3649cae4e18ff Mon Sep 17 00:00:00 2001 From: =?utf8?q?Ville=20Syrj=C3=A4l=C3=A4?= Date: Fri, 19 Sep 2025 22:29:54 +0300 Subject: [PATCH] drm/i915: Extract increase_wm_latency() MIME-Version: 1.0 Content-Type: text/plain; charset=utf8 Content-Transfer-Encoding: 8bit Extract the "increase wm latencies by some amount" code into a helper that can be reused. Reviewed-by: Luca Coelho Signed-off-by: Ville Syrjälä Link: https://patchwork.freedesktop.org/patch/msgid/20250919193000.17665-8-ville.syrjala@linux.intel.com --- drivers/gpu/drm/i915/display/skl_watermark.c | 28 ++++++++++++-------- 1 file changed, 17 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/display/skl_watermark.c b/drivers/gpu/drm/i915/display/skl_watermark.c index 1ac94cb4f27d8..98ca592f6042e 100644 --- a/drivers/gpu/drm/i915/display/skl_watermark.c +++ b/drivers/gpu/drm/i915/display/skl_watermark.c @@ -3183,6 +3183,21 @@ static void multiply_wm_latency(struct intel_display *display, int mult) wm[level] *= mult; } +static void increase_wm_latency(struct intel_display *display, int inc) +{ + u16 *wm = display->wm.skl_latency; + int level, num_levels = display->wm.num_levels; + + wm[0] += inc; + + for (level = 1; level < num_levels; level++) { + if (wm[level] == 0) + break; + + wm[level] += inc; + } +} + static bool need_16gb_dimm_wa(struct intel_display *display) { const struct dram_info *dram_info = intel_dram_info(display->drm); @@ -3207,7 +3222,6 @@ adjust_wm_latency(struct intel_display *display) { u16 *wm = display->wm.skl_latency; int i, level, num_levels = display->wm.num_levels; - int read_latency = wm_read_latency(display); if (display->platform.dg2) multiply_wm_latency(display, 2); @@ -3232,16 +3246,8 @@ adjust_wm_latency(struct intel_display *display) * to add proper adjustment to each valid level we retrieve * from the punit when level 0 response data is 0us. */ - if (wm[0] == 0) { - wm[0] += read_latency; - - for (level = 1; level < num_levels; level++) { - if (wm[level] == 0) - break; - - wm[level] += read_latency; - } - } + if (wm[0] == 0) + increase_wm_latency(display, wm_read_latency(display)); /* * WA Level-0 adjustment for 16Gb+ DIMMs: SKL+ -- 2.47.3